VARCem/PTV_Archive
1
0
Fork 0
mirror of https://github.com/VARCem/PTV_Archive.git synced 2026-07-09 02:26:31 +00:00
Code Issues Packages Projects Releases Wiki Activity
Files
main
PTV_Archive/PT5212/source-code/config.LST
Karsten Hansen e89983d50f New files developed by DK
2022-02-21 17:51:05 +01:00

290 lines
16 KiB
Plaintext
Raw Permalink Blame History

This file contains invisible Unicode characters
This file contains invisible Unicode characters that are indistinguishable to humans but may be processed differently by a computer. If you think that this is intentional, you can safely ignore this warning. Use the Escape button to reveal them.
C51 COMPILER V7.05 CONFIG 06/04/2007 16:18:34 PAGE 1
C51 COMPILER V7.05, COMPILATION OF MODULE CONFIG
OBJECT MODULE PLACED IN config.OBJ
COMPILER INVOKED BY: C:\Program Files\silabs\IDEfiles\C51\Bin\C51.EXE config.c DB OE
stmt level source
1 //---------------------------------------------------------------
2 // CYGNAL Integrated Products
3 //
4 // C Code Configuration Tool: F320 INITIALIZATION/CONFIGURATION CODE
5 //----------------------------------------------------------------
6 // This file is read only. To insert the code into your
7 // application, simply cut and paste or use the "Save As"
8 // command in the file menu to save the file in your project
9 // directory.
10 //----------------------------------------------------------------
11
12 //----------------------------------------------------------------
13 // INCLUDES
14 //----------------------------------------------------------------
15
16 #include <C8051F320.h> // Register definition file.
17
18 //------------------------------------------------------------------------------------
19 // Global CONSTANTS
20 //------------------------------------------------------------------------------------
21
22 //------------------------------------------------------------------------------------
23 // Function PROTOTYPES
24 //------------------------------------------------------------------------------------
25
26 //------------------------------------------------------------------------------------
27 // Config Routine
28 //------------------------------------------------------------------------------------
29 void config (void) {
30 1
31 1 //Local Variable Definitions
32 1
33 1
34 1
35 1 //----------------------------------------------------------------
36 1 // CROSSBAR REGISTER CONFIGURATION
37 1 //
38 1 // NOTE: The crossbar register should be configured before any
39 1 // of the digital peripherals are enabled. The pinout of the
40 1 // device is dependent on the crossbar configuration so caution
41 1 // must be exercised when modifying the contents of the XBR0,
42 1 // XBR1 registers. For detailed information on
43 1 // Crossbar Decoder Configuration, refer to Application Note
44 1 // AN001, "Configuring the Port I/O Crossbar Decoder".
45 1 //----------------------------------------------------------------
46 1
47 1 // Configure the XBRn Registers
48 1
49 1 XBR0 = 0x00; // Crossbar Register 1
50 1 XBR1 = 0x00; // Crossbar Register 2
51 1 // Select Pin I/0
52 1
53 1 // NOTE: Some peripheral I/O pins can function as either inputs or
54 1 // outputs, depending on the configuration of the peripheral. By default,
55 1 // the configuration utility will configure these I/O pins as push-pull
C51 COMPILER V7.05 CONFIG 06/04/2007 16:18:34 PAGE 2
56 1 // outputs.
57 1 // Port configuration (1 = Push Pull Output)
58 1 P0MDOUT = 0x00; // Output configuration for P0
59 1 P1MDOUT = 0x00; // Output configuration for P1
60 1 P2MDOUT = 0x00; // Output configuration for P2
61 1 P3MDOUT = 0x00; // Output configuration for P3
62 1
63 1 P0MDIN = 0xFF; // Input configuration for P0
64 1 P1MDIN = 0xFF; // Input configuration for P1
65 1 P2MDIN = 0xFF; // Input configuration for P2
66 1 P3MDIN = 0xFF; // Input configuration for P3
67 1
68 1 P0SKIP = 0x00; // Port 0 Crossbar Skip Register
69 1 P1SKIP = 0x00; // Port 1 Crossbar Skip Register
70 1 P2SKIP = 0x00; // Port 2 Crossbar Skip Register
71 1
72 1 // View port pinout
73 1
74 1 // The current Crossbar configuration results in the
75 1 // following port pinout assignment:
76 1 // Port 0
77 1 // P0.0 = unassigned (Open-Drain Output/Input)(Digital)
78 1 // P0.1 = unassigned (Open-Drain Output/Input)(Digital)
79 1 // P0.2 = unassigned (Open-Drain Output/Input)(Digital)
80 1 // P0.3 = unassigned (Open-Drain Output/Input)(Digital)
81 1 // P0.4 = unassigned (Open-Drain Output/Input)(Digital)
82 1 // P0.5 = unassigned (Open-Drain Output/Input)(Digital)
83 1 // P0.6 = unassigned (Open-Drain Output/Input)(Digital)
84 1 // P0.7 = unassigned (Open-Drain Output/Input)(Digital)
85 1
86 1 // Port 1
87 1 // P1.0 = unassigned (Open-Drain Output/Input)(Digital)
88 1 // P1.1 = unassigned (Open-Drain Output/Input)(Digital)
89 1 // P1.2 = unassigned (Open-Drain Output/Input)(Digital)
90 1 // P1.3 = unassigned (Open-Drain Output/Input)(Digital)
91 1 // P1.4 = unassigned (Open-Drain Output/Input)(Digital)
92 1 // P1.5 = unassigned (Open-Drain Output/Input)(Digital)
93 1 // P1.6 = unassigned (Open-Drain Output/Input)(Digital)
94 1 // P1.7 = unassigned (Open-Drain Output/Input)(Digital)
95 1
96 1 // Port 2
97 1 // P2.0 = unassigned (Open-Drain Output/Input)(Digital)
98 1 // P2.1 = unassigned (Open-Drain Output/Input)(Digital)
99 1 // P2.2 = unassigned (Open-Drain Output/Input)(Digital)
100 1 // P2.3 = unassigned (Open-Drain Output/Input)(Digital)
101 1 // P2.4 = unassigned (Open-Drain Output/Input)(Digital)
102 1 // P2.5 = unassigned (Open-Drain Output/Input)(Digital)
103 1 // P2.6 = unassigned (Open-Drain Output/Input)(Digital)
104 1 // P2.7 = unassigned (Open-Drain Output/Input)(Digital)
105 1
106 1 // Port 3
107 1 // P3.0 = unassigned (Open-Drain Output/Input)(Digital)
108 1
109 1 //----------------------------------------------------------------
110 1 // Comparator Register Configuration
111 1 //----------------------------------------------------------------
112 1
113 1 CPT0MX = 0x00; // Comparator 0 MUX Selection Register
114 1 CPT0MD = 0x02; // Comparator 0 Mode Selection Register
115 1 CPT0CN = 0x00; // Comparator 0 Control Register
116 1
117 1 CPT1MX = 0x00; // Comparator 1 MUX Selection Register
C51 COMPILER V7.05 CONFIG 06/04/2007 16:18:34 PAGE 3
118 1 CPT1MD = 0x02; // Comparator 1 Mode Selection Register
119 1 CPT1CN = 0x00; // Comparator 1 Control Register
120 1
121 1 //----------------------------------------------------------------
122 1 // Oscillator Configuration
123 1 //----------------------------------------------------------------
124 1
125 1 OSCXCN = 0x00; // EXTERNAL Oscillator Control Register
126 1 CLKSEL = 0x00; // Oscillator Clock Select Register
127 1 OSCICN = 0x80; // Internal Oscillator Control Register
128 1
129 1 //----------------------------------------------------------------
130 1 // SPI Configuration
131 1 //----------------------------------------------------------------
132 1
133 1 SPI0CFG = 0x00; // SPI Configuration Register
134 1 SPI0CKR = 0x00; // SPI Clock Rate Register
135 1 SPI0CN = 0x00; // SPI Control Register
136 1
137 1
138 1 //----------------------------------------------------------------
139 1 // Reference Control Register Configuration
140 1 //----------------------------------------------------------------
141 1
142 1 REF0CN = 0x00; // Reference Control Register
143 1
144 1 //----------------------------------------------------------------
145 1 // ADC Configuration
146 1 //----------------------------------------------------------------
147 1
148 1 AMX0P = 0x00; // AMX0 Positive Select Register
149 1 AMX0N = 0x00; // AMX0 Negative Select Register
150 1 ADC0CF = 0xF8; // ADC Configuration Register
151 1 ADC0CN = 0x00; // ADC Control Register
152 1
153 1 ADC0H = 0x00; // ADC Data MSB
154 1 ADC0L = 0x00; // ADC Data LSB
155 1 ADC0LTH = 0x00; // ADC Less-Than High Byte Register
156 1 ADC0LTL = 0x00; // ADC Less-Than Low Byte Register
157 1 ADC0GTH = 0xFF; // ADC Greater-Than High Byte Register
158 1 ADC0GTL = 0xFF; // ADC Greater-Than Low Byte Register
159 1
160 1 //----------------------------------------------------------------
161 1 // UART0 Configuration
162 1 //----------------------------------------------------------------
163 1
164 1 SCON0 = 0x00; // Serial Port Control Register
165 1
166 1 PCON = 0x00; // Power Control Register
167 1
168 1 //----------------------------------------------------------------
169 1 // SMBus Configuration
170 1 //----------------------------------------------------------------
171 1
172 1 SMB0CF = 0x00; // SMBus Configuration Register
173 1 SMB0DAT = 0x00; // SMBus Data Register
174 1 SMB0CN = 0x00; // SMBus Control Register
175 1
176 1 //----------------------------------------------------------------
177 1 // PCA Configuration
178 1 //----------------------------------------------------------------
179 1
C51 COMPILER V7.05 CONFIG 06/04/2007 16:18:34 PAGE 4
180 1 PCA0MD = 0x00; // PCA Mode Register
181 1 PCA0L = 0x00; // PCA Counter/Timer Low Byte
182 1 PCA0H = 0x00; // PCA Counter/Timer High Byte
183 1 PCA0CN = 0x00; // PCA Control Register
184 1
185 1
186 1 //Module 0
187 1 PCA0CPM0 = 0x00; // PCA Capture/Compare Register 0
188 1 PCA0CPL0 = 0x00; // PCA Counter/Timer Low Byte
189 1 PCA0CPH0 = 0x00; // PCA Counter/Timer High Byte
190 1
191 1 //Module 1
192 1 PCA0CPM1 = 0x00; // PCA Capture/Compare Register 1
193 1 PCA0CPL1 = 0x00; // PCA Counter/Timer Low Byte
194 1 PCA0CPH1 = 0x00; // PCA Counter/Timer High Byte
195 1
196 1 //Module 2
197 1 PCA0CPM2 = 0x00; // PCA Capture/Compare Register 2
198 1 PCA0CPL2 = 0x00; // PCA Counter/Timer Low Byte
199 1 PCA0CPH2 = 0x00; // PCA Counter/Timer High Byte
200 1
201 1 //Module 3
202 1 PCA0CPM3 = 0x00; // PCA Capture/Compare Register 3
203 1 PCA0CPL3 = 0x00; // PCA Counter/Timer Low Byte
204 1 PCA0CPH3 = 0x00; // PCA Counter/Timer High Byte
205 1
206 1 //Module 4
207 1 PCA0CPM4 = 0x00; // PCA Capture/Compare Register 4
208 1 PCA0CPL4 = 0x00; // PCA Counter/Timer Low Byte
209 1 PCA0CPH4 = 0x00; // PCA Counter/Timer High Byte
210 1
211 1 //----------------------------------------------------------------
212 1 // Timers Configuration
213 1 //----------------------------------------------------------------
214 1
215 1 CKCON = 0x02; // Clock Control Register
216 1 TL0 = 0x00; // Timer 0 Low Byte
217 1 TL1 = 0x00; // Timer 1 Low Byte
218 1 TH0 = 0x00; // Timer 0 High Byte
219 1 TH1 = 0x00; // Timer 1 High Byte
220 1 TMOD = 0x02; // Timer Mode Register
221 1 TCON = 0x00; // Timer Control Register
222 1
223 1 TMR2RLL = 0x00; // Timer 2 Reload Register Low Byte
224 1 TMR2RLH = 0x00; // Timer 2 Reload Register High Byte
225 1 TMR2L = 0x00; // Timer 2 Low Byte
226 1 TMR2H = 0x00; // Timer 2 High Byte
227 1 TMR2CN = 0x00; // Timer 2 Control Register
228 1
229 1 TMR3RLL = 0x00; // Timer 3 Reload Register Low Byte
230 1 TMR3RLH = 0x00; // Timer 3 Reload Register High Byte
231 1 TMR3L = 0x00; // Timer 3 Low Byte
232 1 TMR3H = 0x00; // Timer 3 High Byte
233 1 TMR3CN = 0x00; // Timer 3 Control Register
234 1
235 1 //----------------------------------------------------------------
236 1 // Reset Source Configuration
237 1 // NOTE! : Comparator 0 must be enabled before it is enabled as a
238 1 // reset source.
239 1 //------------------------------------------------------------------
240 1
241 1 RSTSRC = 0x00; // Reset Source Register
C51 COMPILER V7.05 CONFIG 06/04/2007 16:18:34 PAGE 5
242 1
243 1
244 1 //----------------------------------------------------------------
245 1 // Interrupt Configuration
246 1 //----------------------------------------------------------------
247 1
248 1 IE = 0x02; //Interrupt Enable
249 1 IP = 0x00; //Interrupt Priority
250 1 EIE1 = 0x00; //EXtended Interrupt Enable
251 1 // EIP1 = 0x00; //EXtended Interrupt Priority
252 1 IT01CF = 0x01; //INT0/INT1 Configuration Register
253 1
254 1 // other initialization code here...
255 1
256 1
257 1
258 1 } //End of config
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 180 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = ---- ----
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
Reference in New Issue View Git Blame Copy Permalink