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https://github.com/aaru-dps/Aaru.Checksums.Native.git
synced 2025-12-16 19:24:29 +00:00
Implement Fletcher-32 using ARM NEON instructions.
This commit is contained in:
@@ -71,6 +71,6 @@ if("${CMAKE_BUILD_TYPE}" MATCHES "Release")
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endif()
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endif()
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add_library("Aaru.Checksums.Native" SHARED adler32.h adler32.c crc16.h crc16.c crc16_ccitt.h crc16_ccitt.c crc32.c crc32.h crc64.c crc64.h fletcher16.h fletcher16.c fletcher32.h fletcher32.c library.h spamsum.c spamsum.h crc32_clmul.c crc64_clmul.c simd.c simd.h adler32_ssse3.c adler32_avx2.c adler32_neon.c crc32_arm_simd.c crc32_vmull.c crc32_simd.h arm_vmull.c arm_vmull.h crc64_vmull.c library.c)
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add_library("Aaru.Checksums.Native" SHARED adler32.h adler32.c crc16.h crc16.c crc16_ccitt.h crc16_ccitt.c crc32.c crc32.h crc64.c crc64.h fletcher16.h fletcher16.c fletcher32.h fletcher32.c fletcher32_neon.c library.h spamsum.c spamsum.h crc32_clmul.c crc64_clmul.c simd.c simd.h adler32_ssse3.c adler32_avx2.c adler32_neon.c crc32_arm_simd.c crc32_vmull.c crc32_simd.h arm_vmull.c arm_vmull.h crc64_vmull.c library.c)
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add_subdirectory(tests)
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@@ -46,6 +46,15 @@ AARU_EXPORT int AARU_CALL fletcher32_update(fletcher32_ctx* ctx, const uint8_t*
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{
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if(!ctx || !data) return -1;
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#if defined(__aarch64__) || defined(_M_ARM64) || ((defined(__arm__) || defined(_M_ARM)) && !defined(__MINGW32__))
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if(have_neon())
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{
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fletcher32_neon(&ctx->sum1, &ctx->sum2, data, len);
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return 0;
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}
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#endif
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uint32_t sum1 = ctx->sum1;
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uint32_t sum2 = ctx->sum2;
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unsigned n;
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@@ -34,4 +34,10 @@ AARU_EXPORT int AARU_CALL fletcher32_update(fletcher32_ctx* ctx, con
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AARU_EXPORT int AARU_CALL fletcher32_final(fletcher32_ctx* ctx, uint32_t* checksum);
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AARU_EXPORT void AARU_CALL fletcher32_free(fletcher32_ctx* ctx);
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#if defined(__aarch64__) || defined(_M_ARM64) || defined(__arm__) || defined(_M_ARM)
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AARU_EXPORT void AARU_CALL fletcher32_neon(uint16_t* sum1, uint16_t* sum2, const uint8_t* data, uint32_t len);
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#endif
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#endif // AARU_CHECKSUMS_NATIVE_FLETCHER32_H
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199
fletcher32_neon.c
Normal file
199
fletcher32_neon.c
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@@ -0,0 +1,199 @@
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/*
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* This file is part of the Aaru Data Preservation Suite.
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* Copyright (c) 2019-2023 Natalia Portillo.
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* Copyright 2017 The Chromium Authors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following disclaimer
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* in the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Google Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#if defined(__aarch64__) || defined(_M_ARM64) || ((defined(__arm__) || defined(_M_ARM)))
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#include <arm_neon.h>
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#include "library.h"
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#include "fletcher32.h"
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#include "simd.h"
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TARGET_WITH_SIMD /***/
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/**
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* @brief Compute the Fletcher-32 checksum using NEON instructions.
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*
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* @param[out] sum1 Pointer to the first sum value.
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* @param[out] sum2 Pointer to the second sum value.
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* @param[in] data Pointer to the input data.
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* @param[in] len The length of the input data.
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*/
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void fletcher32_neon(uint16_t *sum1, uint16_t *sum2, const uint8_t *data, uint32_t len) {
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/*
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* Split Fletcher-32 into component sums.
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*/
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uint32_t s1 = *sum1;
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uint32_t s2 = *sum2;
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/*
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* Serially compute s1 & s2, until the data is 16-byte aligned.
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*/
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if ((uintptr_t) data & 15) {
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while ((uintptr_t) data & 15) {
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s2 += (s1 += *data++);
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--len;
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}
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if (s1 >= FLETCHER32_MODULE) s1 -= FLETCHER32_MODULE;
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s2 %= FLETCHER32_MODULE;
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}
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/*
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* Process the data in blocks.
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*/
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const unsigned BLOCK_SIZE = 1 << 5;
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uint32_t blocks = len / BLOCK_SIZE;
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len -= blocks * BLOCK_SIZE;
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while (blocks) {
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unsigned n = NMAX / BLOCK_SIZE; /* The NMAX constraint. */
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if (n > blocks) n = (unsigned) blocks;
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blocks -= n;
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/*
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* Process n blocks of data. At most NMAX data bytes can be
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* processed before s2 must be reduced modulo FLETCHER32_MODULE.
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*/
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#ifdef _MSC_VER
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uint32x4_t v_s2 = {.n128_u32 = {0, 0, 0, s1 * n}};
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uint32x4_t v_s1 = {.n128_u32 = {0, 0, 0, 0}};
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#else
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uint32x4_t v_s2 = (uint32x4_t) {0, 0, 0, s1 * n};
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uint32x4_t v_s1 = (uint32x4_t) {0, 0, 0, 0};
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#endif
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uint16x8_t v_column_sum_1 = vdupq_n_u16(0);
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uint16x8_t v_column_sum_2 = vdupq_n_u16(0);
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uint16x8_t v_column_sum_3 = vdupq_n_u16(0);
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uint16x8_t v_column_sum_4 = vdupq_n_u16(0);
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do {
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/*
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* Load 32 input bytes.
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*/
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const uint8x16_t bytes1 = vld1q_u8((uint8_t *) (data));
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const uint8x16_t bytes2 = vld1q_u8((uint8_t *) (data + 16));
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/*
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* Add previous block byte sum to v_s2.
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*/
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v_s2 = vaddq_u32(v_s2, v_s1);
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/*
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* Horizontally add the bytes for s1.
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*/
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v_s1 = vpadalq_u16(v_s1, vpadalq_u8(vpaddlq_u8(bytes1), bytes2));
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/*
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* Vertically add the bytes for s2.
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*/
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v_column_sum_1 = vaddw_u8(v_column_sum_1, vget_low_u8(bytes1));
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v_column_sum_2 = vaddw_u8(v_column_sum_2, vget_high_u8(bytes1));
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v_column_sum_3 = vaddw_u8(v_column_sum_3, vget_low_u8(bytes2));
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v_column_sum_4 = vaddw_u8(v_column_sum_4, vget_high_u8(bytes2));
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data += BLOCK_SIZE;
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} while (--n);
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v_s2 = vshlq_n_u32(v_s2, 5);
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/*
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* Multiply-add bytes by [ 32, 31, 30, ... ] for s2.
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*/
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#ifdef _MSC_VER
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#ifdef _M_ARM64
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v_s2 = vmlal_u16(v_s2, vget_low_u16(v_column_sum_1), neon_ld1m_16((uint16_t[]) {32, 31, 30, 29}));
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v_s2 = vmlal_u16(v_s2, vget_high_u16(v_column_sum_1), neon_ld1m_16((uint16_t[]) {28, 27, 26, 25}));
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v_s2 = vmlal_u16(v_s2, vget_low_u16(v_column_sum_2), neon_ld1m_16((uint16_t[]) {24, 23, 22, 21}));
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v_s2 = vmlal_u16(v_s2, vget_high_u16(v_column_sum_2), neon_ld1m_16((uint16_t[]) {20, 19, 18, 17}));
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v_s2 = vmlal_u16(v_s2, vget_low_u16(v_column_sum_3), neon_ld1m_16((uint16_t[]) {16, 15, 14, 13}));
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v_s2 = vmlal_u16(v_s2, vget_high_u16(v_column_sum_3), neon_ld1m_16((uint16_t[]) {12, 11, 10, 9}));
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v_s2 = vmlal_u16(v_s2, vget_low_u16(v_column_sum_4), neon_ld1m_16((uint16_t[]) {8, 7, 6, 5}));
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v_s2 = vmlal_u16(v_s2, vget_high_u16(v_column_sum_4), neon_ld1m_16((uint16_t[]) {4, 3, 2, 1}));
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#else
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v_s2 = vmlal_u16(v_s2, vget_low_u16(v_column_sum_1), vld1_u16(((uint16_t[]) {32, 31, 30, 29})));
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v_s2 = vmlal_u16(v_s2, vget_high_u16(v_column_sum_1), vld1_u16(((uint16_t[]) {28, 27, 26, 25})));
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v_s2 = vmlal_u16(v_s2, vget_low_u16(v_column_sum_2), vld1_u16(((uint16_t[]) {24, 23, 22, 21})));
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v_s2 = vmlal_u16(v_s2, vget_high_u16(v_column_sum_2), vld1_u16(((uint16_t[]) {20, 19, 18, 17})));
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v_s2 = vmlal_u16(v_s2, vget_low_u16(v_column_sum_3), vld1_u16(((uint16_t[]) {16, 15, 14, 13})));
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v_s2 = vmlal_u16(v_s2, vget_high_u16(v_column_sum_3), vld1_u16(((uint16_t[]) {12, 11, 10, 9})));
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v_s2 = vmlal_u16(v_s2, vget_low_u16(v_column_sum_4), vld1_u16(((uint16_t[]) {8, 7, 6, 5})));
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v_s2 = vmlal_u16(v_s2, vget_high_u16(v_column_sum_4), vld1_u16(((uint16_t[]) {4, 3, 2, 1})));
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#endif
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#else
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v_s2 = vmlal_u16(v_s2, vget_low_u16(v_column_sum_1), (uint16x4_t) {32, 31, 30, 29});
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v_s2 = vmlal_u16(v_s2, vget_high_u16(v_column_sum_1), (uint16x4_t) {28, 27, 26, 25});
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v_s2 = vmlal_u16(v_s2, vget_low_u16(v_column_sum_2), (uint16x4_t) {24, 23, 22, 21});
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v_s2 = vmlal_u16(v_s2, vget_high_u16(v_column_sum_2), (uint16x4_t) {20, 19, 18, 17});
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v_s2 = vmlal_u16(v_s2, vget_low_u16(v_column_sum_3), (uint16x4_t) {16, 15, 14, 13});
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v_s2 = vmlal_u16(v_s2, vget_high_u16(v_column_sum_3), (uint16x4_t) {12, 11, 10, 9});
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v_s2 = vmlal_u16(v_s2, vget_low_u16(v_column_sum_4), (uint16x4_t) {8, 7, 6, 5});
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v_s2 = vmlal_u16(v_s2, vget_high_u16(v_column_sum_4), (uint16x4_t) {4, 3, 2, 1});
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#endif
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/*
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* Sum epi32 ints v_s1(s2) and accumulate in s1(s2).
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*/
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uint32x2_t sum1 = vpadd_u32(vget_low_u32(v_s1), vget_high_u32(v_s1));
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uint32x2_t sum2 = vpadd_u32(vget_low_u32(v_s2), vget_high_u32(v_s2));
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uint32x2_t s1s2 = vpadd_u32(sum1, sum2);
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s1 += vget_lane_u32(s1s2, 0);
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s2 += vget_lane_u32(s1s2, 1);
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/*
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* Reduce.
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*/
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s1 %= FLETCHER32_MODULE;
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s2 %= FLETCHER32_MODULE;
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}
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/*
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* Handle leftover data.
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*/
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if (len) {
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if (len >= 16) {
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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len -= 16;
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}
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while (len--) { s2 += (s1 += *data++); }
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if (s1 >= FLETCHER32_MODULE) s1 -= FLETCHER32_MODULE;
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s2 %= FLETCHER32_MODULE;
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}
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/*
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* Return the recombined sums.
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*/
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*sum1 = s1 & 0xFFFF;
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*sum2 = s2 & 0xFFFF;
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}
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#endif
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