From 712281aba59e7f58b95192d60ada61f24d9673c4 Mon Sep 17 00:00:00 2001 From: JosJuice Date: Sun, 24 Sep 2023 09:26:12 +0200 Subject: [PATCH] Implement Fletcher-16 using ARM NEON instructions --- CMakeLists.txt | 2 +- fletcher16.c | 9 ++ fletcher16.h | 6 ++ fletcher16_neon.c | 204 +++++++++++++++++++++++++++++++++++++++++++ tests/fletcher16.cpp | 146 +++++++++++++++++++++++++++++++ 5 files changed, 366 insertions(+), 1 deletion(-) create mode 100644 fletcher16_neon.c diff --git a/CMakeLists.txt b/CMakeLists.txt index b0abfa9..47a6c56 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -71,6 +71,6 @@ if("${CMAKE_BUILD_TYPE}" MATCHES "Release") endif() endif() -add_library("Aaru.Checksums.Native" SHARED adler32.h adler32.c crc16.h crc16.c crc16_ccitt.h crc16_ccitt.c crc32.c crc32.h crc64.c crc64.h fletcher16.h fletcher16.c fletcher16_ssse3.c fletcher32.h fletcher32.c fletcher32_avx2.c fletcher32_neon.c fletcher32_ssse3.c library.h spamsum.c spamsum.h crc32_clmul.c crc64_clmul.c simd.c simd.h adler32_ssse3.c adler32_avx2.c adler32_neon.c crc32_arm_simd.c crc32_vmull.c crc32_simd.h arm_vmull.c arm_vmull.h crc64_vmull.c library.c) +add_library("Aaru.Checksums.Native" SHARED adler32.h adler32.c crc16.h crc16.c crc16_ccitt.h crc16_ccitt.c crc32.c crc32.h crc64.c crc64.h fletcher16.h fletcher16.c fletcher16_neon.c fletcher16_ssse3.c fletcher32.h fletcher32.c fletcher32_avx2.c fletcher32_neon.c fletcher32_ssse3.c library.h spamsum.c spamsum.h crc32_clmul.c crc64_clmul.c simd.c simd.h adler32_ssse3.c adler32_avx2.c adler32_neon.c crc32_arm_simd.c crc32_vmull.c crc32_simd.h arm_vmull.c arm_vmull.h crc64_vmull.c library.c) add_subdirectory(tests) diff --git a/fletcher16.c b/fletcher16.c index 1da649b..5b465ea 100644 --- a/fletcher16.c +++ b/fletcher16.c @@ -66,6 +66,15 @@ AARU_EXPORT int AARU_CALL fletcher16_update(fletcher16_ctx *ctx, const uint8_t * { if(!ctx || !data) return -1; +#if defined(__aarch64__) || defined(_M_ARM64) || ((defined(__arm__) || defined(_M_ARM)) && !defined(__MINGW32__)) + if(have_neon()) + { + fletcher16_neon(&ctx->sum1, &ctx->sum2, data, len); + + return 0; + } +#endif + #if defined(__x86_64__) || defined(__amd64) || defined(_M_AMD64) || defined(_M_X64) || defined(__I386__) || \ defined(__i386__) || defined(__THW_INTEL) || defined(_M_IX86) if(have_ssse3()) diff --git a/fletcher16.h b/fletcher16.h index b04abd7..1a7e321 100644 --- a/fletcher16.h +++ b/fletcher16.h @@ -41,4 +41,10 @@ AARU_EXPORT TARGET_WITH_SSSE3 void AARU_CALL fletcher16_ssse3(uint8_t* sum1, uin #endif +#if defined(__aarch64__) || defined(_M_ARM64) || defined(__arm__) || defined(_M_ARM) + +AARU_EXPORT TARGET_WITH_NEON void AARU_CALL fletcher16_neon(uint8_t* sum1, uint8_t* sum2, const uint8_t* data, uint32_t len); + +#endif + #endif // AARU_CHECKSUMS_NATIVE_FLETCHER16_H diff --git a/fletcher16_neon.c b/fletcher16_neon.c new file mode 100644 index 0000000..2d30d7f --- /dev/null +++ b/fletcher16_neon.c @@ -0,0 +1,204 @@ +/* + * This file is part of the Aaru Data Preservation Suite. + * Copyright (c) 2019-2023 Natalia Portillo. + * Copyright 2017 The Chromium Authors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following disclaimer + * in the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Google Inc. nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#if defined(__aarch64__) || defined(_M_ARM64) || ((defined(__arm__) || defined(_M_ARM))) + +#include + +#include "library.h" +#include "fletcher16.h" +#include "simd.h" + +/** + * @brief Calculate Fletcher-16 checksum for a given data using NEON instructions. + * + * This function calculates the Fletcher-16 checksum for a block of data using NEON vector instructions. + * + * @param sum1 Pointer to the variable where the first 8-bit checksum value is stored. + * @param sum2 Pointer to the variable where the second 8-bit checksum value is stored. + * @param data Pointer to the data buffer. + * @param len Length of the data buffer in bytes. + */ +TARGET_WITH_NEON void fletcher16_neon(uint8_t* sum1, uint8_t* sum2, const uint8_t* data, uint32_t len) +{ + /* + * Split Fletcher-16 into component sums. + */ + uint32_t s1 = *sum1; + uint32_t s2 = *sum2; + /* + * Serially compute s1 & s2, until the data is 16-byte aligned. + */ + if((uintptr_t)data & 15) + { + while((uintptr_t)data & 15) + { + s2 += (s1 += *data++); + --len; + } + s1 %= FLETCHER16_MODULE; + s2 %= FLETCHER16_MODULE; + } + /* + * Process the data in blocks. + */ + const unsigned BLOCK_SIZE = 1 << 5; + uint32_t blocks = len / BLOCK_SIZE; + len -= blocks * BLOCK_SIZE; + while(blocks) + { + unsigned n = NMAX / BLOCK_SIZE; /* The NMAX constraint. */ + if(n > blocks) n = (unsigned)blocks; + blocks -= n; + /* + * Process n blocks of data. At most NMAX data bytes can be + * processed before s2 must be reduced modulo FLETCHER16_MODULE. + */ +#ifdef _MSC_VER + uint32x4_t v_s2 = {.n128_u32 = {0, 0, 0, s1 * n}}; + uint32x4_t v_s1 = {.n128_u32 = {0, 0, 0, 0}}; +#else + uint32x4_t v_s2 = (uint32x4_t){0, 0, 0, s1 * n}; + uint32x4_t v_s1 = (uint32x4_t){0, 0, 0, 0}; +#endif + uint16x8_t v_column_sum_1 = vdupq_n_u16(0); + uint16x8_t v_column_sum_2 = vdupq_n_u16(0); + uint16x8_t v_column_sum_3 = vdupq_n_u16(0); + uint16x8_t v_column_sum_4 = vdupq_n_u16(0); + do { + /* + * Load 32 input bytes. + */ + const uint8x16_t bytes1 = vld1q_u8((uint8_t*)(data)); + const uint8x16_t bytes2 = vld1q_u8((uint8_t*)(data + 16)); + /* + * Add previous block byte sum to v_s2. + */ + v_s2 = vaddq_u32(v_s2, v_s1); + /* + * Horizontally add the bytes for s1. + */ + v_s1 = vpadalq_u16(v_s1, vpadalq_u8(vpaddlq_u8(bytes1), bytes2)); + /* + * Vertically add the bytes for s2. + */ + v_column_sum_1 = vaddw_u8(v_column_sum_1, vget_low_u8(bytes1)); + v_column_sum_2 = vaddw_u8(v_column_sum_2, vget_high_u8(bytes1)); + v_column_sum_3 = vaddw_u8(v_column_sum_3, vget_low_u8(bytes2)); + v_column_sum_4 = vaddw_u8(v_column_sum_4, vget_high_u8(bytes2)); + data += BLOCK_SIZE; + } while(--n); + v_s2 = vshlq_n_u32(v_s2, 5); + /* + * Multiply-add bytes by [ 32, 31, 30, ... ] for s2. + */ +#ifdef _MSC_VER +#ifdef _M_ARM64 + v_s2 = vmlal_u16(v_s2, vget_low_u16(v_column_sum_1), neon_ld1m_16((uint16_t[]){32, 31, 30, 29})); + v_s2 = vmlal_u16(v_s2, vget_high_u16(v_column_sum_1), neon_ld1m_16((uint16_t[]){28, 27, 26, 25})); + v_s2 = vmlal_u16(v_s2, vget_low_u16(v_column_sum_2), neon_ld1m_16((uint16_t[]){24, 23, 22, 21})); + v_s2 = vmlal_u16(v_s2, vget_high_u16(v_column_sum_2), neon_ld1m_16((uint16_t[]){20, 19, 18, 17})); + v_s2 = vmlal_u16(v_s2, vget_low_u16(v_column_sum_3), neon_ld1m_16((uint16_t[]){16, 15, 14, 13})); + v_s2 = vmlal_u16(v_s2, vget_high_u16(v_column_sum_3), neon_ld1m_16((uint16_t[]){12, 11, 10, 9})); + v_s2 = vmlal_u16(v_s2, vget_low_u16(v_column_sum_4), neon_ld1m_16((uint16_t[]){8, 7, 6, 5})); + v_s2 = vmlal_u16(v_s2, vget_high_u16(v_column_sum_4), neon_ld1m_16((uint16_t[]){4, 3, 2, 1})); +#else + v_s2 = vmlal_u16(v_s2, vget_low_u16(v_column_sum_1), vld1_u16(((uint16_t[]){32, 31, 30, 29}))); + v_s2 = vmlal_u16(v_s2, vget_high_u16(v_column_sum_1), vld1_u16(((uint16_t[]){28, 27, 26, 25}))); + v_s2 = vmlal_u16(v_s2, vget_low_u16(v_column_sum_2), vld1_u16(((uint16_t[]){24, 23, 22, 21}))); + v_s2 = vmlal_u16(v_s2, vget_high_u16(v_column_sum_2), vld1_u16(((uint16_t[]){20, 19, 18, 17}))); + v_s2 = vmlal_u16(v_s2, vget_low_u16(v_column_sum_3), vld1_u16(((uint16_t[]){16, 15, 14, 13}))); + v_s2 = vmlal_u16(v_s2, vget_high_u16(v_column_sum_3), vld1_u16(((uint16_t[]){12, 11, 10, 9}))); + v_s2 = vmlal_u16(v_s2, vget_low_u16(v_column_sum_4), vld1_u16(((uint16_t[]){8, 7, 6, 5}))); + v_s2 = vmlal_u16(v_s2, vget_high_u16(v_column_sum_4), vld1_u16(((uint16_t[]){4, 3, 2, 1}))); +#endif +#else + v_s2 = vmlal_u16(v_s2, vget_low_u16(v_column_sum_1), (uint16x4_t){32, 31, 30, 29}); + v_s2 = vmlal_u16(v_s2, vget_high_u16(v_column_sum_1), (uint16x4_t){28, 27, 26, 25}); + v_s2 = vmlal_u16(v_s2, vget_low_u16(v_column_sum_2), (uint16x4_t){24, 23, 22, 21}); + v_s2 = vmlal_u16(v_s2, vget_high_u16(v_column_sum_2), (uint16x4_t){20, 19, 18, 17}); + v_s2 = vmlal_u16(v_s2, vget_low_u16(v_column_sum_3), (uint16x4_t){16, 15, 14, 13}); + v_s2 = vmlal_u16(v_s2, vget_high_u16(v_column_sum_3), (uint16x4_t){12, 11, 10, 9}); + v_s2 = vmlal_u16(v_s2, vget_low_u16(v_column_sum_4), (uint16x4_t){8, 7, 6, 5}); + v_s2 = vmlal_u16(v_s2, vget_high_u16(v_column_sum_4), (uint16x4_t){4, 3, 2, 1}); +#endif + /* + * Sum epi32 ints v_s1(s2) and accumulate in s1(s2). + */ + uint32x2_t sum1 = vpadd_u32(vget_low_u32(v_s1), vget_high_u32(v_s1)); + uint32x2_t sum2 = vpadd_u32(vget_low_u32(v_s2), vget_high_u32(v_s2)); + uint32x2_t s1s2 = vpadd_u32(sum1, sum2); + s1 += vget_lane_u32(s1s2, 0); + s2 += vget_lane_u32(s1s2, 1); + /* + * Reduce. + */ + s1 %= FLETCHER16_MODULE; + s2 %= FLETCHER16_MODULE; + } + /* + * Handle leftover data. + */ + if(len) + { + if(len >= 16) + { + s2 += (s1 += *data++); + s2 += (s1 += *data++); + s2 += (s1 += *data++); + s2 += (s1 += *data++); + s2 += (s1 += *data++); + s2 += (s1 += *data++); + s2 += (s1 += *data++); + s2 += (s1 += *data++); + s2 += (s1 += *data++); + s2 += (s1 += *data++); + s2 += (s1 += *data++); + s2 += (s1 += *data++); + s2 += (s1 += *data++); + s2 += (s1 += *data++); + s2 += (s1 += *data++); + s2 += (s1 += *data++); + len -= 16; + } + while(len--) { s2 += (s1 += *data++); } + s1 %= FLETCHER16_MODULE; + s2 %= FLETCHER16_MODULE; + } + /* + * Return the recombined sums. + */ + *sum1 = s1 & 0xFF; + *sum2 = s2 & 0xFF; +} + +#endif diff --git a/tests/fletcher16.cpp b/tests/fletcher16.cpp index c9efdd7..2849dac 100644 --- a/tests/fletcher16.cpp +++ b/tests/fletcher16.cpp @@ -180,6 +180,152 @@ TEST_F(fletcher16Fixture, fletcher16_auto_2352bytes) EXPECT_EQ(fletcher, EXPECTED_FLETCHER16_2352BYTES); } +#if defined(__aarch64__) || defined(_M_ARM64) || ((defined(__arm__) || defined(_M_ARM)) && !defined(_WIN32)) +TEST_F(fletcher16Fixture, fletcher16_neon) +{ + if(!have_neon()) return; + + uint8_t sum1; + uint8_t sum2; + uint32_t fletcher16; + + sum1 = 0xFF; + sum2 = 0xFF; + + fletcher16_neon(&sum1, &sum2, buffer, 1048576); + + fletcher16 = (sum2 << 8) | sum1; + + EXPECT_EQ(fletcher16, EXPECTED_FLETCHER16); +} + +TEST_F(fletcher16Fixture, fletcher16_neon_misaligned) +{ + if(!have_neon()) return; + + uint8_t sum1; + uint8_t sum2; + uint32_t fletcher16; + + sum1 = 0xFF; + sum2 = 0xFF; + + fletcher16_neon(&sum1, &sum2, buffer_misaligned + 1, 1048576); + + fletcher16 = (sum2 << 8) | sum1; + + EXPECT_EQ(fletcher16, EXPECTED_FLETCHER16); +} + +TEST_F(fletcher16Fixture, fletcher16_neon_1byte) +{ + if(!have_neon()) return; + + uint8_t sum1; + uint8_t sum2; + uint32_t fletcher16; + + sum1 = 0xFF; + sum2 = 0xFF; + + fletcher16_neon(&sum1, &sum2, buffer, 1); + + fletcher16 = (sum2 << 8) | sum1; + + EXPECT_EQ(fletcher16, EXPECTED_FLETCHER16_1BYTE); +} + +TEST_F(fletcher16Fixture, fletcher16_neon_7bytes) +{ + if(!have_neon()) return; + + uint8_t sum1; + uint8_t sum2; + uint32_t fletcher16; + + sum1 = 0xFF; + sum2 = 0xFF; + + fletcher16_neon(&sum1, &sum2, buffer, 7); + + fletcher16 = (sum2 << 8) | sum1; + + EXPECT_EQ(fletcher16, EXPECTED_FLETCHER16_7BYTES); +} + +TEST_F(fletcher16Fixture, fletcher16_neon_15bytes) +{ + if(!have_neon()) return; + + uint8_t sum1; + uint8_t sum2; + uint32_t fletcher16; + + sum1 = 0xFF; + sum2 = 0xFF; + + fletcher16_neon(&sum1, &sum2, buffer, 15); + + fletcher16 = (sum2 << 8) | sum1; + + EXPECT_EQ(fletcher16, EXPECTED_FLETCHER16_15BYTES); +} + +TEST_F(fletcher16Fixture, fletcher16_neon_31bytes) +{ + if(!have_neon()) return; + + uint8_t sum1; + uint8_t sum2; + uint32_t fletcher16; + + sum1 = 0xFF; + sum2 = 0xFF; + + fletcher16_neon(&sum1, &sum2, buffer, 31); + + fletcher16 = (sum2 << 8) | sum1; + + EXPECT_EQ(fletcher16, EXPECTED_FLETCHER16_31BYTES); +} + +TEST_F(fletcher16Fixture, fletcher16_neon_63bytes) +{ + if(!have_neon()) return; + + uint8_t sum1; + uint8_t sum2; + uint32_t fletcher16; + + sum1 = 0xFF; + sum2 = 0xFF; + + fletcher16_neon(&sum1, &sum2, buffer, 63); + + fletcher16 = (sum2 << 8) | sum1; + + EXPECT_EQ(fletcher16, EXPECTED_FLETCHER16_63BYTES); +} + +TEST_F(fletcher16Fixture, fletcher16_neon_2352bytes) +{ + if(!have_neon()) return; + + uint8_t sum1; + uint8_t sum2; + uint32_t fletcher16; + + sum1 = 0xFF; + sum2 = 0xFF; + + fletcher16_neon(&sum1, &sum2, buffer, 2352); + + fletcher16 = (sum2 << 8) | sum1; + + EXPECT_EQ(fletcher16, EXPECTED_FLETCHER16_2352BYTES); +} +#endif + #if defined(__x86_64__) || defined(__amd64) || defined(_M_AMD64) || defined(_M_X64) || defined(__I386__) || \ defined(__i386__) || defined(__THW_INTEL) || defined(_M_IX86)