mirror of
https://github.com/aaru-dps/Aaru.Checksums.Native.git
synced 2025-12-16 11:14:29 +00:00
Implement Fletcher-16 using AVX2 instructions
This commit is contained in:
JosJuice
@@ -71,6 +71,6 @@ if("${CMAKE_BUILD_TYPE}" MATCHES "Release")
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endif()
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endif()
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add_library("Aaru.Checksums.Native" SHARED adler32.h adler32.c crc16.h crc16.c crc16_ccitt.h crc16_ccitt.c crc32.c crc32.h crc64.c crc64.h fletcher16.h fletcher16.c fletcher16_neon.c fletcher16_ssse3.c fletcher32.h fletcher32.c fletcher32_avx2.c fletcher32_neon.c fletcher32_ssse3.c library.h spamsum.c spamsum.h crc32_clmul.c crc64_clmul.c simd.c simd.h adler32_ssse3.c adler32_avx2.c adler32_neon.c crc32_arm_simd.c crc32_vmull.c crc32_simd.h arm_vmull.c arm_vmull.h crc64_vmull.c library.c)
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add_library("Aaru.Checksums.Native" SHARED adler32.h adler32.c crc16.h crc16.c crc16_ccitt.h crc16_ccitt.c crc32.c crc32.h crc64.c crc64.h fletcher16.h fletcher16.c fletcher16_avx2.c fletcher16_neon.c fletcher16_ssse3.c fletcher32.h fletcher32.c fletcher32_avx2.c fletcher32_neon.c fletcher32_ssse3.c library.h spamsum.c spamsum.h crc32_clmul.c crc64_clmul.c simd.c simd.h adler32_ssse3.c adler32_avx2.c adler32_neon.c crc32_arm_simd.c crc32_vmull.c crc32_simd.h arm_vmull.c arm_vmull.h crc64_vmull.c library.c)
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add_subdirectory(tests)
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@@ -77,6 +77,13 @@ AARU_EXPORT int AARU_CALL fletcher16_update(fletcher16_ctx *ctx, const uint8_t *
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#if defined(__x86_64__) || defined(__amd64) || defined(_M_AMD64) || defined(_M_X64) || defined(__I386__) || \
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defined(__i386__) || defined(__THW_INTEL) || defined(_M_IX86)
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if(have_avx2())
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{
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fletcher16_avx2(&ctx->sum1, &ctx->sum2, data, len);
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return 0;
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}
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if(have_ssse3())
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{
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fletcher16_ssse3(&ctx->sum1, &ctx->sum2, data, len);
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@@ -37,6 +37,7 @@ AARU_EXPORT void AARU_CALL fletcher16_free(fletcher16_ctx *ctx);
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#if defined(__x86_64__) || defined(__amd64) || defined(_M_AMD64) || defined(_M_X64) || defined(__I386__) || \
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defined(__i386__) || defined(__THW_INTEL) || defined(_M_IX86)
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AARU_EXPORT TARGET_WITH_AVX2 void AARU_CALL fletcher16_avx2(uint8_t* sum1, uint8_t* sum2, const uint8_t* data, long len);
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AARU_EXPORT TARGET_WITH_SSSE3 void AARU_CALL fletcher16_ssse3(uint8_t* sum1, uint8_t* sum2, const uint8_t* data, long len);
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#endif
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189
fletcher16_avx2.c
Normal file
189
fletcher16_avx2.c
Normal file
@@ -0,0 +1,189 @@
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/*
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* This file is part of the Aaru Data Preservation Suite.
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* Copyright (c) 2019-2023 Natalia Portillo.
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* Copyright (C) 1995-2011 Mark Adler
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* Copyright (C) Jean-loup Gailly
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*
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* This software is provided 'as-is', without any express or implied
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* warranty. In no event will the authors be held liable for any damages
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* arising from the use of this software.
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software. If you use this software
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* in a product, an acknowledgment in the product documentation would be
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* appreciated but is not required.
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*
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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* 3. This notice may not be removed or altered from any source distribution.
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*/
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#if defined(__x86_64__) || defined(__amd64) || defined(_M_AMD64) || defined(_M_X64) || defined(__I386__) || \
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defined(__i386__) || defined(__THW_INTEL) || defined(_M_IX86)
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#include <immintrin.h>
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#include <stdint.h>
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#include "library.h"
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#include "fletcher16.h"
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#include "simd.h"
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/**
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* @brief Calculate Fletcher-16 checksum for a given data using NEON instructions.
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*
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* This function calculates the Fletcher-16 checksum for a block of data using NEON vector instructions.
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*
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* @param sum1 Pointer to the variable where the first 8-bit checksum value is stored.
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* @param sum2 Pointer to the variable where the second 8-bit checksum value is stored.
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* @param data Pointer to the data buffer.
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* @param len Length of the data buffer in bytes.
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*/
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AARU_EXPORT TARGET_WITH_AVX2 void AARU_CALL
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fletcher16_avx2(uint8_t *sum1, uint8_t *sum2, const uint8_t *data, long len)
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{
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uint32_t s1 = *sum1;
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uint32_t s2 = *sum2;
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/*
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* Process the data in blocks.
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*/
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const unsigned BLOCK_SIZE = 1 << 5;
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long blocks = len / BLOCK_SIZE;
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len -= blocks * BLOCK_SIZE;
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while(blocks)
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{
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unsigned n = NMAX / BLOCK_SIZE; /* The NMAX constraint. */
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if(n > blocks) n = (unsigned)blocks;
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blocks -= n;
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const __m256i tap = _mm256_set_epi8(1,
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2,
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3,
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4,
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5,
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6,
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7,
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9,
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11,
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12,
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13,
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14,
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15,
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16,
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17,
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18,
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19,
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20,
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30,
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31,
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32);
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const __m256i zero = _mm256_setzero_si256();
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const __m256i ones = _mm256_set1_epi16(1);
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/*
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* Process n blocks of data. At most NMAX data bytes can be
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* processed before s2 must be reduced modulo BASE.
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*/
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__m256i v_ps = _mm256_set_epi32(0, 0, 0, 0, 0, 0, 0, (s1 * n));
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__m256i v_s2 = _mm256_set_epi32(0, 0, 0, 0, 0, 0, 0, s2);
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__m256i v_s1 = _mm256_setzero_si256();
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do
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{
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/*
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* Load 32 input bytes.
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*/
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const __m256i bytes = _mm256_lddqu_si256((__m256i *)(data));
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/*
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* Add previous block byte sum to v_ps.
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*/
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v_ps = _mm256_add_epi32(v_ps, v_s1);
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/*
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* Horizontally add the bytes for s1, multiply-adds the
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* bytes by [ 32, 31, 30, ... ] for s2.
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*/
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v_s1 = _mm256_add_epi32(v_s1, _mm256_sad_epu8(bytes, zero));
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const __m256i mad = _mm256_maddubs_epi16(bytes, tap);
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v_s2 = _mm256_add_epi32(v_s2, _mm256_madd_epi16(mad, ones));
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data += BLOCK_SIZE;
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}
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while(--n);
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__m128i sum = _mm_add_epi32(_mm256_castsi256_si128(v_s1), _mm256_extracti128_si256(v_s1, 1));
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__m128i hi = _mm_unpackhi_epi64(sum, sum);
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sum = _mm_add_epi32(hi, sum);
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hi = _mm_shuffle_epi32(sum, 177);
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sum = _mm_add_epi32(sum, hi);
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s1 += _mm_cvtsi128_si32(sum);
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v_s2 = _mm256_add_epi32(v_s2, _mm256_slli_epi32(v_ps, 5));
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sum = _mm_add_epi32(_mm256_castsi256_si128(v_s2), _mm256_extracti128_si256(v_s2, 1));
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hi = _mm_unpackhi_epi64(sum, sum);
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sum = _mm_add_epi32(hi, sum);
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hi = _mm_shuffle_epi32(sum, 177);
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sum = _mm_add_epi32(sum, hi);
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s2 = _mm_cvtsi128_si32(sum);
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/*
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* Reduce.
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*/
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s1 %= FLETCHER16_MODULE;
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s2 %= FLETCHER16_MODULE;
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}
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/*
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* Handle leftover data.
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*/
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if(len)
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{
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if(len >= 16)
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{
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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s2 += (s1 += *data++);
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len -= 16;
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}
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while(len--)
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{ s2 += (s1 += *data++); }
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s1 %= FLETCHER16_MODULE;
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s2 %= FLETCHER16_MODULE;
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}
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/*
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* Return the recombined sums.
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*/
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*sum1 = s1 & 0xFF;
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*sum2 = s2 & 0xFF;
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}
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#endif
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@@ -329,6 +329,24 @@ TEST_F(fletcher16Fixture, fletcher16_neon_2352bytes)
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#if defined(__x86_64__) || defined(__amd64) || defined(_M_AMD64) || defined(_M_X64) || defined(__I386__) || \
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defined(__i386__) || defined(__THW_INTEL) || defined(_M_IX86)
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TEST_F(fletcher16Fixture, fletcher16_avx2)
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{
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if(!have_avx2()) return;
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uint8_t sum1;
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uint8_t sum2;
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uint32_t fletcher16;
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sum1 = 0xFF;
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sum2 = 0xFF;
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fletcher16_avx2(&sum1, &sum2, buffer, 1048576);
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fletcher16 = (sum2 << 8) | sum1;
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EXPECT_EQ(fletcher16, EXPECTED_FLETCHER16);
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}
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TEST_F(fletcher16Fixture, fletcher16_ssse3)
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{
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if(!have_ssse3()) return;
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@@ -347,6 +365,24 @@ TEST_F(fletcher16Fixture, fletcher16_ssse3)
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EXPECT_EQ(fletcher16, EXPECTED_FLETCHER16);
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}
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TEST_F(fletcher16Fixture, fletcher16_avx2_misaligned)
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{
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if(!have_avx2()) return;
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uint8_t sum1;
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uint8_t sum2;
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uint32_t fletcher16;
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sum1 = 0xFF;
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sum2 = 0xFF;
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fletcher16_avx2(&sum1, &sum2, buffer_misaligned + 1, 1048576);
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fletcher16 = (sum2 << 8) | sum1;
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EXPECT_EQ(fletcher16, EXPECTED_FLETCHER16);
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}
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TEST_F(fletcher16Fixture, fletcher16_ssse3_misaligned)
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{
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if(!have_ssse3()) return;
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@@ -365,6 +401,24 @@ TEST_F(fletcher16Fixture, fletcher16_ssse3_misaligned)
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EXPECT_EQ(fletcher16, EXPECTED_FLETCHER16);
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}
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TEST_F(fletcher16Fixture, fletcher16_avx2_1byte)
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{
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if(!have_avx2()) return;
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uint8_t sum1;
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uint8_t sum2;
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uint32_t fletcher16;
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sum1 = 0xFF;
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sum2 = 0xFF;
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fletcher16_avx2(&sum1, &sum2, buffer, 1);
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fletcher16 = (sum2 << 8) | sum1;
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EXPECT_EQ(fletcher16, EXPECTED_FLETCHER16_1BYTE);
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}
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TEST_F(fletcher16Fixture, fletcher16_ssse3_1byte)
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{
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if(!have_ssse3()) return;
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@@ -383,6 +437,24 @@ TEST_F(fletcher16Fixture, fletcher16_ssse3_1byte)
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EXPECT_EQ(fletcher16, EXPECTED_FLETCHER16_1BYTE);
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}
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TEST_F(fletcher16Fixture, fletcher16_avx2_7bytes)
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{
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if(!have_avx2()) return;
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uint8_t sum1;
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uint8_t sum2;
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uint32_t fletcher16;
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sum1 = 0xFF;
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sum2 = 0xFF;
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fletcher16_avx2(&sum1, &sum2, buffer, 7);
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fletcher16 = (sum2 << 8) | sum1;
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EXPECT_EQ(fletcher16, EXPECTED_FLETCHER16_7BYTES);
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}
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TEST_F(fletcher16Fixture, fletcher16_ssse3_7bytes)
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{
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if(!have_ssse3()) return;
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@@ -401,6 +473,24 @@ TEST_F(fletcher16Fixture, fletcher16_ssse3_7bytes)
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EXPECT_EQ(fletcher16, EXPECTED_FLETCHER16_7BYTES);
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}
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TEST_F(fletcher16Fixture, fletcher16_avx2_15bytes)
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{
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if(!have_avx2()) return;
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uint8_t sum1;
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uint8_t sum2;
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uint32_t fletcher16;
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sum1 = 0xFF;
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sum2 = 0xFF;
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fletcher16_avx2(&sum1, &sum2, buffer, 15);
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fletcher16 = (sum2 << 8) | sum1;
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EXPECT_EQ(fletcher16, EXPECTED_FLETCHER16_15BYTES);
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}
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TEST_F(fletcher16Fixture, fletcher16_ssse3_15bytes)
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{
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if(!have_ssse3()) return;
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@@ -419,6 +509,24 @@ TEST_F(fletcher16Fixture, fletcher16_ssse3_15bytes)
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EXPECT_EQ(fletcher16, EXPECTED_FLETCHER16_15BYTES);
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}
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TEST_F(fletcher16Fixture, fletcher16_avx2_31bytes)
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{
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if(!have_avx2()) return;
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uint8_t sum1;
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uint8_t sum2;
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uint32_t fletcher16;
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sum1 = 0xFF;
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sum2 = 0xFF;
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fletcher16_avx2(&sum1, &sum2, buffer, 31);
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fletcher16 = (sum2 << 8) | sum1;
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EXPECT_EQ(fletcher16, EXPECTED_FLETCHER16_31BYTES);
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}
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TEST_F(fletcher16Fixture, fletcher16_ssse3_31bytes)
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{
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if(!have_ssse3()) return;
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@@ -437,6 +545,24 @@ TEST_F(fletcher16Fixture, fletcher16_ssse3_31bytes)
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EXPECT_EQ(fletcher16, EXPECTED_FLETCHER16_31BYTES);
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}
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TEST_F(fletcher16Fixture, fletcher16_avx2_63bytes)
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{
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if(!have_avx2()) return;
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uint8_t sum1;
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uint8_t sum2;
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uint32_t fletcher16;
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sum1 = 0xFF;
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sum2 = 0xFF;
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fletcher16_avx2(&sum1, &sum2, buffer, 63);
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fletcher16 = (sum2 << 8) | sum1;
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EXPECT_EQ(fletcher16, EXPECTED_FLETCHER16_63BYTES);
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}
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TEST_F(fletcher16Fixture, fletcher16_ssse3_63bytes)
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{
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if(!have_ssse3()) return;
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@@ -455,6 +581,24 @@ TEST_F(fletcher16Fixture, fletcher16_ssse3_63bytes)
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EXPECT_EQ(fletcher16, EXPECTED_FLETCHER16_63BYTES);
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}
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TEST_F(fletcher16Fixture, fletcher16_avx2_2352bytes)
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{
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if(!have_avx2()) return;
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uint8_t sum1;
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uint8_t sum2;
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uint32_t fletcher16;
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sum1 = 0xFF;
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sum2 = 0xFF;
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fletcher16_avx2(&sum1, &sum2, buffer, 2352);
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fletcher16 = (sum2 << 8) | sum1;
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EXPECT_EQ(fletcher16, EXPECTED_FLETCHER16_2352BYTES);
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}
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TEST_F(fletcher16Fixture, fletcher16_ssse3_2352bytes)
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{
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if(!have_ssse3()) return;
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