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https://github.com/aaru-dps/Aaru.Checksums.Native.git
synced 2025-12-16 19:24:29 +00:00
General refactor and cleanup.
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@@ -42,8 +42,7 @@
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* @param data Pointer to the data buffer.
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* @param len Length of the data buffer in bytes.
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*/
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AARU_EXPORT TARGET_WITH_AVX2 void AARU_CALL
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fletcher16_avx2(uint8_t *sum1, uint8_t *sum2, const uint8_t *data, long len)
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AARU_EXPORT TARGET_WITH_AVX2 void AARU_CALL fletcher16_avx2(uint8_t *sum1, uint8_t *sum2, const uint8_t *data, long len)
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{
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uint32_t s1 = *sum1;
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uint32_t s2 = *sum2;
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@@ -54,7 +53,7 @@ fletcher16_avx2(uint8_t *sum1, uint8_t *sum2, const uint8_t *data, long len)
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const unsigned BLOCK_SIZE = 1 << 5;
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if(len >= BLOCK_SIZE)
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{
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long blocks = len / BLOCK_SIZE;
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long blocks = len / BLOCK_SIZE;
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len -= blocks * BLOCK_SIZE;
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while(blocks)
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@@ -64,38 +63,8 @@ fletcher16_avx2(uint8_t *sum1, uint8_t *sum2, const uint8_t *data, long len)
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if(n > blocks) n = (unsigned)blocks;
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blocks -= n;
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const __m256i tap = _mm256_set_epi8(1,
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2,
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3,
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4,
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5,
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6,
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7,
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8,
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9,
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10,
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11,
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12,
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13,
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16,
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17,
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18,
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19,
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20,
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21,
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22,
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23,
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24,
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27,
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28,
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29,
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30,
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31,
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32);
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const __m256i tap = _mm256_set_epi8(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
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21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
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const __m256i zero = _mm256_setzero_si256();
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const __m256i ones = _mm256_set1_epi16(1);
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@@ -106,8 +75,7 @@ fletcher16_avx2(uint8_t *sum1, uint8_t *sum2, const uint8_t *data, long len)
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__m256i v_ps = _mm256_set_epi32(0, 0, 0, 0, 0, 0, 0, (s1 * n));
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__m256i v_s2 = _mm256_set_epi32(0, 0, 0, 0, 0, 0, 0, s2);
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__m256i v_s1 = _mm256_setzero_si256();
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do
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{
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do {
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/*
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* Load 32 input bytes.
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*/
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@@ -116,24 +84,23 @@ fletcher16_avx2(uint8_t *sum1, uint8_t *sum2, const uint8_t *data, long len)
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/*
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* Add previous block byte sum to v_ps.
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*/
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v_ps = _mm256_add_epi32(v_ps, v_s1);
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v_ps = _mm256_add_epi32(v_ps, v_s1);
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/*
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* Horizontally add the bytes for s1, multiply-adds the
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* bytes by [ 32, 31, 30, ... ] for s2.
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*/
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v_s1 = _mm256_add_epi32(v_s1, _mm256_sad_epu8(bytes, zero));
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v_s1 = _mm256_add_epi32(v_s1, _mm256_sad_epu8(bytes, zero));
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const __m256i mad = _mm256_maddubs_epi16(bytes, tap);
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v_s2 = _mm256_add_epi32(v_s2, _mm256_madd_epi16(mad, ones));
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v_s2 = _mm256_add_epi32(v_s2, _mm256_madd_epi16(mad, ones));
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data += BLOCK_SIZE;
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}
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while(--n);
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} while(--n);
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__m128i sum = _mm_add_epi32(_mm256_castsi256_si128(v_s1), _mm256_extracti128_si256(v_s1, 1));
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__m128i hi = _mm_unpackhi_epi64(sum, sum);
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sum = _mm_add_epi32(hi, sum);
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hi = _mm_shuffle_epi32(sum, 177);
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sum = _mm_add_epi32(sum, hi);
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sum = _mm_add_epi32(hi, sum);
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hi = _mm_shuffle_epi32(sum, 177);
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sum = _mm_add_epi32(sum, hi);
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s1 += _mm_cvtsi128_si32(sum);
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v_s2 = _mm256_add_epi32(v_s2, _mm256_slli_epi32(v_ps, 5));
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@@ -177,8 +144,7 @@ fletcher16_avx2(uint8_t *sum1, uint8_t *sum2, const uint8_t *data, long len)
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s2 += (s1 += *data++);
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len -= 16;
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}
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while(len--)
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{ s2 += (s1 += *data++); }
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while(len--) { s2 += (s1 += *data++); }
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s1 %= FLETCHER16_MODULE;
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s2 %= FLETCHER16_MODULE;
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}
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