Commit Graph

20 Commits

Author SHA1 Message Date
1f31d93572 Add ARM SIMD VMULL implementation of CRC32. 2021-10-05 00:33:48 +01:00
33abe35273 Enable GCC optimizations. 2021-09-29 02:54:49 +01:00
d433af7987 Add ARM special instructions implementation for CRC32. 2021-09-29 02:49:40 +01:00
2458863cb4 Add NEON implementation for Adler32. 2021-09-29 01:27:02 +01:00
fe773bd1b6 Add AVX2 implementation for Adler32. 2021-09-28 22:30:57 +01:00
00a8cb8668 Add SSSE3 implementation for Adler32. 2021-09-28 20:16:40 +01:00
04d7f954d6 Add optimizations for MSVC and set target cpu for x86 and x64 to minimum supported by RyuJIT. 2021-09-28 19:50:26 +01:00
84f639b3d2 Separate compiler optimization options by architecture. 2021-09-26 17:42:32 +01:00
6b45dd6e5b Condition compilation of CLMUL to IA32/AMD64 and check if it's available before executing. 2021-09-26 17:37:50 +01:00
186f57d7cb Add CLMUL implementations for CRC32 and CRC64. 2021-09-22 23:49:10 +01:00
25fcc7f474 Enable hard optimizations. 2021-09-22 17:04:40 +01:00
1407e647a8 Add SpamSum. 2021-09-22 00:46:07 +01:00
3431e43f1e Add Fletcher-32. 2021-09-22 00:01:36 +01:00
4e7fbac91b Add Fletcher-16. 2021-09-21 23:59:19 +01:00
d9b53ed189 Add CRC64 (ECMA). 2021-09-21 23:54:09 +01:00
40cf0017da Add CRC32 (ISO). 2021-09-21 23:51:30 +01:00
2904944095 Add CRC16 (IBM) 2021-09-21 23:46:04 +01:00
003d5d216c Add CRC16 (CCITT). 2021-09-21 23:40:11 +01:00
f44a1596e1 Added ADLER32. 2021-09-21 23:20:31 +01:00
c295172ce7 Initial commit. 2021-09-21 20:33:32 +01:00