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140 lines
6.2 KiB
C
140 lines
6.2 KiB
C
//
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// Created by claunia on 12/10/21.
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//
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#if defined(__aarch64__) || defined(_M_ARM64) || defined(__arm__) || defined(_M_ARM)
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#include <arm_neon.h>
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#include "library.h"
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#include "arm_vmull.h"
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#include "simd.h"
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TARGET_WITH_CRYPTO static uint64x2_t sse2neon_vmull_p64_crypto(uint64x1_t _a, uint64x1_t _b)
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{
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poly64_t a = vget_lane_p64(vreinterpret_p64_u64(_a), 0);
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poly64_t b = vget_lane_p64(vreinterpret_p64_u64(_b), 0);
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return vreinterpretq_u64_p128(vmull_p64(a, b));
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}
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TARGET_WITH_SIMD uint64x2_t sse2neon_vmull_p64(uint64x1_t _a, uint64x1_t _b)
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{
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// Wraps vmull_p64
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if(have_arm_crypto()) return sse2neon_vmull_p64_crypto(_a, _b);
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// ARMv7 polyfill
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// ARMv7/some A64 lacks vmull_p64, but it has vmull_p8.
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//
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// vmull_p8 calculates 8 8-bit->16-bit polynomial multiplies, but we need a
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// 64-bit->128-bit polynomial multiply.
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//
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// It needs some work and is somewhat slow, but it is still faster than all
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// known scalar methods.
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//
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// Algorithm adapted to C from
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// https://www.workofard.com/2017/07/ghash-for-low-end-cores/, which is adapted
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// from "Fast Software Polynomial Multiplication on ARM Processors Using the
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// NEON Engine" by Danilo Camara, Conrado Gouvea, Julio Lopez and Ricardo Dahab
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// (https://hal.inria.fr/hal-01506572)
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poly8x8_t a = vreinterpret_p8_u64(_a);
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poly8x8_t b = vreinterpret_p8_u64(_b);
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// Masks
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uint8x16_t k48_32 = vcombine_u8(vcreate_u8(0x0000ffffffffffff), vcreate_u8(0x00000000ffffffff));
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uint8x16_t k16_00 = vcombine_u8(vcreate_u8(0x000000000000ffff), vcreate_u8(0x0000000000000000));
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// Do the multiplies, rotating with vext to get all combinations
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uint8x16_t d = vreinterpretq_u8_p16(vmull_p8(a, b)); // D = A0 * B0
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uint8x16_t e = vreinterpretq_u8_p16(vmull_p8(a, vext_p8(b, b, 1))); // E = A0 * B1
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uint8x16_t f = vreinterpretq_u8_p16(vmull_p8(vext_p8(a, a, 1), b)); // F = A1 * B0
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uint8x16_t g = vreinterpretq_u8_p16(vmull_p8(a, vext_p8(b, b, 2))); // G = A0 * B2
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uint8x16_t h = vreinterpretq_u8_p16(vmull_p8(vext_p8(a, a, 2), b)); // H = A2 * B0
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uint8x16_t i = vreinterpretq_u8_p16(vmull_p8(a, vext_p8(b, b, 3))); // I = A0 * B3
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uint8x16_t j = vreinterpretq_u8_p16(vmull_p8(vext_p8(a, a, 3), b)); // J = A3 * B0
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uint8x16_t k = vreinterpretq_u8_p16(vmull_p8(a, vext_p8(b, b, 4))); // L = A0 * B4
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// Add cross products
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uint8x16_t l = veorq_u8(e, f); // L = E + F
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uint8x16_t m = veorq_u8(g, h); // M = G + H
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uint8x16_t n = veorq_u8(i, j); // N = I + J
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// Interleave. Using vzip1 and vzip2 prevents Clang from emitting TBL
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// instructions.
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#if defined(__aarch64__)
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uint8x16_t lm_p0 = vreinterpretq_u8_u64(vzip1q_u64(vreinterpretq_u64_u8(l), vreinterpretq_u64_u8(m)));
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uint8x16_t lm_p1 = vreinterpretq_u8_u64(vzip2q_u64(vreinterpretq_u64_u8(l), vreinterpretq_u64_u8(m)));
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uint8x16_t nk_p0 = vreinterpretq_u8_u64(vzip1q_u64(vreinterpretq_u64_u8(n), vreinterpretq_u64_u8(k)));
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uint8x16_t nk_p1 = vreinterpretq_u8_u64(vzip2q_u64(vreinterpretq_u64_u8(n), vreinterpretq_u64_u8(k)));
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#else
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uint8x16_t lm_p0 = vcombine_u8(vget_low_u8(l), vget_low_u8(m));
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uint8x16_t lm_p1 = vcombine_u8(vget_high_u8(l), vget_high_u8(m));
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uint8x16_t nk_p0 = vcombine_u8(vget_low_u8(n), vget_low_u8(k));
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uint8x16_t nk_p1 = vcombine_u8(vget_high_u8(n), vget_high_u8(k));
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#endif
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// t0 = (L) (P0 + P1) << 8
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// t1 = (M) (P2 + P3) << 16
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uint8x16_t t0t1_tmp = veorq_u8(lm_p0, lm_p1);
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uint8x16_t t0t1_h = vandq_u8(lm_p1, k48_32);
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uint8x16_t t0t1_l = veorq_u8(t0t1_tmp, t0t1_h);
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// t2 = (N) (P4 + P5) << 24
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// t3 = (K) (P6 + P7) << 32
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uint8x16_t t2t3_tmp = veorq_u8(nk_p0, nk_p1);
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uint8x16_t t2t3_h = vandq_u8(nk_p1, k16_00);
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uint8x16_t t2t3_l = veorq_u8(t2t3_tmp, t2t3_h);
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// De-interleave
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#if defined(__aarch64__)
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uint8x16_t t0 = vreinterpretq_u8_u64(vuzp1q_u64(vreinterpretq_u64_u8(t0t1_l), vreinterpretq_u64_u8(t0t1_h)));
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uint8x16_t t1 = vreinterpretq_u8_u64(vuzp2q_u64(vreinterpretq_u64_u8(t0t1_l), vreinterpretq_u64_u8(t0t1_h)));
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uint8x16_t t2 = vreinterpretq_u8_u64(vuzp1q_u64(vreinterpretq_u64_u8(t2t3_l), vreinterpretq_u64_u8(t2t3_h)));
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uint8x16_t t3 = vreinterpretq_u8_u64(vuzp2q_u64(vreinterpretq_u64_u8(t2t3_l), vreinterpretq_u64_u8(t2t3_h)));
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#else
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uint8x16_t t1 = vcombine_u8(vget_high_u8(t0t1_l), vget_high_u8(t0t1_h));
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uint8x16_t t0 = vcombine_u8(vget_low_u8(t0t1_l), vget_low_u8(t0t1_h));
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uint8x16_t t3 = vcombine_u8(vget_high_u8(t2t3_l), vget_high_u8(t2t3_h));
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uint8x16_t t2 = vcombine_u8(vget_low_u8(t2t3_l), vget_low_u8(t2t3_h));
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#endif
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// Shift the cross products
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uint8x16_t t0_shift = vextq_u8(t0, t0, 15); // t0 << 8
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uint8x16_t t1_shift = vextq_u8(t1, t1, 14); // t1 << 16
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uint8x16_t t2_shift = vextq_u8(t2, t2, 13); // t2 << 24
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uint8x16_t t3_shift = vextq_u8(t3, t3, 12); // t3 << 32
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// Accumulate the products
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uint8x16_t cross1 = veorq_u8(t0_shift, t1_shift);
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uint8x16_t cross2 = veorq_u8(t2_shift, t3_shift);
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uint8x16_t mix = veorq_u8(d, cross1);
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uint8x16_t r = veorq_u8(mix, cross2);
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return vreinterpretq_u64_u8(r);
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}
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TARGET_WITH_SIMD uint64x2_t mm_shuffle_epi8(uint64x2_t a, uint64x2_t b)
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{
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uint8x16_t tbl = vreinterpretq_u8_u64(a); // input a
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uint8x16_t idx = vreinterpretq_u8_u64(b); // input b
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uint8x16_t idx_masked = vandq_u8(idx, vdupq_n_u8(0x8F)); // avoid using meaningless bits
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#if defined(__aarch64__)
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return vreinterpretq_u64_u8(vqtbl1q_u8(tbl, idx_masked));
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#else
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// use this line if testing on aarch64
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uint8x8x2_t a_split = {vget_low_u8(tbl), vget_high_u8(tbl)};
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return vreinterpretq_u64_u8(
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vcombine_u8(vtbl2_u8(a_split, vget_low_u8(idx_masked)), vtbl2_u8(a_split, vget_high_u8(idx_masked))));
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#endif
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}
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TARGET_WITH_SIMD uint64x2_t mm_srli_si128(uint64x2_t a, int imm)
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{
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uint8x16_t tmp[2] = {vreinterpretq_u8_u64(a), vdupq_n_u8(0)};
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return vreinterpretq_u64_u8(vld1q_u8(((uint8_t const*)tmp) + imm));
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}
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TARGET_WITH_SIMD uint64x2_t mm_slli_si128(uint64x2_t a, int imm)
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{
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uint8x16_t tmp[2] = {vdupq_n_u8(0), vreinterpretq_u8_u64(a)};
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return vreinterpretq_u64_u8(vld1q_u8(((uint8_t const*)tmp) + (16 - imm)));
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}
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#endif |