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https://github.com/aaru-dps/Aaru.git
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Fix SIMD implementations for partial CRC blocks.
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@@ -412,6 +412,8 @@ namespace Aaru.Checksums
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static void Step(ref uint previousCrc, uint[][] table, byte[] data, uint len, bool useIso)
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{
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int currentPos = 0;
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if(useIso)
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{
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if(Pclmulqdq.IsSupported &&
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@@ -419,9 +421,19 @@ namespace Aaru.Checksums
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Ssse3.IsSupported &&
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Sse2.IsSupported)
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{
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previousCrc = ~Clmul.Step(data, len, ~previousCrc);
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// Only works in blocks of 16 bytes
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uint blocks = len / 64;
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return;
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if(blocks > 0)
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{
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previousCrc = ~Clmul.Step(data, blocks * 64, ~previousCrc);
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currentPos = (int)(blocks * 64);
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len -= blocks * 64;
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}
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if(len == 0)
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return;
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}
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if(Crc32.Arm64.IsSupported)
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@@ -442,7 +454,6 @@ namespace Aaru.Checksums
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// Unroll according to Intel slicing by uint8_t
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// http://www.intel.com/technology/comms/perfnet/download/CRC_generators.pdf
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// http://sourceforge.net/projects/slicing-by-8/
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int currentPos = 0;
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const int unroll = 4;
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const int bytesAtOnce = 8 * unroll;
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uint crc = previousCrc;
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