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Added information about commodore formats

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Natalia Portillo
2015-03-25 02:19:24 +00:00
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*** PCV (PCVIC VIC-20 emulator saved-session files)
*** Document revision: 1.1
*** Last updated: March 11, 2004
*** Compiler/Editor: Peter Schepers
*** Contributors/sources: unknown
This is another snapshot file, generated by the PCVIC VIC-20 emulator,
written by BW Van Schooten. This description is based on the version 1.0 of
the PCVIC emulator.
Bytes: $0000-0015 - PCVIC signature string "PCVIC system snapshot", with
a zero terminator
0016-0017 - Version#, minor (0-99)/major (0-255).
0018-0019 - Size of register state block (not including this size
value)
001A-XXXX - Register state block, contains system register values
and memory expansion settings.
XXXX-MMMM - Byte-run compression of VIC memory. This excludes
the standard ROM areas $8000-8FFF and $C000-CFFF
(END-1)-END - Two-byte checksum of the data from $0016 to the end
of the MMMM section.
Here is most of the contents of the register state block:
Byte: $00-01 - 6502 X register in low byte, high byte set to 0
02-03 - 6502 Y register in low byte, high byte set to 0
04-05 - 6502 SP (stack pointer) in low byte, high byte set to 1
06 - Unused
07 - 6502 auxiliary flags. Bits 2-5 are bits 2-5 of the CPU
flag register. All other bits set to 0.
08-09 - Scanline
0-263 - NTSC
0-311 - PAL
0A - VIA1 IFR register
0B - VIA1 IER register
0C - VIA2 IFR register
0D - VIA2 IER register
0E - VIA1 IRB port
0F - VIA1 ORB port
10 - VIA1 IRA port
11 - VIA1 ORA port
12 - VIA2 IRB port
13 - VIA2 ORB port
14 - VIA2 IRA port
15 - VIA2 ORA port
16 - Timer Status. 1=Active, 0=Inactive
Bit: 0 - VIA1 Timer 1
1 - VIA1 Timer 2
2 - VIA2 Timer 1
3 - VIA2 Timer 2
4-7 - Future expansion, set to 0
17 - VIA1 Timer 2 Latch
18 - VIA2 Timer 2 Latch
19 - VIA1 Timer 2 Timer
1A - VIA2 Timer 2 Timer
1B - NMI Flank.
0 - NMI was low since last time NMI was sampled
1 - NMI was high since last time NMI was sampled
1C - Memory configuration. If bit set, area is RAM. If bit
clear, area is either ROM or unavailable. Each bit
represents an 8Kb block of RAM.
Bit: 0 - $0000-1FFF*
1 - 2000-3FFF
2 - 4000-5FFF
3 - 6000-7FFF
4 - (always set to 0, ROM)
5 - A000-BFFF
6 - (always set to 0, ROM)
7 - (always set to 0, ROM)
*Note: The areas 0000-03ff and 1000-2000 are
considered to be always occupied by RAM. For an
unexpanded Vic, all blocks are set to 0. Setting only
the low block (bit 0) it to 1 results in 3K RAM
expansion.
1D-1E - 6502 PC (program counter) register
1F-20 - 6502 main flags
Bit: 00 - Don't care
01 - Don't care
02 - Don't care
03 - Don't care
04 - Don't care
05 - Don't care
06 - Zero flag
07 - Sign flag
08 - Carry flag
09 - Set to 0
10 - Set to 0
11 - Set to 0
12 - Set to 0
13 - Set to 0
14 - Overlfow flag
15 - Set to 0
21 - 6502 A register
22 - Scan count. CPU cylce count within scan line.
0 - End of scan line
129 (NTSC) or 131 (PAL) - Start of scan line
23 - END of register state block.
The rest of the file consists of the RAM and I/O areas. These are
byterun compressed, and require source code to decode properly, which I
will not get into here.