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108 lines
4.7 KiB
Plaintext
108 lines
4.7 KiB
Plaintext
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*** PCV (PCVIC VIC-20 emulator saved-session files)
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*** Document revision: 1.1
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*** Last updated: March 11, 2004
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*** Compiler/Editor: Peter Schepers
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*** Contributors/sources: unknown
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This is another snapshot file, generated by the PCVIC VIC-20 emulator,
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written by BW Van Schooten. This description is based on the version 1.0 of
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the PCVIC emulator.
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Bytes: $0000-0015 - PCVIC signature string "PCVIC system snapshot", with
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a zero terminator
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0016-0017 - Version#, minor (0-99)/major (0-255).
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0018-0019 - Size of register state block (not including this size
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value)
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001A-XXXX - Register state block, contains system register values
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and memory expansion settings.
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XXXX-MMMM - Byte-run compression of VIC memory. This excludes
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the standard ROM areas $8000-8FFF and $C000-CFFF
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(END-1)-END - Two-byte checksum of the data from $0016 to the end
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of the MMMM section.
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Here is most of the contents of the register state block:
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Byte: $00-01 - 6502 X register in low byte, high byte set to 0
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02-03 - 6502 Y register in low byte, high byte set to 0
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04-05 - 6502 SP (stack pointer) in low byte, high byte set to 1
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06 - Unused
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07 - 6502 auxiliary flags. Bits 2-5 are bits 2-5 of the CPU
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flag register. All other bits set to 0.
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08-09 - Scanline
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0-263 - NTSC
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0-311 - PAL
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0A - VIA1 IFR register
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0B - VIA1 IER register
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0C - VIA2 IFR register
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0D - VIA2 IER register
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0E - VIA1 IRB port
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0F - VIA1 ORB port
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10 - VIA1 IRA port
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11 - VIA1 ORA port
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12 - VIA2 IRB port
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13 - VIA2 ORB port
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14 - VIA2 IRA port
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15 - VIA2 ORA port
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16 - Timer Status. 1=Active, 0=Inactive
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Bit: 0 - VIA1 Timer 1
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1 - VIA1 Timer 2
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2 - VIA2 Timer 1
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3 - VIA2 Timer 2
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4-7 - Future expansion, set to 0
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17 - VIA1 Timer 2 Latch
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18 - VIA2 Timer 2 Latch
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19 - VIA1 Timer 2 Timer
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1A - VIA2 Timer 2 Timer
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1B - NMI Flank.
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0 - NMI was low since last time NMI was sampled
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1 - NMI was high since last time NMI was sampled
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1C - Memory configuration. If bit set, area is RAM. If bit
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clear, area is either ROM or unavailable. Each bit
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represents an 8Kb block of RAM.
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Bit: 0 - $0000-1FFF*
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1 - 2000-3FFF
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2 - 4000-5FFF
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3 - 6000-7FFF
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4 - (always set to 0, ROM)
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5 - A000-BFFF
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6 - (always set to 0, ROM)
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7 - (always set to 0, ROM)
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*Note: The areas 0000-03ff and 1000-2000 are
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considered to be always occupied by RAM. For an
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unexpanded Vic, all blocks are set to 0. Setting only
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the low block (bit 0) it to 1 results in 3K RAM
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expansion.
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1D-1E - 6502 PC (program counter) register
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1F-20 - 6502 main flags
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Bit: 00 - Don't care
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01 - Don't care
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02 - Don't care
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03 - Don't care
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04 - Don't care
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05 - Don't care
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06 - Zero flag
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07 - Sign flag
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08 - Carry flag
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09 - Set to 0
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10 - Set to 0
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11 - Set to 0
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12 - Set to 0
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13 - Set to 0
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14 - Overlfow flag
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15 - Set to 0
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21 - 6502 A register
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22 - Scan count. CPU cylce count within scan line.
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0 - End of scan line
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129 (NTSC) or 131 (PAL) - Start of scan line
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23 - END of register state block.
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The rest of the file consists of the RAM and I/O areas. These are
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byterun compressed, and require source code to decode properly, which I
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will not get into here.
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