libaaruformat 1.0
Aaru Data Preservation Suite - Format Library
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arm_vmull.c
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1/*
2 * This file is part of the Aaru Data Preservation Suite.
3 * Copyright (c) 2019-2026 Natalia Portillo.
4 * Copyright sse2neon.h contributors
5 *
6 * sse2neon is freely redistributable under the MIT License.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * SOFTWARE.
25 */
26
27#if defined(__aarch64__) || defined(_M_ARM64) || defined(__arm__) || defined(_M_ARM)
28
29#include <arm_neon.h>
30
31#include <aaruformat.h>
32
33#include "arm_vmull.h"
34
35#ifdef TARGET_WITH_CRYPTO
36TARGET_WITH_CRYPTO static uint64x2_t sse2neon_vmull_p64_crypto(uint64x1_t _a, uint64x1_t _b)
37{
38 poly64_t a = vget_lane_p64(vreinterpret_p64_u64(_a), 0);
39 poly64_t b = vget_lane_p64(vreinterpret_p64_u64(_b), 0);
40 return vreinterpretq_u64_p128(vmull_p64(a, b));
41}
42#endif
43
44TARGET_WITH_SIMD uint64x2_t sse2neon_vmull_p64(uint64x1_t _a, uint64x1_t _b)
45{
46#ifdef TARGET_WITH_CRYPTO
47 if(have_arm_crypto()) return sse2neon_vmull_p64_crypto(_a, _b);
48#endif
49
50 // ARMv7 polyfill
51 // ARMv7/some A64 lacks vmull_p64, but it has vmull_p8.
52 //
53 // vmull_p8 calculates 8 8-bit->16-bit polynomial multiplies, but we need a
54 // 64-bit->128-bit polynomial multiply.
55 //
56 // It needs some work and is somewhat slow, but it is still faster than all
57 // known scalar methods.
58 //
59 // Algorithm adapted to C from
60 // https://www.workofard.com/2017/07/ghash-for-low-end-cores/, which is adapted
61 // from "Fast Software Polynomial Multiplication on ARM Processors Using the
62 // NEON Engine" by Danilo Camara, Conrado Gouvea, Julio Lopez and Ricardo Dahab
63 // (https://hal.inria.fr/hal-01506572)
64
65 poly8x8_t a = vreinterpret_p8_u64(_a);
66 poly8x8_t b = vreinterpret_p8_u64(_b);
67
68 // Masks
69 uint8x16_t k48_32 = vcombine_u8(vcreate_u8(0x0000ffffffffffff), vcreate_u8(0x00000000ffffffff));
70 uint8x16_t k16_00 = vcombine_u8(vcreate_u8(0x000000000000ffff), vcreate_u8(0x0000000000000000));
71
72 // Do the multiplies, rotating with vext to get all combinations
73 uint8x16_t d = vreinterpretq_u8_p16(vmull_p8(a, b)); // D = A0 * B0
74 uint8x16_t e = vreinterpretq_u8_p16(vmull_p8(a, vext_p8(b, b, 1))); // E = A0 * B1
75 uint8x16_t f = vreinterpretq_u8_p16(vmull_p8(vext_p8(a, a, 1), b)); // F = A1 * B0
76 uint8x16_t g = vreinterpretq_u8_p16(vmull_p8(a, vext_p8(b, b, 2))); // G = A0 * B2
77 uint8x16_t h = vreinterpretq_u8_p16(vmull_p8(vext_p8(a, a, 2), b)); // H = A2 * B0
78 uint8x16_t i = vreinterpretq_u8_p16(vmull_p8(a, vext_p8(b, b, 3))); // I = A0 * B3
79 uint8x16_t j = vreinterpretq_u8_p16(vmull_p8(vext_p8(a, a, 3), b)); // J = A3 * B0
80 uint8x16_t k = vreinterpretq_u8_p16(vmull_p8(a, vext_p8(b, b, 4))); // L = A0 * B4
81
82 // Add cross products
83 uint8x16_t l = veorq_u8(e, f); // L = E + F
84 uint8x16_t m = veorq_u8(g, h); // M = G + H
85 uint8x16_t n = veorq_u8(i, j); // N = I + J
86
87 // Interleave. Using vzip1 and vzip2 prevents Clang from emitting TBL
88 // instructions.
89#if defined(__aarch64__)
90 uint8x16_t lm_p0 = vreinterpretq_u8_u64(vzip1q_u64(vreinterpretq_u64_u8(l), vreinterpretq_u64_u8(m)));
91 uint8x16_t lm_p1 = vreinterpretq_u8_u64(vzip2q_u64(vreinterpretq_u64_u8(l), vreinterpretq_u64_u8(m)));
92 uint8x16_t nk_p0 = vreinterpretq_u8_u64(vzip1q_u64(vreinterpretq_u64_u8(n), vreinterpretq_u64_u8(k)));
93 uint8x16_t nk_p1 = vreinterpretq_u8_u64(vzip2q_u64(vreinterpretq_u64_u8(n), vreinterpretq_u64_u8(k)));
94#else
95 uint8x16_t lm_p0 = vcombine_u8(vget_low_u8(l), vget_low_u8(m));
96 uint8x16_t lm_p1 = vcombine_u8(vget_high_u8(l), vget_high_u8(m));
97 uint8x16_t nk_p0 = vcombine_u8(vget_low_u8(n), vget_low_u8(k));
98 uint8x16_t nk_p1 = vcombine_u8(vget_high_u8(n), vget_high_u8(k));
99#endif
100 // t0 = (L) (P0 + P1) << 8
101 // t1 = (M) (P2 + P3) << 16
102 uint8x16_t t0t1_tmp = veorq_u8(lm_p0, lm_p1);
103 uint8x16_t t0t1_h = vandq_u8(lm_p1, k48_32);
104 uint8x16_t t0t1_l = veorq_u8(t0t1_tmp, t0t1_h);
105
106 // t2 = (N) (P4 + P5) << 24
107 // t3 = (K) (P6 + P7) << 32
108 uint8x16_t t2t3_tmp = veorq_u8(nk_p0, nk_p1);
109 uint8x16_t t2t3_h = vandq_u8(nk_p1, k16_00);
110 uint8x16_t t2t3_l = veorq_u8(t2t3_tmp, t2t3_h);
111
112 // De-interleave
113#if defined(__aarch64__)
114 uint8x16_t t0 = vreinterpretq_u8_u64(vuzp1q_u64(vreinterpretq_u64_u8(t0t1_l), vreinterpretq_u64_u8(t0t1_h)));
115 uint8x16_t t1 = vreinterpretq_u8_u64(vuzp2q_u64(vreinterpretq_u64_u8(t0t1_l), vreinterpretq_u64_u8(t0t1_h)));
116 uint8x16_t t2 = vreinterpretq_u8_u64(vuzp1q_u64(vreinterpretq_u64_u8(t2t3_l), vreinterpretq_u64_u8(t2t3_h)));
117 uint8x16_t t3 = vreinterpretq_u8_u64(vuzp2q_u64(vreinterpretq_u64_u8(t2t3_l), vreinterpretq_u64_u8(t2t3_h)));
118#else
119 uint8x16_t t1 = vcombine_u8(vget_high_u8(t0t1_l), vget_high_u8(t0t1_h));
120 uint8x16_t t0 = vcombine_u8(vget_low_u8(t0t1_l), vget_low_u8(t0t1_h));
121 uint8x16_t t3 = vcombine_u8(vget_high_u8(t2t3_l), vget_high_u8(t2t3_h));
122 uint8x16_t t2 = vcombine_u8(vget_low_u8(t2t3_l), vget_low_u8(t2t3_h));
123#endif
124 // Shift the cross products
125 uint8x16_t t0_shift = vextq_u8(t0, t0, 15); // t0 << 8
126 uint8x16_t t1_shift = vextq_u8(t1, t1, 14); // t1 << 16
127 uint8x16_t t2_shift = vextq_u8(t2, t2, 13); // t2 << 24
128 uint8x16_t t3_shift = vextq_u8(t3, t3, 12); // t3 << 32
129
130 // Accumulate the products
131 uint8x16_t cross1 = veorq_u8(t0_shift, t1_shift);
132 uint8x16_t cross2 = veorq_u8(t2_shift, t3_shift);
133 uint8x16_t mix = veorq_u8(d, cross1);
134 uint8x16_t r = veorq_u8(mix, cross2);
135 return vreinterpretq_u64_u8(r);
136}
137
138TARGET_WITH_SIMD uint64x2_t mm_shuffle_epi8(uint64x2_t a, uint64x2_t b)
139{
140 uint8x16_t tbl = vreinterpretq_u8_u64(a); // input a
141 uint8x16_t idx = vreinterpretq_u8_u64(b); // input b
142 uint8x16_t idx_masked = vandq_u8(idx, vdupq_n_u8(0x8F)); // avoid using meaningless bits
143#if defined(__aarch64__)
144 return vreinterpretq_u64_u8(vqtbl1q_u8(tbl, idx_masked));
145#else
146 // use this line if testing on aarch64
147 uint8x8x2_t a_split = {vget_low_u8(tbl), vget_high_u8(tbl)};
148 return vreinterpretq_u64_u8(
149 vcombine_u8(vtbl2_u8(a_split, vget_low_u8(idx_masked)), vtbl2_u8(a_split, vget_high_u8(idx_masked))));
150#endif
151}
152
153TARGET_WITH_SIMD uint64x2_t mm_srli_si128(uint64x2_t a, int imm)
154{
155 uint8x16_t tmp[2] = {vreinterpretq_u8_u64(a), vdupq_n_u8(0)};
156 return vreinterpretq_u64_u8(vld1q_u8(((uint8_t const *)tmp) + imm));
157}
158
159TARGET_WITH_SIMD uint64x2_t mm_slli_si128(uint64x2_t a, int imm)
160{
161 uint8x16_t tmp[2] = {vdupq_n_u8(0), vreinterpretq_u8_u64(a)};
162 return vreinterpretq_u64_u8(vld1q_u8(((uint8_t const *)tmp) + (16 - imm)));
163}
164
165#endif
arm_vmull.h