436 lines
9.9 KiB
C
436 lines
9.9 KiB
C
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/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the CMD PCI-0646 controller.
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*
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* Authors: Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2020 Miran Grca.
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include <86box/cdrom.h>
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#include <86box/scsi_device.h>
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#include <86box/scsi_cdrom.h>
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#include <86box/dma.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/keyboard.h>
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#include <86box/mem.h>
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#include <86box/pci.h>
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#include <86box/pic.h>
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#include <86box/timer.h>
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#include <86box/hdc.h>
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#include <86box/hdc_ide.h>
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#include <86box/hdc_ide_sff8038i.h>
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#include <86box/zip.h>
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#include <86box/mo.h>
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typedef struct
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{
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uint8_t vlb_idx, single_channel,
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in_cfg, regs[256];
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uint32_t local;
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int slot, irq_mode[2],
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irq_pin;
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sff8038i_t *bm[2];
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} cmd646_t;
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#ifdef ENABLE_CMD646_LOG
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int cmd646_do_log = ENABLE_CMD646_LOG;
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static void
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cmd646_log(const char *fmt, ...)
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{
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va_list ap;
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if (cmd646_do_log)
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{
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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#define cmd646_log(fmt, ...)
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#endif
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static void
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cmd646_set_irq(int channel, void *priv)
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{
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cmd646_t *dev = (cmd646_t *) priv;
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if (channel & 0x01) {
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if (!(dev->regs[0x57] & 0x10) || (channel & 0x40)) {
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dev->regs[0x57] &= ~0x10;
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dev->regs[0x57] |= (channel >> 2);
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}
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} else {
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if (!(dev->regs[0x50] & 0x04) || (channel & 0x40)) {
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dev->regs[0x50] &= ~0x04;
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dev->regs[0x50] |= (channel >> 4);
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}
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}
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sff_bus_master_set_irq(channel, dev->bm[channel & 0x01]);
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}
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static int
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cmd646_bus_master_dma(int channel, uint8_t *data, int transfer_length, int out, void *priv)
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{
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cmd646_t *dev = (cmd646_t *) priv;
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return sff_bus_master_dma(channel, data, transfer_length, out, dev->bm[channel & 0x01]);
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}
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static void
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cmd646_ide_handlers(cmd646_t *dev)
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{
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uint16_t main, side;
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int irq_mode[2] = { 0, 0 };
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ide_pri_disable();
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if ((dev->regs[0x09] & 0x01) && (dev->regs[0x50] & 0x40)) {
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main = (dev->regs[0x11] << 8) | (dev->regs[0x10] & 0xf8);
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side = ((dev->regs[0x15] << 8) | (dev->regs[0x14] & 0xfc)) + 2;
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} else {
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main = 0x1f0;
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side = 0x3f6;
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}
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ide_set_base(0, main);
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ide_set_side(0, side);
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if (dev->regs[0x09] & 0x01)
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irq_mode[0] = 1;
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sff_set_irq_mode(dev->bm[0], 0, irq_mode[0]);
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sff_set_irq_mode(dev->bm[0], 1, irq_mode[1]);
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if (dev->regs[0x04] & 0x01)
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ide_pri_enable();
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if (dev->single_channel)
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return;
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ide_sec_disable();
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if ((dev->regs[0x09] & 0x04) && (dev->regs[0x50] & 0x40)) {
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main = (dev->regs[0x19] << 8) | (dev->regs[0x18] & 0xf8);
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side = ((dev->regs[0x1d] << 8) | (dev->regs[0x1c] & 0xfc)) + 2;
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} else {
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main = 0x170;
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side = 0x376;
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}
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ide_set_base(1, main);
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ide_set_side(1, side);
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if (dev->regs[0x09] & 0x04)
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irq_mode[1] = 1;
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sff_set_irq_mode(dev->bm[1], 0, irq_mode[0]);
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sff_set_irq_mode(dev->bm[1], 1, irq_mode[1]);
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if ((dev->regs[0x04] & 0x01) && (dev->regs[0x51] & 0x08))
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ide_sec_enable();
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}
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static void
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cmd646_ide_bm_handlers(cmd646_t *dev)
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{
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uint16_t base = (dev->regs[0x20] & 0xf0) | (dev->regs[0x21] << 8);
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sff_bus_master_handler(dev->bm[0], (dev->regs[0x04] & 1), base);
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sff_bus_master_handler(dev->bm[1], (dev->regs[0x04] & 1), base + 8);
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}
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static void
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cmd646_pci_write(int func, int addr, uint8_t val, void *priv)
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{
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cmd646_t *dev = (cmd646_t *) priv;
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cmd646_log("[%04X:%08X] (%08X) cmd646_pci_write(%i, %02X, %02X)\n", CS, cpu_state.pc, ESI, func, addr, val);
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if (func == 0x00) switch (addr) {
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case 0x04:
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dev->regs[addr] = (val & 0x45);
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cmd646_ide_handlers(dev);
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break;
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case 0x07:
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dev->regs[addr] &= ~(val & 0xb1);
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break;
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case 0x09:
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if ((dev->regs[addr] & 0x0a) == 0x0a) {
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dev->regs[addr] = (dev->regs[addr] & 0x0a) | (val & 0x05);
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dev->irq_mode[0] = !!(val & 0x01);
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dev->irq_mode[1] = !!(val & 0x04);
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cmd646_ide_handlers(dev);
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}
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break;
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case 0x10:
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if (dev->regs[0x50] & 0x40) {
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dev->regs[0x10] = (val & 0xf8) | 1;
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cmd646_ide_handlers(dev);
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}
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break;
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case 0x11:
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if (dev->regs[0x50] & 0x40) {
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dev->regs[0x11] = val;
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cmd646_ide_handlers(dev);
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}
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break;
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case 0x14:
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if (dev->regs[0x50] & 0x40) {
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dev->regs[0x14] = (val & 0xfc) | 1;
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cmd646_ide_handlers(dev);
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}
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break;
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case 0x15:
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if (dev->regs[0x50] & 0x40) {
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dev->regs[0x15] = val;
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cmd646_ide_handlers(dev);
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}
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break;
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case 0x18:
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if (dev->regs[0x50] & 0x40) {
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dev->regs[0x18] = (val & 0xf8) | 1;
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cmd646_ide_handlers(dev);
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}
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break;
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case 0x19:
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if (dev->regs[0x50] & 0x40) {
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dev->regs[0x19] = val;
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cmd646_ide_handlers(dev);
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}
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break;
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case 0x1c:
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if (dev->regs[0x50] & 0x40) {
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dev->regs[0x1c] = (val & 0xfc) | 1;
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cmd646_ide_handlers(dev);
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}
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break;
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case 0x1d:
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if (dev->regs[0x50] & 0x40) {
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dev->regs[0x1d] = val;
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cmd646_ide_handlers(dev);
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}
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break;
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case 0x20:
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dev->regs[0x20] = (val & 0xf0) | 1;
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cmd646_ide_bm_handlers(dev);
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break;
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case 0x21:
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dev->regs[0x21] = val;
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cmd646_ide_bm_handlers(dev);
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break;
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case 0x51:
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dev->regs[addr] = val & 0xc8;
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cmd646_ide_handlers(dev);
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break;
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case 0x52: case 0x54: case 0x56: case 0x58:
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case 0x59: case 0x5b:
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dev->regs[addr] = val;
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break;
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case 0x53: case 0x55:
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dev->regs[addr] = val & 0xc0;
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break;
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case 0x57:
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dev->regs[addr] = (dev->regs[addr] & 0x10) | (val & 0xcc);
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break;
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case 0x70 ... 0x77:
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sff_bus_master_write(addr & 0x0f, val, dev->bm[0]);
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break;
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case 0x78 ... 0x7f:
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sff_bus_master_write(addr & 0x0f, val, dev->bm[1]);
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break;
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}
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}
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static uint8_t
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cmd646_pci_read(int func, int addr, void *priv)
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{
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cmd646_t *dev = (cmd646_t *) priv;
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uint8_t ret = 0xff;
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if (func == 0x00) {
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ret = dev->regs[addr];
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if (addr == 0x50)
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dev->regs[0x50] &= ~0x04;
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else if (addr == 0x57)
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dev->regs[0x57] &= ~0x10;
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else if ((addr >= 0x70) && (addr <= 0x77))
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ret = sff_bus_master_read(addr & 0x0f, dev->bm[0]);
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else if ((addr >= 0x78) && (addr <= 0x7f))
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ret = sff_bus_master_read(addr & 0x0f, dev->bm[0]);
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}
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cmd646_log("[%04X:%08X] (%08X) cmd646_pci_read(%i, %02X, %02X)\n", CS, cpu_state.pc, ESI, func, addr, ret);
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return ret;
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}
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static void
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cmd646_reset(void *priv)
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{
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cmd646_t *dev = (cmd646_t *) priv;
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int i = 0;
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for (i = 0; i < CDROM_NUM; i++) {
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if ((cdrom[i].bus_type == CDROM_BUS_ATAPI) &&
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(cdrom[i].ide_channel < 4) && cdrom[i].priv)
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scsi_cdrom_reset((scsi_common_t *) cdrom[i].priv);
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}
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for (i = 0; i < ZIP_NUM; i++) {
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if ((zip_drives[i].bus_type == ZIP_BUS_ATAPI) &&
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(zip_drives[i].ide_channel < 4) && zip_drives[i].priv)
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zip_reset((scsi_common_t *) zip_drives[i].priv);
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}
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for (i = 0; i < MO_NUM; i++) {
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if ((mo_drives[i].bus_type == MO_BUS_ATAPI) &&
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(mo_drives[i].ide_channel < 4) && mo_drives[i].priv)
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mo_reset((scsi_common_t *) mo_drives[i].priv);
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}
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cmd646_set_irq(0x00, priv);
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cmd646_set_irq(0x01, priv);
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memset(dev->regs, 0x00, sizeof(dev->regs));
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dev->regs[0x00] = 0x95; /* CMD */
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dev->regs[0x01] = 0x10;
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dev->regs[0x02] = 0x46; /* PCI-0646 */
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dev->regs[0x03] = 0x06;
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dev->regs[0x04] = 0x00;
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dev->regs[0x06] = 0x80;
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dev->regs[0x07] = 0x02; /* DEVSEL timing: 01 medium */
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dev->regs[0x09] = dev->local; /* Programming interface */
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dev->regs[0x0a] = 0x01; /* IDE controller */
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dev->regs[0x0b] = 0x01; /* Mass storage controller */
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if ((dev->local & 0xffff) == 0x8a) {
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dev->regs[0x50] = 0x40; /* Enable Base address register R/W;
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If 0, they return 0 and are read-only 8 */
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/* Base addresses (1F0, 3F4, 170, 374) */
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dev->regs[0x10] = 0xf1; dev->regs[0x11] = 0x01;
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dev->regs[0x14] = 0xf5; dev->regs[0x15] = 0x03;
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dev->regs[0x18] = 0x71; dev->regs[0x19] = 0x01;
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dev->regs[0x1c] = 0x75; dev->regs[0x1d] = 0x03;
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}
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dev->regs[0x20] = 0x01;
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dev->regs[0x3c] = 0x0e; /* IRQ 14 */
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dev->regs[0x3d] = 0x01; /* INTA */
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dev->regs[0x3e] = 0x02; /* Min_Gnt */
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dev->regs[0x3f] = 0x04; /* Max_Iat */
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if (!dev->single_channel)
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dev->regs[0x51] = 0x08;
|
||
|
|
|
||
|
|
dev->regs[0x57] = 0x0c;
|
||
|
|
dev->regs[0x59] = 0x40;
|
||
|
|
|
||
|
|
dev->irq_mode[0] = dev->irq_mode[1] = 0;
|
||
|
|
dev->irq_pin = PCI_INTA;
|
||
|
|
|
||
|
|
cmd646_ide_handlers(dev);
|
||
|
|
cmd646_ide_bm_handlers(dev);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
static void
|
||
|
|
cmd646_close(void *priv)
|
||
|
|
{
|
||
|
|
cmd646_t *dev = (cmd646_t *) priv;
|
||
|
|
|
||
|
|
free(dev);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
static void *
|
||
|
|
cmd646_init(const device_t *info)
|
||
|
|
{
|
||
|
|
cmd646_t *dev = (cmd646_t *) malloc(sizeof(cmd646_t));
|
||
|
|
memset(dev, 0x00, sizeof(cmd646_t));
|
||
|
|
|
||
|
|
dev->local = info->local;
|
||
|
|
|
||
|
|
device_add(&ide_pci_2ch_device);
|
||
|
|
|
||
|
|
dev->slot = pci_add_card(PCI_ADD_IDE, cmd646_pci_read, cmd646_pci_write, dev);
|
||
|
|
|
||
|
|
dev->single_channel = !!(info->local & 0x20000);
|
||
|
|
|
||
|
|
dev->bm[0] = device_add_inst(&sff8038i_device, 1);
|
||
|
|
if (!dev->single_channel)
|
||
|
|
dev->bm[1] = device_add_inst(&sff8038i_device, 2);
|
||
|
|
|
||
|
|
ide_set_bus_master(0, cmd646_bus_master_dma, cmd646_set_irq, dev);
|
||
|
|
if (!dev->single_channel)
|
||
|
|
ide_set_bus_master(1, cmd646_bus_master_dma, cmd646_set_irq, dev);
|
||
|
|
|
||
|
|
sff_set_irq_mode(dev->bm[0], 0, 0);
|
||
|
|
sff_set_irq_mode(dev->bm[0], 1, 0);
|
||
|
|
|
||
|
|
if (!dev->single_channel) {
|
||
|
|
sff_set_irq_mode(dev->bm[1], 0, 0);
|
||
|
|
sff_set_irq_mode(dev->bm[1], 1, 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
cmd646_reset(dev);
|
||
|
|
|
||
|
|
return dev;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
const device_t ide_cmd646_device = {
|
||
|
|
"CMD PCI-0646",
|
||
|
|
DEVICE_PCI,
|
||
|
|
0x8a,
|
||
|
|
cmd646_init, cmd646_close, cmd646_reset,
|
||
|
|
{ NULL }, NULL, NULL,
|
||
|
|
NULL
|
||
|
|
};
|
||
|
|
|
||
|
|
const device_t ide_cmd646_legacy_only_device = {
|
||
|
|
"CMD PCI-0646 (Legacy Mode Only)",
|
||
|
|
DEVICE_PCI,
|
||
|
|
0x80,
|
||
|
|
cmd646_init, cmd646_close, cmd646_reset,
|
||
|
|
{ NULL }, NULL, NULL,
|
||
|
|
NULL
|
||
|
|
};
|
||
|
|
|
||
|
|
const device_t ide_cmd646_single_channel_device = {
|
||
|
|
"CMD PCI-0646",
|
||
|
|
DEVICE_PCI,
|
||
|
|
0x2008a,
|
||
|
|
cmd646_init, cmd646_close, cmd646_reset,
|
||
|
|
{ NULL }, NULL, NULL,
|
||
|
|
NULL
|
||
|
|
};
|