2016-06-26 00:34:39 +02:00
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#include "ibm.h"
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#include "io.h"
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#include "mem.h"
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2017-06-02 01:38:25 +02:00
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#include "pic.h"
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2016-06-26 00:34:39 +02:00
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#include "pci.h"
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2017-08-24 01:14:39 -04:00
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2016-06-26 00:34:39 +02:00
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void (*pci_card_write[32])(int func, int addr, uint8_t val, void *priv);
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uint8_t (*pci_card_read[32])(int func, int addr, void *priv);
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void *pci_priv[32];
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2017-06-02 01:38:25 +02:00
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static int pci_irq_routing[32];
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2017-06-22 06:50:33 +02:00
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/* static int pci_irq_active[32]; */
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2017-06-02 01:38:25 +02:00
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static int pci_irqs[4];
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static int pci_card_valid[32];
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2017-08-28 16:53:53 +02:00
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static uint64_t pci_irq_hold[16];
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2017-06-02 01:38:25 +02:00
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static int pci_index, pci_func, pci_card, pci_bus, pci_enable, pci_key;
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2016-06-26 00:34:39 +02:00
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int pci_burst_time, pci_nonburst_time;
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void pci_cf8_write(uint16_t port, uint32_t val, void *p)
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{
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pci_index = val & 0xff;
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pci_func = (val >> 8) & 7;
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pci_card = (val >> 11) & 31;
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pci_bus = (val >> 16) & 0xff;
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pci_enable = (val >> 31) & 1;
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}
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uint32_t pci_cf8_read(uint16_t port, void *p)
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{
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return pci_index | (pci_func << 8) | (pci_card << 11) | (pci_bus << 16) | (pci_enable << 31);
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}
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void pci_write(uint16_t port, uint8_t val, void *priv)
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{
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switch (port)
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{
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case 0xcfc: case 0xcfd: case 0xcfe: case 0xcff:
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if (!pci_enable)
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return;
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2017-06-02 01:38:25 +02:00
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2016-06-26 00:34:39 +02:00
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if (!pci_bus && pci_card_write[pci_card])
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pci_card_write[pci_card](pci_func, pci_index | (port & 3), val, pci_priv[pci_card]);
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break;
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}
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}
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uint8_t pci_read(uint16_t port, void *priv)
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{
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switch (port)
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{
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case 0xcfc: case 0xcfd: case 0xcfe: case 0xcff:
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if (!pci_enable)
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return 0xff;
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if (!pci_bus && pci_card_read[pci_card])
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return pci_card_read[pci_card](pci_func, pci_index | (port & 3), pci_priv[pci_card]);
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return 0xff;
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}
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2017-06-02 01:38:25 +02:00
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return 0xff;
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2016-06-26 00:34:39 +02:00
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}
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2017-06-03 00:45:12 +02:00
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uint8_t elcr[2] = { 0, 0 };
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void elcr_write(uint16_t port, uint8_t val, void *priv)
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{
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2017-06-03 02:11:36 +02:00
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/* pclog("ELCR%i: WRITE %02X\n", port & 1, val); */
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2017-06-03 00:45:12 +02:00
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elcr[port & 1] = val;
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2017-06-22 06:50:33 +02:00
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2017-06-22 06:56:22 +02:00
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/* printf("ELCR %i: %c %c %c %c %c %c %c %c\n", port & 1, (val & 1) ? 'L' : 'E', (val & 2) ? 'L' : 'E', (val & 4) ? 'L' : 'E', (val & 8) ? 'L' : 'E', (val & 0x10) ? 'L' : 'E', (val & 0x20) ? 'L' : 'E', (val & 0x40) ? 'L' : 'E', (val & 0x80) ? 'L' : 'E'); */
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2017-06-03 00:45:12 +02:00
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}
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uint8_t elcr_read(uint16_t port, void *priv)
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{
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2017-06-03 02:11:36 +02:00
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/* pclog("ELCR%i: READ %02X\n", port & 1, elcr[port & 1]); */
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2017-06-03 00:45:12 +02:00
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return elcr[port & 1];
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}
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2017-06-21 19:42:36 +02:00
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void elcr_reset(void)
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{
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int i = 0;
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pic_reset();
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elcr[0] = elcr[1] = 0;
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2017-06-22 06:50:33 +02:00
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#if 0
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2017-06-21 19:42:36 +02:00
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for (i = 0; i < 32; i++)
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{
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pci_irq_active[i] = 0;
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}
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2017-06-22 06:50:33 +02:00
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#endif
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for (i = 0; i < 16; i++)
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{
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pci_irq_hold[i] = 0;
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}
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2017-06-21 19:42:36 +02:00
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}
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2016-06-26 00:34:39 +02:00
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void pci_type2_write(uint16_t port, uint8_t val, void *priv);
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uint8_t pci_type2_read(uint16_t port, void *priv);
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void pci_type2_write(uint16_t port, uint8_t val, void *priv)
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{
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if (port == 0xcf8)
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{
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pci_func = (val >> 1) & 7;
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if (!pci_key && (val & 0xf0))
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io_sethandler(0xc000, 0x1000, pci_type2_read, NULL, NULL, pci_type2_write, NULL, NULL, NULL);
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else
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io_removehandler(0xc000, 0x1000, pci_type2_read, NULL, NULL, pci_type2_write, NULL, NULL, NULL);
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pci_key = val & 0xf0;
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}
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else if (port == 0xcfa)
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{
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pci_bus = val;
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}
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else
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{
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pci_card = (port >> 8) & 0xf;
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pci_index = port & 0xff;
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if (!pci_bus && pci_card_write[pci_card])
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pci_card_write[pci_card](pci_func, pci_index | (port & 3), val, pci_priv[pci_card]);
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}
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}
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uint8_t pci_type2_read(uint16_t port, void *priv)
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{
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if (port == 0xcf8)
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{
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return pci_key | (pci_func << 1);
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}
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else if (port == 0xcfa)
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{
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return pci_bus;
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}
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else
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{
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pci_card = (port >> 8) & 0xf;
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pci_index = port & 0xff;
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if (!pci_bus && pci_card_write[pci_card])
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return pci_card_read[pci_card](pci_func, pci_index | (port & 3), pci_priv[pci_card]);
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}
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return 0xff;
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}
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2017-06-02 01:38:25 +02:00
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void pci_set_irq_routing(int pci_int, int irq)
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{
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pci_irqs[pci_int - 1] = irq;
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}
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void pci_set_card_routing(int card, int pci_int)
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{
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pci_irq_routing[card] = pci_int;
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}
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2017-06-22 06:50:33 +02:00
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int pci_irq_is_level(int irq)
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2017-06-03 00:45:12 +02:00
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{
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int real_irq = irq & 7;
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2017-06-22 06:50:33 +02:00
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/* int irq_elcr = 0; */
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2017-06-03 00:45:12 +02:00
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if (irq > 7)
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{
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2017-06-22 06:50:33 +02:00
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return !!(elcr[1] & (1 << real_irq));
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2017-06-03 00:45:12 +02:00
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}
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else
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{
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2017-06-22 06:50:33 +02:00
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return !!(elcr[0] & (1 << real_irq));
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2017-06-03 00:45:12 +02:00
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}
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2017-06-22 06:50:33 +02:00
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}
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2017-06-03 00:45:12 +02:00
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2017-06-22 06:50:33 +02:00
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void pci_issue_irq(int irq)
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{
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2017-08-27 23:57:47 +02:00
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/* pclog("Issuing PCI IRQ %i: ", irq); */
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2017-06-22 06:50:33 +02:00
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if (pci_irq_is_level(irq))
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2017-06-03 00:45:12 +02:00
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{
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2017-08-27 23:57:47 +02:00
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/* pclog("Level\n"); */
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2017-06-19 06:46:08 +02:00
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picintlevel(1 << irq);
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2017-06-03 00:45:12 +02:00
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}
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else
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{
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2017-08-27 23:57:47 +02:00
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/* pclog("Edge\n"); */
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2017-06-03 00:45:12 +02:00
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picint(1 << irq);
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}
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}
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2017-08-28 16:53:53 +02:00
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void pci_ide_set_irq(int ide_board, int irq)
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{
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if (pci_irq_is_level(irq) && (pci_irq_hold[irq] & (1LL << (0x20LL + ide_board))))
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{
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/* IRQ already held, do nothing. */
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return;
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}
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if (!pci_irq_is_level(irq) || !pci_irq_hold[irq])
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{
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/* Only raise the interrupt if it's edge-triggered or level-triggered and not yet being held. */
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pci_issue_irq(irq);
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}
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/* If the IRQ is level-triggered, mark that this card is holding it. */
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if (pci_irq_is_level(irq))
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{
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pci_irq_hold[irq] |= (1LL << (0x20LL + ide_board));
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}
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}
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2017-06-02 01:38:25 +02:00
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void pci_set_irq(int card, int pci_int)
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{
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2017-06-19 06:46:08 +02:00
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int irq = ((pci_int - PCI_INTA) + (pci_irq_routing[card] - PCI_INTA)) & 3;
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2017-08-27 23:57:47 +02:00
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if (pci_irq_routing[card] && (pci_irqs[irq] != PCI_IRQ_DISABLED))
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2017-06-02 01:38:25 +02:00
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{
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2017-08-28 16:53:53 +02:00
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if (pci_irq_is_level(pci_irqs[irq]) && (pci_irq_hold[pci_irqs[irq]] & (1 << card)))
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{
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/* IRQ already held, do nothing. */
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return;
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}
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2017-08-27 23:57:47 +02:00
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2017-08-28 16:53:53 +02:00
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if (!pci_irq_is_level(pci_irqs[irq]) || !pci_irq_hold[pci_irqs[irq]])
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{
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/* Only raise the interrupt if it's edge-triggered or level-triggered and not yet being held. */
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pci_issue_irq(pci_irqs[irq]);
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}
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/* If the IRQ is level-triggered, mark that this card is holding it. */
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2017-08-27 23:57:47 +02:00
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if (pci_irq_is_level(pci_irqs[irq]))
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2017-06-22 06:56:22 +02:00
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{
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pci_irq_hold[pci_irqs[irq]] |= (1 << card);
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}
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2017-06-02 01:38:25 +02:00
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}
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}
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2017-08-28 16:53:53 +02:00
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void pci_ide_clear_irq(int ide_board, int irq)
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{
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if (pci_irq_is_level(irq))
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{
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pci_irq_hold[irq] &= ~(1LL << (0x20LL + ide_board));
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if (!pci_irq_hold[irq])
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{
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picintc(1 << irq);
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}
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}
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else
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{
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picintc(1 << irq);
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}
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}
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2017-06-02 01:38:25 +02:00
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void pci_clear_irq(int card, int pci_int)
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{
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2017-06-19 06:46:08 +02:00
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int irq = ((pci_int - PCI_INTA) + (pci_irq_routing[card] - PCI_INTA)) & 3;
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2017-06-22 06:50:33 +02:00
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/* Do not clear the interrupt until we're the last card being serviced. */
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2017-08-27 23:57:47 +02:00
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if (pci_irq_routing[card] && (pci_irqs[irq] != PCI_IRQ_DISABLED))
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2017-06-02 01:38:25 +02:00
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{
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2017-08-27 23:57:47 +02:00
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/* pclog("Clearing PCI IRQ %i: ", pci_irqs[irq]); */
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if (pci_irq_is_level(pci_irqs[irq]))
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{
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pci_irq_hold[pci_irqs[irq]] &= ~(1 << card);
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/* pclog("Level "); */
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if (!pci_irq_hold[pci_irqs[irq]])
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{
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/* pclog("(clearing)\n"); */
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picintc(1 << pci_irqs[irq]);
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}
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else
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{
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/* pclog("(held)\n"); */
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}
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}
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else
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{
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/* pclog("Edge\n"); */
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picintc(1 << pci_irqs[irq]);
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}
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2017-06-02 01:38:25 +02:00
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}
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}
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2017-08-28 22:55:10 +02:00
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void pci_reset(void)
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{
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int i = 0;
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for (i = 0; i < 16; i++)
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{
|
|
|
|
|
if (pci_irq_hold[i])
|
|
|
|
|
{
|
|
|
|
|
pci_irq_hold[i] = 0;
|
|
|
|
|
|
|
|
|
|
picintc(1 << i);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
elcr_reset();
|
|
|
|
|
}
|
|
|
|
|
|
2017-06-02 01:38:25 +02:00
|
|
|
void pci_init(int type)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
|
|
|
|
int c;
|
|
|
|
|
|
|
|
|
|
PCI = 1;
|
2017-06-03 00:45:12 +02:00
|
|
|
|
2017-08-28 22:55:10 +02:00
|
|
|
pci_reset();
|
2017-06-21 19:42:36 +02:00
|
|
|
|
2017-06-03 00:45:12 +02:00
|
|
|
io_sethandler(0x04d0, 0x0002, elcr_read, NULL, NULL, elcr_write, NULL, NULL, NULL);
|
2016-06-26 00:34:39 +02:00
|
|
|
|
|
|
|
|
if (type == PCI_CONFIG_TYPE_1)
|
|
|
|
|
{
|
|
|
|
|
io_sethandler(0x0cf8, 0x0001, NULL, NULL, pci_cf8_read, NULL, NULL, pci_cf8_write, NULL);
|
|
|
|
|
io_sethandler(0x0cfc, 0x0004, pci_read, NULL, NULL, pci_write, NULL, NULL, NULL);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
io_sethandler(0x0cf8, 0x0001, pci_type2_read, NULL, NULL, pci_type2_write, NULL, NULL, NULL);
|
|
|
|
|
io_sethandler(0x0cfa, 0x0001, pci_type2_read, NULL, NULL, pci_type2_write, NULL, NULL, NULL);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (c = 0; c < 32; c++)
|
2017-06-02 01:38:25 +02:00
|
|
|
{
|
|
|
|
|
pci_card_read[c] = NULL;
|
|
|
|
|
pci_card_write[c] = NULL;
|
|
|
|
|
pci_priv[c] = NULL;
|
|
|
|
|
pci_irq_routing[c] = 0;
|
2017-06-22 06:50:33 +02:00
|
|
|
/* pci_irq_active[c] = 0; */
|
2017-06-02 01:38:25 +02:00
|
|
|
pci_card_valid[c] = 0;
|
|
|
|
|
}
|
2016-06-26 00:34:39 +02:00
|
|
|
|
2017-06-02 01:38:25 +02:00
|
|
|
for (c = 0; c < 4; c++)
|
|
|
|
|
pci_irqs[c] = PCI_IRQ_DISABLED;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void pci_slot(int card)
|
|
|
|
|
{
|
|
|
|
|
pci_card_valid[card] = 1;
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void pci_add_specific(int card, uint8_t (*read)(int func, int addr, void *priv), void (*write)(int func, int addr, uint8_t val, void *priv), void *priv)
|
|
|
|
|
{
|
|
|
|
|
pci_card_read[card] = read;
|
|
|
|
|
pci_card_write[card] = write;
|
|
|
|
|
pci_priv[card] = priv;
|
|
|
|
|
}
|
|
|
|
|
|
2017-06-02 01:38:25 +02:00
|
|
|
int pci_add(uint8_t (*read)(int func, int addr, void *priv), void (*write)(int func, int addr, uint8_t val, void *priv), void *priv)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
|
|
|
|
int c;
|
|
|
|
|
|
2017-06-02 01:38:25 +02:00
|
|
|
for (c = 0; c < 32; c++)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2017-06-02 01:38:25 +02:00
|
|
|
if (pci_card_valid[c] && !pci_card_read[c] && !pci_card_write[c])
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
|
|
|
|
pci_card_read[c] = read;
|
|
|
|
|
pci_card_write[c] = write;
|
|
|
|
|
pci_priv[c] = priv;
|
2017-06-02 01:38:25 +02:00
|
|
|
return c;
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
}
|
2017-06-02 01:38:25 +02:00
|
|
|
|
|
|
|
|
return -1;
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|