2017-05-30 03:38:38 +02:00
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/*
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2022-11-05 21:44:11 -04:00
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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2017-05-30 03:38:38 +02:00
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*
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2022-11-05 21:44:11 -04:00
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* This file is part of the 86Box distribution.
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2017-05-30 03:38:38 +02:00
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*
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2022-11-05 21:44:11 -04:00
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* Generic SVGA handling.
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2017-05-30 03:38:38 +02:00
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*
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2022-11-05 21:44:11 -04:00
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* This is intended to be used by another SVGA driver,
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* and not as a card in its own right.
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2017-05-30 03:38:38 +02:00
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*
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2020-03-25 00:46:02 +02:00
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*
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2017-09-23 21:12:26 -04:00
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*
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2023-01-06 15:36:29 -05:00
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* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
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2022-11-05 21:44:11 -04:00
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* Miran Grca, <mgrca8@gmail.com>
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2017-10-11 05:40:44 -04:00
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*
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2022-11-05 21:44:11 -04:00
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* Copyright 2008-2019 Sarah Walker.
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* Copyright 2016-2019 Miran Grca.
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2017-05-30 03:38:38 +02:00
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*/
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2018-01-25 19:35:23 +01:00
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#include <inttypes.h>
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2022-11-06 18:54:39 -05:00
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#include <stdarg.h>
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2016-07-19 02:44:32 +02:00
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#include <stdio.h>
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2017-09-25 04:31:20 -04:00
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#include <stdint.h>
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2021-07-04 18:22:52 +03:00
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#include <stdlib.h>
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2022-11-06 18:54:39 -05:00
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#include <string.h>
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2017-09-25 04:31:20 -04:00
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#include <wchar.h>
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2022-11-06 18:54:39 -05:00
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#define HAVE_STDARG_H
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2020-03-29 14:24:42 +02:00
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#include <86box/86box.h>
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2020-02-29 19:12:23 +01:00
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#include "cpu.h"
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2020-05-06 00:23:07 +02:00
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#include <86box/device.h>
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2020-03-29 14:24:42 +02:00
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#include <86box/machine.h>
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/pit.h>
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#include <86box/mem.h>
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#include <86box/rom.h>
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2021-04-13 14:07:21 -03:00
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#include <86box/plat.h>
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#include <86box/ui.h>
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2020-03-29 14:24:42 +02:00
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#include <86box/video.h>
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2023-10-09 20:14:03 +02:00
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#include <86box/vid_8514a.h>
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#include <86box/vid_xga.h>
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2020-03-29 14:24:42 +02:00
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#include <86box/vid_svga.h>
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#include <86box/vid_svga_render.h>
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2023-07-14 23:38:04 +02:00
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#include <86box/vid_xga_device.h>
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2017-05-06 17:48:33 +02:00
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2021-09-13 23:19:10 +02:00
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void svga_doblit(int wx, int wy, svga_t *svga);
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2024-05-29 20:47:22 +02:00
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void svga_poll(void *priv);
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2016-06-26 00:34:39 +02:00
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2022-05-14 19:26:41 +02:00
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svga_t *svga_8514;
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2022-08-31 19:19:29 -04:00
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extern int cyc_total;
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extern uint8_t edatlookup[4][4];
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2016-06-26 00:34:39 +02:00
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2022-06-12 17:31:54 +02:00
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uint8_t svga_rotate[8][256];
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2018-04-25 23:51:13 +02:00
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2016-06-26 00:34:39 +02:00
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/*Primary SVGA device. As multiple video cards are not yet supported this is the
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only SVGA device.*/
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2022-06-12 17:31:54 +02:00
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static svga_t *svga_pri;
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2018-04-25 23:51:13 +02:00
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2022-11-06 18:54:39 -05:00
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#ifdef ENABLE_SVGA_LOG
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int svga_do_log = ENABLE_SVGA_LOG;
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static void
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svga_log(const char *fmt, ...)
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{
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va_list ap;
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if (svga_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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# define svga_log(fmt, ...)
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#endif
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|
2022-11-17 22:44:06 +01:00
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svga_t *
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svga_get_pri(void)
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2018-04-25 23:51:13 +02:00
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{
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return svga_pri;
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}
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void
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svga_set_override(svga_t *svga, int val)
|
2016-06-26 00:34:39 +02:00
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{
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2024-11-02 20:50:06 +01:00
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ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
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2018-04-25 23:51:13 +02:00
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if (svga->override && !val)
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2023-01-22 16:50:21 +06:00
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svga->fullchange = svga->monitor->mon_changeframecount;
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2018-04-25 23:51:13 +02:00
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svga->override = val;
|
2019-10-20 15:09:38 +02:00
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2024-11-02 20:50:06 +01:00
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svga_log("Override=%x.\n", val);
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if (ibm8514_active && (svga->dev8514 != NULL)) {
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if (dev->on) {
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if (svga->override)
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timer_set_callback(&svga->timer, svga_poll);
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else
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timer_set_callback(&svga->timer, ibm8514_poll);
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} else
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timer_set_callback(&svga->timer, svga_poll);
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} else
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timer_set_callback(&svga->timer, svga_poll);
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|
2024-04-02 00:08:40 +02:00
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#ifdef OVERRIDE_OVERSCAN
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2019-10-20 15:09:38 +02:00
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if (!val) {
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2022-08-31 19:19:29 -04:00
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/* Override turned off, restore overscan X and Y per the CRTC. */
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2024-01-09 17:38:54 +01:00
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svga->monitor->mon_overscan_y = (svga->rowcount + 1) << 1;
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2019-10-20 15:09:38 +02:00
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2024-01-09 17:38:54 +01:00
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if (svga->monitor->mon_overscan_y < 16)
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svga->monitor->mon_overscan_y = 16;
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2019-10-20 15:09:38 +02:00
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2023-01-22 16:50:21 +06:00
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svga->monitor->mon_overscan_x = (svga->seqregs[1] & 1) ? 16 : 18;
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2019-10-20 15:09:38 +02:00
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2022-08-31 19:19:29 -04:00
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if (svga->seqregs[1] & 8)
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2023-01-22 16:50:21 +06:00
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svga->monitor->mon_overscan_x <<= 1;
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2019-10-20 15:09:38 +02:00
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} else
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2023-01-22 16:50:21 +06:00
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svga->monitor->mon_overscan_x = svga->monitor->mon_overscan_y = 16;
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2022-08-31 19:19:29 -04:00
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/* Override turned off, fix overcan X and Y to 16. */
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2024-04-02 00:08:40 +02:00
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#endif
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2016-06-26 00:34:39 +02:00
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}
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2018-04-25 23:51:13 +02:00
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void
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2023-06-09 23:46:54 -04:00
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svga_out(uint16_t addr, uint8_t val, void *priv)
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2016-06-26 00:34:39 +02:00
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{
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2023-08-11 20:32:56 -04:00
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svga_t *svga = (svga_t *) priv;
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2023-10-09 20:14:03 +02:00
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ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
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xga_t *xga = (xga_t *) svga->xga;
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2023-08-11 20:32:56 -04:00
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uint8_t o;
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uint8_t index;
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2023-12-27 21:01:25 +01:00
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uint8_t pal4to16[16] = { 0, 7, 0x38, 0x3f, 0, 3, 4, 0x3f, 0, 2, 4, 0x3e, 0, 3, 5, 0x3f };
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2018-04-25 23:51:13 +02:00
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2024-11-02 20:50:06 +01:00
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if ((addr >= 0x2ea) && (addr <= 0x2ed)) {
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if (!dev)
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return;
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}
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2024-05-29 20:47:22 +02:00
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2018-04-25 23:51:13 +02:00
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switch (addr) {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
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case 0x2ea:
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dev->dac_mask = val;
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break;
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case 0x2eb:
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case 0x2ec:
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dev->dac_pos = 0;
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dev->dac_status = addr & 0x03;
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dev->dac_addr = (val + (addr & 0x01)) & 0xff;
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break;
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case 0x2ed:
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svga->fullchange = svga->monitor->mon_changeframecount;
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switch (dev->dac_pos) {
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case 0:
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dev->dac_r = val;
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dev->dac_pos++;
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break;
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case 1:
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dev->dac_g = val;
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dev->dac_pos++;
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break;
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case 2:
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|
index = dev->dac_addr & 0xff;
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dev->dac_b = val;
|
2024-10-26 21:32:47 +02:00
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dev->_8514pal[index].r = dev->dac_r;
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|
|
dev->_8514pal[index].g = dev->dac_g;
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dev->_8514pal[index].b = dev->dac_b;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (svga->ramdac_type == RAMDAC_8BIT)
|
2024-10-26 21:32:47 +02:00
|
|
|
dev->pallook[index] = makecol32(dev->_8514pal[index].r, dev->_8514pal[index].g, dev->_8514pal[index].b);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
else
|
2024-10-26 21:32:47 +02:00
|
|
|
dev->pallook[index] = makecol32(video_6to8[dev->_8514pal[index].r & 0x3f], video_6to8[dev->_8514pal[index].g & 0x3f], video_6to8[dev->_8514pal[index].b & 0x3f]);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
dev->dac_pos = 0;
|
|
|
|
|
dev->dac_addr = (dev->dac_addr + 1) & 0xff;
|
|
|
|
|
break;
|
2023-08-11 20:32:56 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
case 0x3c0:
|
|
|
|
|
case 0x3c1:
|
|
|
|
|
if (!svga->attrff) {
|
2023-12-27 21:01:25 +01:00
|
|
|
svga->attraddr = val & 0x1f;
|
2022-08-31 19:19:29 -04:00
|
|
|
if ((val & 0x20) != svga->attr_palette_enable) {
|
|
|
|
|
svga->fullchange = 3;
|
|
|
|
|
svga->attr_palette_enable = val & 0x20;
|
2024-11-02 20:50:06 +01:00
|
|
|
svga_log("Write Port %03x palette enable=%02x.\n", addr, svga->attr_palette_enable);
|
2022-08-31 19:19:29 -04:00
|
|
|
svga_recalctimings(svga);
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
if ((svga->attraddr == 0x13) && (svga->attrregs[0x13] != val))
|
2023-01-22 16:50:21 +06:00
|
|
|
svga->fullchange = svga->monitor->mon_changeframecount;
|
2023-12-27 21:01:25 +01:00
|
|
|
o = svga->attrregs[svga->attraddr & 0x1f];
|
|
|
|
|
svga->attrregs[svga->attraddr & 0x1f] = val;
|
|
|
|
|
if (svga->attraddr < 0x10)
|
2023-01-22 16:50:21 +06:00
|
|
|
svga->fullchange = svga->monitor->mon_changeframecount;
|
2023-12-27 21:01:25 +01:00
|
|
|
|
|
|
|
|
if ((svga->attraddr == 0x10) || (svga->attraddr == 0x14) || (svga->attraddr < 0x10)) {
|
|
|
|
|
for (int c = 0; c < 0x10; c++) {
|
|
|
|
|
if (svga->attrregs[0x10] & 0x80)
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->egapal[c] = (svga->attrregs[c] & 0xf) | ((svga->attrregs[0x14] & 0xf) << 4);
|
2023-12-27 21:01:25 +01:00
|
|
|
else if (svga->ati_4color)
|
|
|
|
|
svga->egapal[c] = pal4to16[(c & 0x03) | ((val >> 2) & 0xc)];
|
|
|
|
|
else
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->egapal[c] = (svga->attrregs[c] & 0x3f) | ((svga->attrregs[0x14] & 0xc) << 4);
|
|
|
|
|
}
|
2023-01-22 16:50:21 +06:00
|
|
|
svga->fullchange = svga->monitor->mon_changeframecount;
|
2022-08-31 19:19:29 -04:00
|
|
|
}
|
|
|
|
|
/* Recalculate timings on change of attribute register 0x11
|
|
|
|
|
(overscan border color) too. */
|
|
|
|
|
if (svga->attraddr == 0x10) {
|
2024-11-02 20:50:06 +01:00
|
|
|
if (o != val) {
|
|
|
|
|
svga_log("ATTR10.\n");
|
2022-08-31 19:19:29 -04:00
|
|
|
svga_recalctimings(svga);
|
2024-11-02 20:50:06 +01:00
|
|
|
}
|
2022-08-31 19:19:29 -04:00
|
|
|
} else if (svga->attraddr == 0x11) {
|
|
|
|
|
svga->overscan_color = svga->pallook[svga->attrregs[0x11]];
|
2024-11-02 20:50:06 +01:00
|
|
|
if (o != val) {
|
|
|
|
|
svga_log("ATTR11.\n");
|
2022-08-31 19:19:29 -04:00
|
|
|
svga_recalctimings(svga);
|
2024-11-02 20:50:06 +01:00
|
|
|
}
|
2022-08-31 19:19:29 -04:00
|
|
|
} else if (svga->attraddr == 0x12) {
|
|
|
|
|
if ((val & 0xf) != svga->plane_mask)
|
2023-01-22 16:50:21 +06:00
|
|
|
svga->fullchange = svga->monitor->mon_changeframecount;
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->plane_mask = val & 0xf;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
svga->attrff ^= 1;
|
|
|
|
|
break;
|
|
|
|
|
case 0x3c2:
|
|
|
|
|
svga->miscout = val;
|
|
|
|
|
svga->vidclock = val & 4;
|
2023-06-09 23:46:54 -04:00
|
|
|
io_removehandler(0x03a0, 0x0020, svga->video_in, NULL, NULL, svga->video_out, NULL, NULL, svga->priv);
|
2022-08-31 19:19:29 -04:00
|
|
|
if (!(val & 1))
|
2023-06-09 23:46:54 -04:00
|
|
|
io_sethandler(0x03a0, 0x0020, svga->video_in, NULL, NULL, svga->video_out, NULL, NULL, svga->priv);
|
2022-08-31 19:19:29 -04:00
|
|
|
svga_recalctimings(svga);
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
case 0x3c3:
|
2023-11-08 23:47:16 +01:00
|
|
|
if (xga_active && xga)
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
xga->on = (val & 0x01) ? 0 : 1;
|
2024-10-26 21:32:47 +02:00
|
|
|
if (ibm8514_active && dev)
|
|
|
|
|
dev->on = (val & 0x01) ? 0 : 1;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
|
2024-11-02 20:50:06 +01:00
|
|
|
svga_log("Write Port 3C3.\n");
|
2024-02-07 01:53:16 +01:00
|
|
|
svga_recalctimings(svga);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
2022-08-31 19:19:29 -04:00
|
|
|
case 0x3c4:
|
|
|
|
|
svga->seqaddr = val;
|
|
|
|
|
break;
|
|
|
|
|
case 0x3c5:
|
|
|
|
|
if (svga->seqaddr > 0xf)
|
|
|
|
|
return;
|
|
|
|
|
o = svga->seqregs[svga->seqaddr & 0xf];
|
|
|
|
|
svga->seqregs[svga->seqaddr & 0xf] = val;
|
2024-11-02 20:50:06 +01:00
|
|
|
if (o != val && (svga->seqaddr & 0xf) == 1) {
|
|
|
|
|
svga_log("SEQADDR1 write1.\n");
|
2022-08-31 19:19:29 -04:00
|
|
|
svga_recalctimings(svga);
|
2024-11-02 20:50:06 +01:00
|
|
|
}
|
2022-08-31 19:19:29 -04:00
|
|
|
switch (svga->seqaddr & 0xf) {
|
|
|
|
|
case 1:
|
|
|
|
|
if (svga->scrblank && !(val & 0x20))
|
|
|
|
|
svga->fullchange = 3;
|
|
|
|
|
svga->scrblank = (svga->scrblank & ~0x20) | (val & 0x20);
|
2024-11-02 20:50:06 +01:00
|
|
|
svga_log("SEQADDR1 write2.\n");
|
2022-08-31 19:19:29 -04:00
|
|
|
svga_recalctimings(svga);
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
svga->writemask = val & 0xf;
|
|
|
|
|
break;
|
|
|
|
|
case 3:
|
|
|
|
|
svga->charsetb = (((val >> 2) & 3) * 0x10000) + 2;
|
|
|
|
|
svga->charseta = ((val & 3) * 0x10000) + 2;
|
|
|
|
|
if (val & 0x10)
|
|
|
|
|
svga->charseta += 0x8000;
|
|
|
|
|
if (val & 0x20)
|
|
|
|
|
svga->charsetb += 0x8000;
|
|
|
|
|
break;
|
|
|
|
|
case 4:
|
|
|
|
|
svga->chain2_write = !(val & 4);
|
2023-08-06 20:29:39 -04:00
|
|
|
svga->chain4 = (svga->chain4 & ~8) | (val & 8);
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->fast = (svga->gdcreg[8] == 0xff && !(svga->gdcreg[3] & 0x18) && !svga->gdcreg[1]) && ((svga->chain4 && (svga->packed_chain4 || svga->force_old_addr)) || svga->fb_only) && !(svga->adv_flags & FLAG_ADDR_BY8);
|
|
|
|
|
break;
|
2023-07-30 19:22:43 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2022-08-31 19:19:29 -04:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0x3c6:
|
|
|
|
|
svga->dac_mask = val;
|
|
|
|
|
break;
|
|
|
|
|
case 0x3c7:
|
|
|
|
|
case 0x3c8:
|
|
|
|
|
svga->dac_pos = 0;
|
|
|
|
|
svga->dac_status = addr & 0x03;
|
2024-11-02 20:50:06 +01:00
|
|
|
svga->dac_addr = (val + (addr & 0x01)) & 0xff;
|
2022-08-31 19:19:29 -04:00
|
|
|
break;
|
|
|
|
|
case 0x3c9:
|
|
|
|
|
if (svga->adv_flags & FLAG_RAMDAC_SHIFT)
|
|
|
|
|
val <<= 2;
|
2023-01-22 16:50:21 +06:00
|
|
|
svga->fullchange = svga->monitor->mon_changeframecount;
|
2022-08-31 19:19:29 -04:00
|
|
|
switch (svga->dac_pos) {
|
|
|
|
|
case 0:
|
|
|
|
|
svga->dac_r = val;
|
|
|
|
|
svga->dac_pos++;
|
|
|
|
|
break;
|
|
|
|
|
case 1:
|
|
|
|
|
svga->dac_g = val;
|
|
|
|
|
svga->dac_pos++;
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
2024-11-02 20:50:06 +01:00
|
|
|
index = svga->dac_addr & 0xff;
|
2023-08-11 20:32:56 -04:00
|
|
|
svga->dac_b = val;
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->vgapal[index].r = svga->dac_r;
|
|
|
|
|
svga->vgapal[index].g = svga->dac_g;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
svga->vgapal[index].b = svga->dac_b;
|
2022-08-31 19:19:29 -04:00
|
|
|
if (svga->ramdac_type == RAMDAC_8BIT)
|
|
|
|
|
svga->pallook[index] = makecol32(svga->vgapal[index].r, svga->vgapal[index].g, svga->vgapal[index].b);
|
|
|
|
|
else
|
|
|
|
|
svga->pallook[index] = makecol32(video_6to8[svga->vgapal[index].r & 0x3f], video_6to8[svga->vgapal[index].g & 0x3f], video_6to8[svga->vgapal[index].b & 0x3f]);
|
|
|
|
|
svga->dac_pos = 0;
|
2024-11-02 20:50:06 +01:00
|
|
|
svga->dac_addr = (svga->dac_addr + 1) & 0xff;
|
2022-08-31 19:19:29 -04:00
|
|
|
break;
|
2023-07-30 19:22:43 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2022-08-31 19:19:29 -04:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0x3ce:
|
|
|
|
|
svga->gdcaddr = val;
|
|
|
|
|
break;
|
|
|
|
|
case 0x3cf:
|
|
|
|
|
o = svga->gdcreg[svga->gdcaddr & 15];
|
|
|
|
|
switch (svga->gdcaddr & 15) {
|
|
|
|
|
case 2:
|
|
|
|
|
svga->colourcompare = val;
|
|
|
|
|
break;
|
|
|
|
|
case 4:
|
|
|
|
|
svga->readplane = val & 3;
|
|
|
|
|
break;
|
|
|
|
|
case 5:
|
|
|
|
|
svga->writemode = val & 3;
|
|
|
|
|
svga->readmode = val & 8;
|
|
|
|
|
svga->chain2_read = val & 0x10;
|
|
|
|
|
break;
|
|
|
|
|
case 6:
|
|
|
|
|
if ((svga->gdcreg[6] & 0xc) != (val & 0xc)) {
|
2022-11-06 18:54:39 -05:00
|
|
|
switch (val & 0xc) {
|
2022-08-31 19:19:29 -04:00
|
|
|
case 0x0: /*128k at A0000*/
|
|
|
|
|
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000);
|
|
|
|
|
svga->banked_mask = 0xffff;
|
|
|
|
|
break;
|
|
|
|
|
case 0x4: /*64k at A0000*/
|
|
|
|
|
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
|
|
|
|
|
svga->banked_mask = 0xffff;
|
|
|
|
|
break;
|
|
|
|
|
case 0x8: /*32k at B0000*/
|
|
|
|
|
mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000);
|
|
|
|
|
svga->banked_mask = 0x7fff;
|
|
|
|
|
break;
|
|
|
|
|
case 0xC: /*32k at B8000*/
|
|
|
|
|
mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000);
|
|
|
|
|
svga->banked_mask = 0x7fff;
|
|
|
|
|
break;
|
2023-07-30 19:22:43 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2022-08-31 19:19:29 -04:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 7:
|
|
|
|
|
svga->colournocare = val;
|
|
|
|
|
break;
|
2023-07-30 19:22:43 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2022-08-31 19:19:29 -04:00
|
|
|
}
|
|
|
|
|
svga->gdcreg[svga->gdcaddr & 15] = val;
|
|
|
|
|
svga->fast = (svga->gdcreg[8] == 0xff && !(svga->gdcreg[3] & 0x18) && !svga->gdcreg[1]) && ((svga->chain4 && (svga->packed_chain4 || svga->force_old_addr)) || svga->fb_only);
|
2024-11-02 20:50:06 +01:00
|
|
|
if (((svga->gdcaddr & 15) == 5 && (val ^ o) & 0x70) || ((svga->gdcaddr & 15) == 6 && (val ^ o) & 1)) {
|
|
|
|
|
svga_log("GDCADDR%02x recalc.\n", svga->gdcaddr & 0x0f);
|
2022-08-31 19:19:29 -04:00
|
|
|
svga_recalctimings(svga);
|
2024-11-02 20:50:06 +01:00
|
|
|
}
|
2022-08-31 19:19:29 -04:00
|
|
|
break;
|
2023-08-06 20:29:39 -04:00
|
|
|
case 0x3da:
|
|
|
|
|
svga->fcr = val;
|
|
|
|
|
break;
|
2023-07-30 19:22:43 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2018-04-25 23:51:13 +02:00
|
|
|
}
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
uint8_t
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_in(uint16_t addr, void *priv)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2023-08-11 20:32:56 -04:00
|
|
|
svga_t *svga = (svga_t *) priv;
|
2023-10-09 20:14:03 +02:00
|
|
|
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
2024-11-02 20:50:06 +01:00
|
|
|
xga_t *xga = (xga_t *) svga->xga;
|
2023-08-11 20:32:56 -04:00
|
|
|
uint8_t index;
|
|
|
|
|
uint8_t ret = 0xff;
|
2018-04-25 23:51:13 +02:00
|
|
|
|
2024-11-02 20:50:06 +01:00
|
|
|
if ((addr >= 0x2ea) && (addr <= 0x2ed)) {
|
|
|
|
|
if (!dev)
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
2018-04-25 23:51:13 +02:00
|
|
|
|
|
|
|
|
switch (addr) {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x2ea:
|
|
|
|
|
ret = dev->dac_mask;
|
|
|
|
|
break;
|
|
|
|
|
case 0x2eb:
|
|
|
|
|
ret = dev->dac_status;
|
|
|
|
|
break;
|
|
|
|
|
case 0x2ec:
|
|
|
|
|
ret = dev->dac_addr;
|
|
|
|
|
break;
|
|
|
|
|
case 0x2ed:
|
|
|
|
|
index = (dev->dac_addr - 1) & 0xff;
|
|
|
|
|
switch (dev->dac_pos) {
|
|
|
|
|
case 0:
|
|
|
|
|
dev->dac_pos++;
|
|
|
|
|
if (svga->ramdac_type == RAMDAC_8BIT)
|
2024-10-26 21:32:47 +02:00
|
|
|
ret = dev->_8514pal[index].r;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
else
|
2024-10-26 21:32:47 +02:00
|
|
|
ret = dev->_8514pal[index].r & 0x3f;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
break;
|
|
|
|
|
case 1:
|
|
|
|
|
dev->dac_pos++;
|
|
|
|
|
if (svga->ramdac_type == RAMDAC_8BIT)
|
2024-10-26 21:32:47 +02:00
|
|
|
ret = dev->_8514pal[index].g;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
else
|
2024-10-26 21:32:47 +02:00
|
|
|
ret = dev->_8514pal[index].g & 0x3f;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
dev->dac_pos = 0;
|
|
|
|
|
dev->dac_addr = (dev->dac_addr + 1) & 0xff;
|
|
|
|
|
if (svga->ramdac_type == RAMDAC_8BIT)
|
2024-10-26 21:32:47 +02:00
|
|
|
ret = dev->_8514pal[index].b;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
else
|
2024-10-26 21:32:47 +02:00
|
|
|
ret = dev->_8514pal[index].b & 0x3f;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
break;
|
|
|
|
|
|
2023-08-11 20:32:56 -04:00
|
|
|
default:
|
|
|
|
|
break;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
case 0x3c0:
|
|
|
|
|
ret = svga->attraddr | svga->attr_palette_enable;
|
|
|
|
|
break;
|
|
|
|
|
case 0x3c1:
|
|
|
|
|
ret = svga->attrregs[svga->attraddr];
|
|
|
|
|
break;
|
|
|
|
|
case 0x3c2:
|
|
|
|
|
if ((svga->vgapal[0].r + svga->vgapal[0].g + svga->vgapal[0].b) >= 0x4e)
|
|
|
|
|
ret = 0;
|
|
|
|
|
else
|
|
|
|
|
ret = 0x10;
|
|
|
|
|
break;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x3c3:
|
2024-11-02 20:50:06 +01:00
|
|
|
ret = 0x00;
|
|
|
|
|
if (xga_active && xga)
|
|
|
|
|
ret |= !xga->on;
|
|
|
|
|
if (ibm8514_active && dev)
|
|
|
|
|
ret |= !dev->on;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
break;
|
2022-08-31 19:19:29 -04:00
|
|
|
case 0x3c4:
|
|
|
|
|
ret = svga->seqaddr;
|
|
|
|
|
break;
|
|
|
|
|
case 0x3c5:
|
|
|
|
|
ret = svga->seqregs[svga->seqaddr & 0x0f];
|
|
|
|
|
break;
|
|
|
|
|
case 0x3c6:
|
|
|
|
|
ret = svga->dac_mask;
|
|
|
|
|
break;
|
|
|
|
|
case 0x3c7:
|
|
|
|
|
ret = svga->dac_status;
|
|
|
|
|
break;
|
|
|
|
|
case 0x3c8:
|
|
|
|
|
ret = svga->dac_addr;
|
|
|
|
|
break;
|
|
|
|
|
case 0x3c9:
|
2024-11-02 20:50:06 +01:00
|
|
|
index = (svga->dac_addr - 1) & 0xff;
|
2022-08-31 19:19:29 -04:00
|
|
|
switch (svga->dac_pos) {
|
|
|
|
|
case 0:
|
|
|
|
|
svga->dac_pos++;
|
|
|
|
|
if (svga->ramdac_type == RAMDAC_8BIT)
|
|
|
|
|
ret = svga->vgapal[index].r;
|
|
|
|
|
else
|
|
|
|
|
ret = svga->vgapal[index].r & 0x3f;
|
|
|
|
|
break;
|
|
|
|
|
case 1:
|
|
|
|
|
svga->dac_pos++;
|
|
|
|
|
if (svga->ramdac_type == RAMDAC_8BIT)
|
|
|
|
|
ret = svga->vgapal[index].g;
|
|
|
|
|
else
|
|
|
|
|
ret = svga->vgapal[index].g & 0x3f;
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
svga->dac_pos = 0;
|
2024-11-02 20:50:06 +01:00
|
|
|
svga->dac_addr = (svga->dac_addr + 1) & 0xff;
|
2022-08-31 19:19:29 -04:00
|
|
|
if (svga->ramdac_type == RAMDAC_8BIT)
|
|
|
|
|
ret = svga->vgapal[index].b;
|
|
|
|
|
else
|
|
|
|
|
ret = svga->vgapal[index].b & 0x3f;
|
|
|
|
|
break;
|
2023-07-30 19:22:43 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2022-08-31 19:19:29 -04:00
|
|
|
}
|
|
|
|
|
if (svga->adv_flags & FLAG_RAMDAC_SHIFT)
|
|
|
|
|
ret >>= 2;
|
|
|
|
|
break;
|
2023-08-06 20:29:39 -04:00
|
|
|
case 0x3ca:
|
|
|
|
|
ret = svga->fcr;
|
|
|
|
|
break;
|
2022-08-31 19:19:29 -04:00
|
|
|
case 0x3cc:
|
|
|
|
|
ret = svga->miscout;
|
|
|
|
|
break;
|
|
|
|
|
case 0x3ce:
|
|
|
|
|
ret = svga->gdcaddr;
|
|
|
|
|
break;
|
|
|
|
|
case 0x3cf:
|
|
|
|
|
/* The spec says GDC addresses 0xF8 to 0xFB return the latch. */
|
|
|
|
|
switch (svga->gdcaddr) {
|
|
|
|
|
case 0xf8:
|
|
|
|
|
ret = svga->latch.b[0];
|
|
|
|
|
break;
|
|
|
|
|
case 0xf9:
|
|
|
|
|
ret = svga->latch.b[1];
|
|
|
|
|
break;
|
|
|
|
|
case 0xfa:
|
|
|
|
|
ret = svga->latch.b[2];
|
|
|
|
|
break;
|
|
|
|
|
case 0xfb:
|
|
|
|
|
ret = svga->latch.b[3];
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
ret = svga->gdcreg[svga->gdcaddr & 0xf];
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0x3da:
|
|
|
|
|
svga->attrff = 0;
|
|
|
|
|
|
|
|
|
|
if (svga->cgastat & 0x01)
|
|
|
|
|
svga->cgastat &= ~0x30;
|
|
|
|
|
else
|
|
|
|
|
svga->cgastat ^= 0x30;
|
2022-11-06 18:54:39 -05:00
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
ret = svga->cgastat;
|
2022-11-06 18:54:39 -05:00
|
|
|
|
2023-08-06 20:29:39 -04:00
|
|
|
if ((svga->fcr & 0x08) && svga->dispon)
|
|
|
|
|
ret |= 0x08;
|
2022-08-31 19:19:29 -04:00
|
|
|
break;
|
2023-07-30 19:22:43 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2018-04-25 23:51:13 +02:00
|
|
|
}
|
|
|
|
|
|
2024-05-29 20:47:22 +02:00
|
|
|
if ((addr >= 0x3c6) && (addr <= 0x3c9))
|
|
|
|
|
svga_log("VGA IN addr=%03x, temp=%02x.\n", addr, ret);
|
|
|
|
|
|
2023-06-01 18:32:25 -04:00
|
|
|
return ret;
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
void
|
|
|
|
|
svga_set_ramdac_type(svga_t *svga, int type)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2023-10-09 20:14:03 +02:00
|
|
|
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
|
|
|
|
xga_t *xga = (xga_t *) svga->xga;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
if (svga->ramdac_type != type) {
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->ramdac_type = type;
|
|
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
for (int c = 0; c < 256; c++) {
|
2023-11-08 23:47:16 +01:00
|
|
|
if (ibm8514_active && dev) {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (svga->ramdac_type == RAMDAC_8BIT)
|
2024-10-26 21:32:47 +02:00
|
|
|
dev->pallook[c] = makecol32(dev->_8514pal[c].r, dev->_8514pal[c].g, dev->_8514pal[c].b);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
else
|
2024-10-26 21:32:47 +02:00
|
|
|
dev->pallook[c] = makecol32((dev->_8514pal[c].r & 0x3f) * 4,
|
|
|
|
|
(dev->_8514pal[c].g & 0x3f) * 4,
|
|
|
|
|
(dev->_8514pal[c].b & 0x3f) * 4);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
}
|
2023-11-08 23:47:16 +01:00
|
|
|
if (xga_active && xga) {
|
2023-08-24 00:30:21 +02:00
|
|
|
if (svga->ramdac_type == RAMDAC_8BIT)
|
2024-10-03 14:56:23 +02:00
|
|
|
xga->pallook[c] = makecol32(xga->xgapal[c].r, xga->xgapal[c].g, xga->xgapal[c].b);
|
|
|
|
|
else {
|
|
|
|
|
xga->pallook[c] = makecol32((xga->xgapal[c].r & 0x3f) * 4,
|
|
|
|
|
(xga->xgapal[c].g & 0x3f) * 4,
|
|
|
|
|
(xga->xgapal[c].b & 0x3f) * 4);
|
|
|
|
|
}
|
2023-08-24 00:30:21 +02:00
|
|
|
}
|
2022-08-31 19:19:29 -04:00
|
|
|
if (svga->ramdac_type == RAMDAC_8BIT)
|
|
|
|
|
svga->pallook[c] = makecol32(svga->vgapal[c].r, svga->vgapal[c].g, svga->vgapal[c].b);
|
|
|
|
|
else
|
|
|
|
|
svga->pallook[c] = makecol32((svga->vgapal[c].r & 0x3f) * 4,
|
|
|
|
|
(svga->vgapal[c].g & 0x3f) * 4,
|
|
|
|
|
(svga->vgapal[c].b & 0x3f) * 4);
|
|
|
|
|
}
|
2018-04-25 23:51:13 +02:00
|
|
|
}
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
void
|
|
|
|
|
svga_recalctimings(svga_t *svga)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2024-02-07 01:53:16 +01:00
|
|
|
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
2023-08-11 20:32:56 -04:00
|
|
|
double crtcconst;
|
|
|
|
|
double _dispontime;
|
|
|
|
|
double _dispofftime;
|
|
|
|
|
double disptime;
|
2024-02-07 20:56:25 +01:00
|
|
|
double crtcconst8514 = 0.0;
|
|
|
|
|
double _dispontime8514 = 0.0;
|
|
|
|
|
double _dispofftime8514 = 0.0;
|
|
|
|
|
double disptime8514 = 0.0;
|
2023-08-06 20:29:39 -04:00
|
|
|
#ifdef ENABLE_SVGA_LOG
|
2024-01-10 08:59:46 +01:00
|
|
|
int vsyncend;
|
|
|
|
|
int vblankend;
|
|
|
|
|
int hdispstart;
|
|
|
|
|
int hdispend;
|
|
|
|
|
int hsyncstart;
|
|
|
|
|
int hsyncend;
|
2023-08-06 20:29:39 -04:00
|
|
|
#endif
|
2018-04-25 23:51:13 +02:00
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->vtotal = svga->crtc[6];
|
|
|
|
|
svga->dispend = svga->crtc[0x12];
|
|
|
|
|
svga->vsyncstart = svga->crtc[0x10];
|
|
|
|
|
svga->split = svga->crtc[0x18];
|
2018-04-25 23:51:13 +02:00
|
|
|
svga->vblankstart = svga->crtc[0x15];
|
|
|
|
|
|
|
|
|
|
if (svga->crtc[7] & 1)
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->vtotal |= 0x100;
|
2018-04-25 23:51:13 +02:00
|
|
|
if (svga->crtc[7] & 32)
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->vtotal |= 0x200;
|
2018-04-25 23:51:13 +02:00
|
|
|
svga->vtotal += 2;
|
|
|
|
|
|
|
|
|
|
if (svga->crtc[7] & 2)
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->dispend |= 0x100;
|
2018-04-25 23:51:13 +02:00
|
|
|
if (svga->crtc[7] & 64)
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->dispend |= 0x200;
|
2018-04-25 23:51:13 +02:00
|
|
|
svga->dispend++;
|
|
|
|
|
|
|
|
|
|
if (svga->crtc[7] & 4)
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->vsyncstart |= 0x100;
|
2018-04-25 23:51:13 +02:00
|
|
|
if (svga->crtc[7] & 128)
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->vsyncstart |= 0x200;
|
2018-04-25 23:51:13 +02:00
|
|
|
svga->vsyncstart++;
|
|
|
|
|
|
|
|
|
|
if (svga->crtc[7] & 0x10)
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->split |= 0x100;
|
2018-04-25 23:51:13 +02:00
|
|
|
if (svga->crtc[9] & 0x40)
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->split |= 0x200;
|
2018-04-25 23:51:13 +02:00
|
|
|
svga->split++;
|
|
|
|
|
|
|
|
|
|
if (svga->crtc[7] & 0x08)
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->vblankstart |= 0x100;
|
2018-04-25 23:51:13 +02:00
|
|
|
if (svga->crtc[9] & 0x20)
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->vblankstart |= 0x200;
|
2018-04-25 23:51:13 +02:00
|
|
|
svga->vblankstart++;
|
|
|
|
|
|
2024-01-11 02:11:23 +01:00
|
|
|
svga->hdisp = svga->crtc[1];
|
2018-04-25 23:51:13 +02:00
|
|
|
svga->hdisp++;
|
|
|
|
|
|
2021-07-04 18:22:52 +03:00
|
|
|
svga->htotal = svga->crtc[0];
|
2023-02-05 17:16:53 +01:00
|
|
|
/* +5 has been verified by Sergi to be correct - +6 must have been an off by one error. */
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
svga->htotal += 5; /*+5 is required for Tyrian*/
|
2021-07-04 18:22:52 +03:00
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
svga->rowoffset = svga->crtc[0x13];
|
|
|
|
|
|
|
|
|
|
svga->clock = (svga->vidclock) ? VGACONST2 : VGACONST1;
|
|
|
|
|
|
2023-12-06 15:00:31 +01:00
|
|
|
svga->lowres = !!(svga->attrregs[0x10] & 0x40);
|
2018-04-25 23:51:13 +02:00
|
|
|
|
|
|
|
|
svga->interlace = 0;
|
|
|
|
|
|
2020-12-20 21:14:24 +01:00
|
|
|
svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]) + ((svga->crtc[8] & 0x60) >> 5);
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->ca_adj = 0;
|
2022-02-20 02:26:27 -05:00
|
|
|
|
2023-12-27 15:47:42 +01:00
|
|
|
svga->rowcount = svga->crtc[9] & 0x1f;
|
2018-04-25 23:51:13 +02:00
|
|
|
|
|
|
|
|
svga->hdisp_time = svga->hdisp;
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->render = svga_render_blank;
|
2022-07-18 23:56:21 +02:00
|
|
|
if (!svga->scrblank && (svga->crtc[0x17] & 0x80) && svga->attr_palette_enable) {
|
2024-01-11 01:56:32 +01:00
|
|
|
/* TODO: In case of bug reports, disable 9-dots-wide character clocks in graphics modes. */
|
2024-02-07 00:11:02 +01:00
|
|
|
if (!(svga->gdcreg[6] & 1) && !(svga->attrregs[0x10] & 1)) {
|
|
|
|
|
if (svga->seqregs[1] & 8)
|
|
|
|
|
svga->hdisp *= (svga->seqregs[1] & 1) ? 16 : 18;
|
|
|
|
|
else
|
|
|
|
|
svga->hdisp *= (svga->seqregs[1] & 1) ? 8 : 9;
|
|
|
|
|
} else {
|
|
|
|
|
if (svga->seqregs[1] & 8)
|
|
|
|
|
svga->hdisp *= 16;
|
|
|
|
|
else
|
|
|
|
|
svga->hdisp *= 8;
|
|
|
|
|
}
|
2023-08-06 20:29:39 -04:00
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
if (!(svga->gdcreg[6] & 1) && !(svga->attrregs[0x10] & 1)) { /*Text mode*/
|
2024-10-03 14:56:23 +02:00
|
|
|
if (svga->seqregs[1] & 8) { /*40 column*/
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->render = svga_render_text_40;
|
2024-10-03 14:56:23 +02:00
|
|
|
} else
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->render = svga_render_text_80;
|
2024-10-03 14:56:23 +02:00
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->hdisp_old = svga->hdisp;
|
|
|
|
|
} else {
|
|
|
|
|
svga->hdisp_old = svga->hdisp;
|
|
|
|
|
|
2023-12-27 15:47:42 +01:00
|
|
|
if ((svga->bpp <= 8) || ((svga->gdcreg[5] & 0x60) <= 0x20)) {
|
2023-12-18 13:42:32 +01:00
|
|
|
if ((svga->gdcreg[5] & 0x60) == 0x00) {
|
2022-08-31 19:19:29 -04:00
|
|
|
if (svga->seqregs[1] & 8) /*Low res (320)*/
|
|
|
|
|
svga->render = svga_render_4bpp_lowres;
|
|
|
|
|
else
|
|
|
|
|
svga->render = svga_render_4bpp_highres;
|
2023-12-27 15:47:42 +01:00
|
|
|
} else if ((svga->gdcreg[5] & 0x60) == 0x20) {
|
2024-07-26 00:39:11 +02:00
|
|
|
if (svga->seqregs[1] & 8) { /*Low res (320)*/
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->render = svga_render_2bpp_lowres;
|
2024-08-12 19:52:52 +02:00
|
|
|
svga_log("2 bpp low res\n");
|
2024-07-26 00:39:11 +02:00
|
|
|
} else
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->render = svga_render_2bpp_highres;
|
2023-12-18 13:42:32 +01:00
|
|
|
} else {
|
|
|
|
|
svga->map8 = svga->pallook;
|
2023-12-27 15:47:42 +01:00
|
|
|
if (svga->lowres) /*Low res (320)*/
|
2023-12-18 13:42:32 +01:00
|
|
|
svga->render = svga_render_8bpp_lowres;
|
|
|
|
|
else
|
|
|
|
|
svga->render = svga_render_8bpp_highres;
|
2023-11-23 09:58:00 +13:00
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
switch (svga->gdcreg[5] & 0x60) {
|
|
|
|
|
case 0x40:
|
|
|
|
|
case 0x60: /*256+ colours*/
|
|
|
|
|
switch (svga->bpp) {
|
|
|
|
|
case 15:
|
|
|
|
|
if (svga->lowres)
|
|
|
|
|
svga->render = svga_render_15bpp_lowres;
|
|
|
|
|
else
|
|
|
|
|
svga->render = svga_render_15bpp_highres;
|
|
|
|
|
break;
|
|
|
|
|
case 16:
|
|
|
|
|
if (svga->lowres)
|
|
|
|
|
svga->render = svga_render_16bpp_lowres;
|
|
|
|
|
else
|
|
|
|
|
svga->render = svga_render_16bpp_highres;
|
|
|
|
|
break;
|
|
|
|
|
case 17:
|
|
|
|
|
if (svga->lowres)
|
|
|
|
|
svga->render = svga_render_15bpp_mix_lowres;
|
|
|
|
|
else
|
|
|
|
|
svga->render = svga_render_15bpp_mix_highres;
|
|
|
|
|
break;
|
|
|
|
|
case 24:
|
|
|
|
|
if (svga->lowres)
|
|
|
|
|
svga->render = svga_render_24bpp_lowres;
|
|
|
|
|
else
|
|
|
|
|
svga->render = svga_render_24bpp_highres;
|
|
|
|
|
break;
|
|
|
|
|
case 32:
|
|
|
|
|
if (svga->lowres)
|
|
|
|
|
svga->render = svga_render_32bpp_lowres;
|
|
|
|
|
else
|
|
|
|
|
svga->render = svga_render_32bpp_highres;
|
|
|
|
|
break;
|
2023-07-30 19:22:43 -04:00
|
|
|
|
2023-11-23 09:58:00 +13:00
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
}
|
2022-08-31 19:19:29 -04:00
|
|
|
}
|
|
|
|
|
}
|
2018-04-25 23:51:13 +02:00
|
|
|
}
|
|
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->linedbl = svga->crtc[9] & 0x80;
|
|
|
|
|
svga->char_width = (svga->seqregs[1] & 1) ? 8 : 9;
|
2020-01-18 21:35:26 +01:00
|
|
|
|
2024-01-09 17:38:54 +01:00
|
|
|
svga->monitor->mon_overscan_y = (svga->rowcount + 1) << 1;
|
2019-10-20 15:09:38 +02:00
|
|
|
|
2024-01-09 17:38:54 +01:00
|
|
|
if (svga->monitor->mon_overscan_y < 16)
|
|
|
|
|
svga->monitor->mon_overscan_y = 16;
|
2019-10-20 15:09:38 +02:00
|
|
|
|
2019-11-19 19:18:44 +01:00
|
|
|
if (!(svga->gdcreg[6] & 1) && !(svga->attrregs[0x10] & 1)) {
|
2023-01-22 16:50:21 +06:00
|
|
|
svga->monitor->mon_overscan_x = (svga->seqregs[1] & 1) ? 16 : 18;
|
2019-10-20 15:09:38 +02:00
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
if (svga->seqregs[1] & 8)
|
2023-01-22 16:50:21 +06:00
|
|
|
svga->monitor->mon_overscan_x <<= 1;
|
2019-11-19 19:18:44 +01:00
|
|
|
} else
|
2023-01-22 16:50:21 +06:00
|
|
|
svga->monitor->mon_overscan_x = 16;
|
2019-10-20 15:09:38 +02:00
|
|
|
|
2024-02-18 17:54:14 +01:00
|
|
|
svga->hblankstart = svga->crtc[2];
|
2023-08-06 20:29:39 -04:00
|
|
|
svga->hblank_end_val = (svga->crtc[3] & 0x1f) | ((svga->crtc[5] & 0x80) ? 0x20 : 0x00);
|
2024-02-07 00:11:02 +01:00
|
|
|
svga->hblank_end_mask = 0x0000003f;
|
2024-01-11 01:56:32 +01:00
|
|
|
|
|
|
|
|
svga_log("htotal = %i, hblankstart = %i, hblank_end_val = %02X\n",
|
|
|
|
|
svga->htotal, svga->hblankstart, svga->hblank_end_val);
|
|
|
|
|
|
2023-08-06 20:29:39 -04:00
|
|
|
if (!svga->scrblank && svga->attr_palette_enable) {
|
2024-01-11 01:56:32 +01:00
|
|
|
/* TODO: In case of bug reports, disable 9-dots-wide character clocks in graphics modes. */
|
2024-02-07 00:11:02 +01:00
|
|
|
if (!(svga->gdcreg[6] & 1) && !(svga->attrregs[0x10] & 1)) {
|
|
|
|
|
if (svga->seqregs[1] & 8)
|
|
|
|
|
svga->dots_per_clock = ((svga->seqregs[1] & 1) ? 16 : 18);
|
|
|
|
|
else
|
|
|
|
|
svga->dots_per_clock = ((svga->seqregs[1] & 1) ? 8 : 9);
|
|
|
|
|
} else {
|
|
|
|
|
if (svga->seqregs[1] & 8)
|
|
|
|
|
svga->dots_per_clock = 16;
|
|
|
|
|
else
|
|
|
|
|
svga->dots_per_clock = 8;
|
|
|
|
|
}
|
2023-08-06 20:29:39 -04:00
|
|
|
} else
|
|
|
|
|
svga->dots_per_clock = 1;
|
|
|
|
|
|
2024-02-09 18:02:33 +01:00
|
|
|
svga->multiplier = 1.0;
|
|
|
|
|
|
2024-01-10 08:59:46 +01:00
|
|
|
if (svga->recalctimings_ex)
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
svga->recalctimings_ex(svga);
|
|
|
|
|
|
2023-10-10 00:49:44 +02:00
|
|
|
if (ibm8514_active && (svga->dev8514 != NULL)) {
|
2023-12-06 15:00:31 +01:00
|
|
|
if ((dev->local & 0xff) == 0x00)
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
ibm8514_recalctimings(svga);
|
2022-05-14 19:26:41 +02:00
|
|
|
}
|
2018-04-25 23:51:13 +02:00
|
|
|
|
2023-10-10 00:49:44 +02:00
|
|
|
if (xga_active && (svga->xga != NULL))
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
xga_recalctimings(svga);
|
|
|
|
|
|
2024-01-11 01:56:32 +01:00
|
|
|
if (!svga->hoverride) {
|
2024-02-07 00:11:02 +01:00
|
|
|
uint32_t dot = svga->hblankstart;
|
|
|
|
|
uint32_t adj_dot = svga->hblankstart;
|
|
|
|
|
/* Verified with both the Voodoo 3 and the S3 cards: compare 7 bits if bit 7 is set,
|
|
|
|
|
otherwise compare 6 bits. */
|
|
|
|
|
uint32_t eff_mask = (svga->hblank_end_val & ~0x0000003f) ? svga->hblank_end_mask : 0x0000003f;
|
2024-01-11 01:56:32 +01:00
|
|
|
svga->hblank_sub = 0;
|
2024-01-10 22:41:13 +01:00
|
|
|
|
2024-02-20 18:41:51 +01:00
|
|
|
svga_log("HDISP=%d, CRTC1+1=%d, Blank: %04i-%04i, Total: %04i, Mask: %02X, ADJ_DOT=%04i.\n", svga->hdisp, svga->crtc[1] + 1, svga->hblankstart, svga->hblank_end_val,
|
|
|
|
|
svga->htotal, eff_mask, adj_dot);
|
2024-02-07 00:11:02 +01:00
|
|
|
|
2024-02-18 11:54:11 +01:00
|
|
|
while (adj_dot < (svga->htotal << 1)) {
|
2024-02-07 00:11:02 +01:00
|
|
|
if (dot == svga->htotal)
|
|
|
|
|
dot = 0;
|
|
|
|
|
|
|
|
|
|
if (adj_dot >= svga->htotal)
|
|
|
|
|
svga->hblank_sub++;
|
|
|
|
|
|
2024-02-20 18:41:51 +01:00
|
|
|
svga_log("Loop: adjdot=%d, htotal=%d, dotmask=%02x, hblankendvalmask=%02x, blankendval=%02x.\n", adj_dot, svga->htotal, dot & eff_mask, svga->hblank_end_val & eff_mask, svga->hblank_end_val);
|
2024-02-07 00:11:02 +01:00
|
|
|
if ((dot & eff_mask) == (svga->hblank_end_val & eff_mask))
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
dot++;
|
|
|
|
|
adj_dot++;
|
2024-01-11 01:56:32 +01:00
|
|
|
}
|
2024-02-07 00:11:02 +01:00
|
|
|
|
|
|
|
|
svga->hdisp -= (svga->hblank_sub * svga->dots_per_clock);
|
2024-02-20 18:41:51 +01:00
|
|
|
}
|
2024-02-07 01:53:16 +01:00
|
|
|
|
2024-02-20 18:41:51 +01:00
|
|
|
#ifdef TBD
|
|
|
|
|
if (ibm8514_active && (svga->dev8514 != NULL)) {
|
2024-10-26 21:32:47 +02:00
|
|
|
if (dev->on) {
|
2024-02-20 18:41:51 +01:00
|
|
|
uint32_t dot8514 = dev->h_blankstart;
|
|
|
|
|
uint32_t adj_dot8514 = dev->h_blankstart;
|
|
|
|
|
uint32_t eff_mask8514 = 0x0000003f;
|
|
|
|
|
dev->hblank_sub = 0;
|
2024-02-07 01:53:16 +01:00
|
|
|
|
2024-02-20 18:41:51 +01:00
|
|
|
while (adj_dot8514 < (dev->h_total << 1)) {
|
|
|
|
|
if (dot8514 == dev->h_total)
|
|
|
|
|
dot8514 = 0;
|
2024-02-07 01:53:16 +01:00
|
|
|
|
2024-02-20 18:41:51 +01:00
|
|
|
if (adj_dot8514 >= dev->h_total)
|
|
|
|
|
dev->hblank_sub++;
|
2024-02-07 01:53:16 +01:00
|
|
|
|
2024-02-20 18:41:51 +01:00
|
|
|
if ((dot8514 & eff_mask8514) == (dev->h_blank_end_val & eff_mask8514))
|
|
|
|
|
break;
|
2024-02-07 01:53:16 +01:00
|
|
|
|
2024-02-20 18:41:51 +01:00
|
|
|
dot8514++;
|
|
|
|
|
adj_dot8514++;
|
2024-02-07 01:53:16 +01:00
|
|
|
}
|
2024-02-20 18:41:51 +01:00
|
|
|
|
|
|
|
|
dev->h_disp -= dev->hblank_sub;
|
2024-02-07 01:53:16 +01:00
|
|
|
}
|
2023-08-06 20:29:39 -04:00
|
|
|
}
|
2024-02-20 18:41:51 +01:00
|
|
|
#endif
|
2023-08-06 20:29:39 -04:00
|
|
|
|
2023-07-30 23:37:21 +02:00
|
|
|
if (svga->hdisp >= 2048)
|
|
|
|
|
svga->monitor->mon_overscan_x = 0;
|
|
|
|
|
|
2024-01-07 09:04:25 +13:00
|
|
|
svga->y_add = (svga->monitor->mon_overscan_y >> 1);
|
2023-01-22 16:50:21 +06:00
|
|
|
svga->x_add = (svga->monitor->mon_overscan_x >> 1);
|
2019-10-20 15:09:38 +02:00
|
|
|
|
2024-08-12 19:52:52 +02:00
|
|
|
if (svga->vblankstart < svga->dispend) {
|
|
|
|
|
svga_log("DISPEND > VBLANKSTART.\n");
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->dispend = svga->vblankstart;
|
2024-08-12 19:52:52 +02:00
|
|
|
}
|
2018-04-25 23:51:13 +02:00
|
|
|
|
2020-01-18 21:35:26 +01:00
|
|
|
crtcconst = svga->clock * svga->char_width;
|
2024-02-07 01:53:16 +01:00
|
|
|
if (ibm8514_active && (svga->dev8514 != NULL)) {
|
2024-10-26 21:32:47 +02:00
|
|
|
if (dev->on)
|
2024-02-07 01:53:16 +01:00
|
|
|
crtcconst8514 = svga->clock8514;
|
|
|
|
|
}
|
2018-04-25 23:51:13 +02:00
|
|
|
|
2023-08-06 20:29:39 -04:00
|
|
|
#ifdef ENABLE_SVGA_LOG
|
|
|
|
|
vsyncend = (svga->vsyncstart & 0xfffffff0) | (svga->crtc[0x11] & 0x0f);
|
|
|
|
|
if (vsyncend <= svga->vsyncstart)
|
|
|
|
|
vsyncend += 0x00000010;
|
|
|
|
|
vblankend = (svga->vblankstart & 0xffffff80) | (svga->crtc[0x16] & 0x7f);
|
|
|
|
|
if (vblankend <= svga->vblankstart)
|
|
|
|
|
vblankend += 0x00000080;
|
|
|
|
|
|
|
|
|
|
hdispstart = ((svga->crtc[3] >> 5) & 3);
|
|
|
|
|
hdispend = svga->crtc[1] + 1;
|
|
|
|
|
hsyncstart = svga->crtc[4] + ((svga->crtc[5] >> 5) & 3) + 1;
|
|
|
|
|
hsyncend = (hsyncstart & 0xffffffe0) | (svga->crtc[5] & 0x1f);
|
|
|
|
|
if (hsyncend <= hsyncstart)
|
|
|
|
|
hsyncend += 0x00000020;
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
svga_log("Last scanline in the vertical period: %i\n"
|
|
|
|
|
"First scanline after the last of active display: %i\n"
|
|
|
|
|
"First scanline with vertical retrace asserted: %i\n"
|
|
|
|
|
"First scanline after the last with vertical retrace asserted: %i\n"
|
|
|
|
|
"First scanline of blanking: %i\n"
|
|
|
|
|
"First scanline after the last of blanking: %i\n"
|
|
|
|
|
"\n"
|
|
|
|
|
"Last character in the horizontal period: %i\n"
|
|
|
|
|
"First character of active display: %i\n"
|
|
|
|
|
"First character after the last of active display: %i\n"
|
|
|
|
|
"First character with horizontal retrace asserted: %i\n"
|
|
|
|
|
"First character after the last with horizontal retrace asserted: %i\n"
|
|
|
|
|
"First character of blanking: %i\n"
|
|
|
|
|
"First character after the last of blanking: %i\n"
|
|
|
|
|
"\n"
|
|
|
|
|
"\n",
|
|
|
|
|
svga->vtotal, svga->dispend, svga->vsyncstart, vsyncend,
|
|
|
|
|
svga->vblankstart, vblankend,
|
|
|
|
|
svga->htotal, hdispstart, hdispend, hsyncstart, hsyncend,
|
|
|
|
|
svga->hblankstart, svga->hblankend);
|
|
|
|
|
|
2024-02-09 18:02:33 +01:00
|
|
|
disptime = svga->htotal * svga->multiplier;
|
2023-08-15 00:11:56 +02:00
|
|
|
_dispontime = svga->hdisp_time;
|
2018-04-25 23:51:13 +02:00
|
|
|
|
2024-02-07 01:53:16 +01:00
|
|
|
if (ibm8514_active && (svga->dev8514 != NULL)) {
|
2024-10-26 21:32:47 +02:00
|
|
|
if (dev->on) {
|
2024-02-22 13:35:04 +01:00
|
|
|
disptime8514 = dev->h_total ? dev->h_total : TIMER_USEC;
|
2024-02-07 01:53:16 +01:00
|
|
|
_dispontime8514 = dev->hdisped;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
if (svga->seqregs[1] & 8) {
|
2022-08-31 19:19:29 -04:00
|
|
|
disptime *= 2;
|
|
|
|
|
_dispontime *= 2;
|
2018-04-25 23:51:13 +02:00
|
|
|
}
|
2019-11-19 19:18:44 +01:00
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
_dispofftime = disptime - _dispontime;
|
|
|
|
|
_dispontime *= crtcconst;
|
|
|
|
|
_dispofftime *= crtcconst;
|
|
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->dispontime = (uint64_t) (_dispontime);
|
|
|
|
|
svga->dispofftime = (uint64_t) (_dispofftime);
|
Added the IBM 5161 ISA expansion for PC and XT;
Cleaned up the parallel port emulation, added IRQ support, and made enabling/disabling per port;
Added the Award 430NX and the Intel Classic/PCI (Alfredo, 420TX);
Finished the 586MC1;
Added 8087 emulation;
Moved Cyrix 6x86'es to the Dev branch;
Sanitized/cleaned up memregs.c/h and intel.c/h;
Split the chipsets from machines and sanitized Port 92 emulation;
Added support for the 15bpp mode to the Compaq ATI 28800;
Moved the MR 386DX and 486 machines to the Dev branch;
Ported the new dynamic recompiler from PCem, but it remains in Dev branch until after v2.00;
Ported the new timer code from PCem;
Cleaned up the CPU table of unused stuff and better optimized its structure;
Ported the Open-XT and Open-AT from VARCem, the Open-AT is in the Dev branch;
Ported the XT MFM controller rewrite and adding of more controllers (incl. two RLL ones), from VARCem;
Added the AHA-1540A and the BusTek BT-542B;
Moved the Sumo SCSI-AT to the Dev branch;
Minor IDE, FDC, and floppy drive code clean-ups;
Made NCR 5380/53C400-based cards' BIOS address configurable;
Got rid of the legacy romset variable;
Unified (video) buffer and buffer32 into one and make the unified buffer 32-bit;
Added the Amstead PPC512 per PCem patch by John Elliott;
Switched memory mapping granularity from 16k to 4k (less than 1k not possible due to internal pages);
Rewrote the CL-GD 54xx blitter, fixes Win-OS/2 on the 54x6 among other thing;
Added the Image Manager 1024 and Professional Graphics Controller per PCem patch by John Elliott and work done on VARCem;
Added Headland HT-216, GC-205 and Video 7 VGA 1024i emulation based on PCem commit;
Implemented the fuction keys for the Toshiba T1000/T1200/T3100 enhancement;
Amstrad MegaPC does now works correctly with non-internal graphics card;
The SLiRP code no longer casts a packed struct type to a non-packed struct type;
The Xi8088 and PB410a no longer hang on 86Box when PS/2 mouse is not present;
The S3 Virge on BeOS is no longer broken (was broken by build #1591);
OS/2 2.0 build 6.167 now sees key presses again;
Xi8088 now work on CGA again;
86F images converted from either the old or new variants of the HxC MFM format now work correctly;
Hardware interrupts with a vector of 0xFF are now handled correctly;
OPTi 495SX boards no longer incorrectly have 64 MB maximum RAM when 32 MB is correct;
Fixed VNC keyboard input bugs;
Fixed AT RTC periodic interrupt - Chicago 58s / 73f / 73g / 81 MIDI play no longer hangs with the build's own VTD driver;
Fixed mouse polling with internal mice - Amstrad and Olivetti mice now work correctly;
Triones ATAPI DMA driver now correctly reads a file at the end of a CD image with a sectors number not divisible by 4;
Compaq Portable now works with all graphics cards;
Fixed various MDSI Genius bugs;
Added segment limit checks and improved page fault checks for several CPU instructions - Memphis 15xx WINSETUP and Chicago 58s WINDISK.CPL no longer issue a GPF, and some S3 drivers that used to have glitches, now work correctly;
Further improved the 808x emulation, also fixes the noticably choppy sound when using 808x CPU's, also fixes #355;
OS/2 installer no logner locks up on splash screen on PS/2 Model 70 and 80, fixes #400.
Fixed several Amstead bugs, GEM no longer crashes on the Amstrad 1640, fixes #391.
Ported John Elliott's Amstrad fixes and improvement from PCem, and fixed the default language so it's correctly Engliish, fixes #278, fixes #389.
Fixed a minor IDE timing bug, fixes #388.
Fixed Toshiba T1000 RAM issues, fixes #379.
Fixed EGA/(S)VGA overscan border handling, fixes #378;
Got rid of the now long useless IDE channel 2 auto-removal, fixes #370;
Fixed the BIOS files used by the AMSTRAD PC1512, fixes #366;
Ported the Unicode CD image file name fix from VARCem, fixes #365;
Fixed high density floppy disks on the Xi8088, fixes #359;
Fixed some bugs in the Hercules emulation, fixes #346, fixes #358;
Fixed the SCSI hard disk mode sense pages, fixes #356;
Removed the AMI Unknown 386SX because of impossibility to identify the chipset, closes #349;
Fixed bugs in the serial mouse emulation, fixes #344;
Compiled 86Box binaries now include all the required .DLL's, fixes #341;
Made some combo boxes in the Settings dialog slightly wider, fixes #276.
2019-09-20 14:02:30 +02:00
|
|
|
if (svga->dispontime < TIMER_USEC)
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->dispontime = TIMER_USEC;
|
Added the IBM 5161 ISA expansion for PC and XT;
Cleaned up the parallel port emulation, added IRQ support, and made enabling/disabling per port;
Added the Award 430NX and the Intel Classic/PCI (Alfredo, 420TX);
Finished the 586MC1;
Added 8087 emulation;
Moved Cyrix 6x86'es to the Dev branch;
Sanitized/cleaned up memregs.c/h and intel.c/h;
Split the chipsets from machines and sanitized Port 92 emulation;
Added support for the 15bpp mode to the Compaq ATI 28800;
Moved the MR 386DX and 486 machines to the Dev branch;
Ported the new dynamic recompiler from PCem, but it remains in Dev branch until after v2.00;
Ported the new timer code from PCem;
Cleaned up the CPU table of unused stuff and better optimized its structure;
Ported the Open-XT and Open-AT from VARCem, the Open-AT is in the Dev branch;
Ported the XT MFM controller rewrite and adding of more controllers (incl. two RLL ones), from VARCem;
Added the AHA-1540A and the BusTek BT-542B;
Moved the Sumo SCSI-AT to the Dev branch;
Minor IDE, FDC, and floppy drive code clean-ups;
Made NCR 5380/53C400-based cards' BIOS address configurable;
Got rid of the legacy romset variable;
Unified (video) buffer and buffer32 into one and make the unified buffer 32-bit;
Added the Amstead PPC512 per PCem patch by John Elliott;
Switched memory mapping granularity from 16k to 4k (less than 1k not possible due to internal pages);
Rewrote the CL-GD 54xx blitter, fixes Win-OS/2 on the 54x6 among other thing;
Added the Image Manager 1024 and Professional Graphics Controller per PCem patch by John Elliott and work done on VARCem;
Added Headland HT-216, GC-205 and Video 7 VGA 1024i emulation based on PCem commit;
Implemented the fuction keys for the Toshiba T1000/T1200/T3100 enhancement;
Amstrad MegaPC does now works correctly with non-internal graphics card;
The SLiRP code no longer casts a packed struct type to a non-packed struct type;
The Xi8088 and PB410a no longer hang on 86Box when PS/2 mouse is not present;
The S3 Virge on BeOS is no longer broken (was broken by build #1591);
OS/2 2.0 build 6.167 now sees key presses again;
Xi8088 now work on CGA again;
86F images converted from either the old or new variants of the HxC MFM format now work correctly;
Hardware interrupts with a vector of 0xFF are now handled correctly;
OPTi 495SX boards no longer incorrectly have 64 MB maximum RAM when 32 MB is correct;
Fixed VNC keyboard input bugs;
Fixed AT RTC periodic interrupt - Chicago 58s / 73f / 73g / 81 MIDI play no longer hangs with the build's own VTD driver;
Fixed mouse polling with internal mice - Amstrad and Olivetti mice now work correctly;
Triones ATAPI DMA driver now correctly reads a file at the end of a CD image with a sectors number not divisible by 4;
Compaq Portable now works with all graphics cards;
Fixed various MDSI Genius bugs;
Added segment limit checks and improved page fault checks for several CPU instructions - Memphis 15xx WINSETUP and Chicago 58s WINDISK.CPL no longer issue a GPF, and some S3 drivers that used to have glitches, now work correctly;
Further improved the 808x emulation, also fixes the noticably choppy sound when using 808x CPU's, also fixes #355;
OS/2 installer no logner locks up on splash screen on PS/2 Model 70 and 80, fixes #400.
Fixed several Amstead bugs, GEM no longer crashes on the Amstrad 1640, fixes #391.
Ported John Elliott's Amstrad fixes and improvement from PCem, and fixed the default language so it's correctly Engliish, fixes #278, fixes #389.
Fixed a minor IDE timing bug, fixes #388.
Fixed Toshiba T1000 RAM issues, fixes #379.
Fixed EGA/(S)VGA overscan border handling, fixes #378;
Got rid of the now long useless IDE channel 2 auto-removal, fixes #370;
Fixed the BIOS files used by the AMSTRAD PC1512, fixes #366;
Ported the Unicode CD image file name fix from VARCem, fixes #365;
Fixed high density floppy disks on the Xi8088, fixes #359;
Fixed some bugs in the Hercules emulation, fixes #346, fixes #358;
Fixed the SCSI hard disk mode sense pages, fixes #356;
Removed the AMI Unknown 386SX because of impossibility to identify the chipset, closes #349;
Fixed bugs in the serial mouse emulation, fixes #344;
Compiled 86Box binaries now include all the required .DLL's, fixes #341;
Made some combo boxes in the Settings dialog slightly wider, fixes #276.
2019-09-20 14:02:30 +02:00
|
|
|
if (svga->dispofftime < TIMER_USEC)
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->dispofftime = TIMER_USEC;
|
2021-05-30 01:52:43 +02:00
|
|
|
|
2024-02-07 01:53:16 +01:00
|
|
|
if (ibm8514_active && (svga->dev8514 != NULL)) {
|
2024-10-26 21:32:47 +02:00
|
|
|
if (dev->on) {
|
2024-02-07 01:53:16 +01:00
|
|
|
_dispofftime8514 = disptime8514 - _dispontime8514;
|
|
|
|
|
_dispontime8514 *= crtcconst8514;
|
|
|
|
|
_dispofftime8514 *= crtcconst8514;
|
|
|
|
|
|
|
|
|
|
dev->dispontime = (uint64_t) (_dispontime8514);
|
|
|
|
|
dev->dispofftime = (uint64_t) (_dispofftime8514);
|
|
|
|
|
if (dev->dispontime < TIMER_USEC)
|
|
|
|
|
dev->dispontime = TIMER_USEC;
|
|
|
|
|
if (dev->dispofftime < TIMER_USEC)
|
|
|
|
|
dev->dispofftime = TIMER_USEC;
|
|
|
|
|
|
2024-05-29 20:47:22 +02:00
|
|
|
svga_log("IBM 8514/A poll.\n");
|
|
|
|
|
timer_set_callback(&svga->timer, ibm8514_poll);
|
2024-02-07 01:53:16 +01:00
|
|
|
} else {
|
2024-05-29 20:47:22 +02:00
|
|
|
svga_log("SVGA Poll.\n");
|
|
|
|
|
timer_set_callback(&svga->timer, svga_poll);
|
2024-02-07 01:53:16 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
if (!svga->force_old_addr)
|
|
|
|
|
svga_recalc_remap_func(svga);
|
2021-04-13 14:07:21 -03:00
|
|
|
|
|
|
|
|
/* Inform the user interface of any DPMS mode changes. */
|
|
|
|
|
if (svga->dpms) {
|
2022-08-31 19:19:29 -04:00
|
|
|
if (!svga->dpms_ui) {
|
2024-02-21 02:25:40 +06:00
|
|
|
/* Make sure to black out the entire screen to avoid lingering image. */
|
|
|
|
|
int y_add = enable_overscan ? svga->monitor->mon_overscan_y : 0;
|
|
|
|
|
int x_add = enable_overscan ? svga->monitor->mon_overscan_x : 0;
|
|
|
|
|
int y_start = enable_overscan ? 0 : (svga->monitor->mon_overscan_y >> 1);
|
|
|
|
|
int x_start = enable_overscan ? 0 : (svga->monitor->mon_overscan_x >> 1);
|
|
|
|
|
video_wait_for_buffer_monitor(svga->monitor_index);
|
|
|
|
|
memset(svga->monitor->target_buffer->dat, 0, svga->monitor->target_buffer->w * svga->monitor->target_buffer->h * 4);
|
|
|
|
|
video_blit_memtoscreen_monitor(x_start, y_start, svga->monitor->mon_xsize + x_add, svga->monitor->mon_ysize + y_add, svga->monitor_index);
|
|
|
|
|
video_wait_for_buffer_monitor(svga->monitor_index);
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->dpms_ui = 1;
|
2024-03-19 14:27:19 +05:00
|
|
|
ui_sb_set_text_w(plat_get_string(STRING_MONITOR_SLEEP));
|
2022-08-31 19:19:29 -04:00
|
|
|
}
|
2021-04-13 14:07:21 -03:00
|
|
|
} else if (svga->dpms_ui) {
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->dpms_ui = 0;
|
|
|
|
|
ui_sb_set_text_w(NULL);
|
2021-04-13 14:07:21 -03:00
|
|
|
}
|
2018-04-25 23:51:13 +02:00
|
|
|
}
|
|
|
|
|
|
2020-01-20 05:36:44 +01:00
|
|
|
static void
|
|
|
|
|
svga_do_render(svga_t *svga)
|
|
|
|
|
{
|
2021-04-13 14:07:21 -03:00
|
|
|
/* Always render a blank screen and nothing else while in DPMS mode. */
|
|
|
|
|
if (svga->dpms) {
|
2022-08-31 19:19:29 -04:00
|
|
|
svga_render_blank(svga);
|
|
|
|
|
return;
|
2021-04-13 14:07:21 -03:00
|
|
|
}
|
|
|
|
|
|
2020-01-20 05:36:44 +01:00
|
|
|
if (!svga->override) {
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->render(svga);
|
2020-01-20 05:36:44 +01:00
|
|
|
|
2023-01-22 16:50:21 +06:00
|
|
|
svga->x_add = (svga->monitor->mon_overscan_x >> 1);
|
2022-08-31 19:19:29 -04:00
|
|
|
svga_render_overscan_left(svga);
|
|
|
|
|
svga_render_overscan_right(svga);
|
2023-01-22 16:50:21 +06:00
|
|
|
svga->x_add = (svga->monitor->mon_overscan_x >> 1) - svga->scrollcache;
|
2020-01-20 05:36:44 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (svga->overlay_on) {
|
2022-08-31 19:19:29 -04:00
|
|
|
if (!svga->override && svga->overlay_draw)
|
|
|
|
|
svga->overlay_draw(svga, svga->displine + svga->y_add);
|
|
|
|
|
svga->overlay_on--;
|
|
|
|
|
if (svga->overlay_on && svga->interlace)
|
|
|
|
|
svga->overlay_on--;
|
2020-01-20 05:36:44 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (svga->dac_hwcursor_on) {
|
2022-08-31 19:19:29 -04:00
|
|
|
if (!svga->override && svga->dac_hwcursor_draw)
|
2024-02-15 00:31:51 +06:00
|
|
|
svga->dac_hwcursor_draw(svga, (svga->displine + svga->y_add + ((svga->dac_hwcursor_latch.y >= 0) ? 0 : svga->dac_hwcursor_latch.y)) & 2047);
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->dac_hwcursor_on--;
|
|
|
|
|
if (svga->dac_hwcursor_on && svga->interlace)
|
|
|
|
|
svga->dac_hwcursor_on--;
|
2020-01-20 05:36:44 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (svga->hwcursor_on) {
|
2022-08-31 19:19:29 -04:00
|
|
|
if (!svga->override && svga->hwcursor_draw)
|
2024-02-15 00:31:51 +06:00
|
|
|
svga->hwcursor_draw(svga, (svga->displine + svga->y_add + ((svga->hwcursor_latch.y >= 0) ? 0 : svga->hwcursor_latch.y)) & 2047);
|
2024-11-02 20:50:06 +01:00
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->hwcursor_on--;
|
|
|
|
|
if (svga->hwcursor_on && svga->interlace)
|
|
|
|
|
svga->hwcursor_on--;
|
2020-01-20 05:36:44 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
void
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_poll(void *priv)
|
2018-04-25 23:51:13 +02:00
|
|
|
{
|
2023-07-30 19:22:43 -04:00
|
|
|
svga_t *svga = (svga_t *) priv;
|
2023-10-09 20:14:03 +02:00
|
|
|
xga_t *xga = (xga_t *) svga->xga;
|
2023-07-30 19:22:43 -04:00
|
|
|
uint32_t x;
|
|
|
|
|
uint32_t blink_delay;
|
|
|
|
|
int wx;
|
|
|
|
|
int wy;
|
|
|
|
|
int ret;
|
|
|
|
|
int old_ma;
|
2018-04-25 23:51:13 +02:00
|
|
|
|
2023-10-11 18:46:15 +02:00
|
|
|
if (!svga->override) {
|
2023-11-08 23:47:16 +01:00
|
|
|
if (xga_active && xga && xga->on) {
|
2023-10-11 18:46:15 +02:00
|
|
|
if ((xga->disp_cntl_2 & 7) >= 2) {
|
2024-10-03 14:56:23 +02:00
|
|
|
xga_poll(svga);
|
2023-10-11 18:46:15 +02:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
}
|
2022-05-14 19:26:41 +02:00
|
|
|
}
|
|
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
if (!svga->linepos) {
|
2024-02-15 00:31:51 +06:00
|
|
|
if (svga->displine == ((svga->hwcursor_latch.y < 0) ? 0 : svga->hwcursor_latch.y) && svga->hwcursor_latch.ena) {
|
2023-07-14 23:38:04 +02:00
|
|
|
svga->hwcursor_on = svga->hwcursor_latch.cur_ysize - svga->hwcursor_latch.yoff;
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->hwcursor_oddeven = 0;
|
|
|
|
|
}
|
|
|
|
|
|
2024-02-15 00:31:51 +06:00
|
|
|
if (svga->displine == (((svga->hwcursor_latch.y < 0) ? 0 : svga->hwcursor_latch.y) + 1) && svga->hwcursor_latch.ena && svga->interlace) {
|
2023-07-14 23:38:04 +02:00
|
|
|
svga->hwcursor_on = svga->hwcursor_latch.cur_ysize - (svga->hwcursor_latch.yoff + 1);
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->hwcursor_oddeven = 1;
|
|
|
|
|
}
|
|
|
|
|
|
2024-02-15 00:31:51 +06:00
|
|
|
if (svga->displine == ((svga->dac_hwcursor_latch.y < 0) ? 0 : svga->dac_hwcursor_latch.y) && svga->dac_hwcursor_latch.ena) {
|
2023-07-14 23:38:04 +02:00
|
|
|
svga->dac_hwcursor_on = svga->dac_hwcursor_latch.cur_ysize - svga->dac_hwcursor_latch.yoff;
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->dac_hwcursor_oddeven = 0;
|
|
|
|
|
}
|
|
|
|
|
|
2024-02-15 00:31:51 +06:00
|
|
|
if (svga->displine == (((svga->dac_hwcursor_latch.y < 0) ? 0 : svga->dac_hwcursor_latch.y) + 1) && svga->dac_hwcursor_latch.ena && svga->interlace) {
|
2023-07-14 23:38:04 +02:00
|
|
|
svga->dac_hwcursor_on = svga->dac_hwcursor_latch.cur_ysize - (svga->dac_hwcursor_latch.yoff + 1);
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->dac_hwcursor_oddeven = 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (svga->displine == svga->overlay_latch.y && svga->overlay_latch.ena) {
|
|
|
|
|
svga->overlay_on = svga->overlay_latch.cur_ysize - svga->overlay_latch.yoff;
|
|
|
|
|
svga->overlay_oddeven = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (svga->displine == svga->overlay_latch.y + 1 && svga->overlay_latch.ena && svga->interlace) {
|
|
|
|
|
svga->overlay_on = svga->overlay_latch.cur_ysize - svga->overlay_latch.yoff;
|
|
|
|
|
svga->overlay_oddeven = 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
timer_advance_u64(&svga->timer, svga->dispofftime);
|
|
|
|
|
svga->cgastat |= 1;
|
|
|
|
|
svga->linepos = 1;
|
|
|
|
|
|
|
|
|
|
if (svga->dispon) {
|
|
|
|
|
svga->hdisp_on = 1;
|
|
|
|
|
|
|
|
|
|
svga->ma &= svga->vram_display_mask;
|
|
|
|
|
if (svga->firstline == 2000) {
|
|
|
|
|
svga->firstline = svga->displine;
|
2023-01-22 16:50:21 +06:00
|
|
|
video_wait_for_buffer_monitor(svga->monitor_index);
|
2022-08-31 19:19:29 -04:00
|
|
|
}
|
|
|
|
|
|
2024-11-02 20:50:06 +01:00
|
|
|
if (svga->hwcursor_on || svga->dac_hwcursor_on || svga->overlay_on)
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->changedvram[svga->ma >> 12] = svga->changedvram[(svga->ma >> 12) + 1] = svga->interlace ? 3 : 2;
|
|
|
|
|
|
|
|
|
|
if (svga->vertical_linedbl) {
|
|
|
|
|
old_ma = svga->ma;
|
|
|
|
|
|
|
|
|
|
svga->displine <<= 1;
|
|
|
|
|
svga->y_add <<= 1;
|
|
|
|
|
|
|
|
|
|
svga_do_render(svga);
|
|
|
|
|
|
|
|
|
|
svga->displine++;
|
|
|
|
|
|
|
|
|
|
svga->ma = old_ma;
|
|
|
|
|
|
|
|
|
|
svga_do_render(svga);
|
|
|
|
|
|
|
|
|
|
svga->y_add >>= 1;
|
|
|
|
|
svga->displine >>= 1;
|
|
|
|
|
} else
|
|
|
|
|
svga_do_render(svga);
|
|
|
|
|
|
|
|
|
|
if (svga->lastline < svga->displine)
|
|
|
|
|
svga->lastline = svga->displine;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
svga->displine++;
|
|
|
|
|
if (svga->interlace)
|
|
|
|
|
svga->displine++;
|
|
|
|
|
if ((svga->cgastat & 8) && ((svga->displine & 15) == (svga->crtc[0x11] & 15)) && svga->vslines)
|
|
|
|
|
svga->cgastat &= ~8;
|
|
|
|
|
svga->vslines++;
|
2023-07-30 23:37:21 +02:00
|
|
|
if (svga->displine > 2000)
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->displine = 0;
|
2018-04-25 23:51:13 +02:00
|
|
|
} else {
|
2022-08-31 19:19:29 -04:00
|
|
|
timer_advance_u64(&svga->timer, svga->dispontime);
|
|
|
|
|
|
|
|
|
|
if (svga->dispon)
|
|
|
|
|
svga->cgastat &= ~1;
|
|
|
|
|
svga->hdisp_on = 0;
|
|
|
|
|
|
|
|
|
|
svga->linepos = 0;
|
|
|
|
|
if ((svga->sc == (svga->crtc[11] & 31)) || (svga->sc == svga->rowcount))
|
|
|
|
|
svga->con = 0;
|
|
|
|
|
if (svga->dispon) {
|
2024-01-07 09:04:25 +13:00
|
|
|
/* TODO: Verify real hardware behaviour for out-of-range fine vertical scroll
|
|
|
|
|
- S3 Trio64V2/DX: sc == rowcount, wrapping 5-bit counter. */
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (svga->linedbl && !svga->linecountff) {
|
2023-07-30 19:22:43 -04:00
|
|
|
svga->linecountff = 1;
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->ma = svga->maback;
|
|
|
|
|
} else if (svga->sc == svga->rowcount) {
|
|
|
|
|
svga->linecountff = 0;
|
|
|
|
|
svga->sc = 0;
|
|
|
|
|
|
2024-05-03 11:18:28 +02:00
|
|
|
svga->maback += (svga->adv_flags & FLAG_NO_SHIFT3) ? svga->rowoffset : (svga->rowoffset << 3);
|
2022-08-31 19:19:29 -04:00
|
|
|
if (svga->interlace)
|
2024-05-03 11:18:28 +02:00
|
|
|
svga->maback += (svga->adv_flags & FLAG_NO_SHIFT3) ? svga->rowoffset : (svga->rowoffset << 3);
|
2023-07-14 23:38:04 +02:00
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->maback &= svga->vram_display_mask;
|
|
|
|
|
svga->ma = svga->maback;
|
|
|
|
|
} else {
|
|
|
|
|
svga->linecountff = 0;
|
|
|
|
|
svga->sc++;
|
2023-07-14 23:38:04 +02:00
|
|
|
svga->sc &= 0x1f;
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->ma = svga->maback;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
svga->hsync_divisor ^= 1;
|
2022-08-31 19:19:29 -04:00
|
|
|
|
|
|
|
|
if (svga->hsync_divisor && (svga->crtc[0x17] & 4))
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
svga->vc++;
|
2023-07-14 23:38:04 +02:00
|
|
|
svga->vc &= 0x7ff;
|
2022-08-31 19:19:29 -04:00
|
|
|
|
|
|
|
|
if (svga->vc == svga->split) {
|
|
|
|
|
ret = 1;
|
|
|
|
|
|
|
|
|
|
if (svga->line_compare)
|
|
|
|
|
ret = svga->line_compare(svga);
|
|
|
|
|
|
|
|
|
|
if (ret) {
|
|
|
|
|
if (svga->interlace && svga->oddeven)
|
2024-02-23 17:02:42 +01:00
|
|
|
svga->ma = svga->maback = (svga->rowoffset << 1) + svga->hblank_sub;
|
2022-08-31 19:19:29 -04:00
|
|
|
else
|
2024-02-23 17:02:42 +01:00
|
|
|
svga->ma = svga->maback = svga->hblank_sub;
|
2024-11-02 20:50:06 +01:00
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->ma = (svga->ma << 2);
|
|
|
|
|
svga->maback = (svga->maback << 2);
|
|
|
|
|
|
|
|
|
|
svga->sc = 0;
|
|
|
|
|
if (svga->attrregs[0x10] & 0x20) {
|
|
|
|
|
svga->scrollcache = 0;
|
2023-01-22 16:50:21 +06:00
|
|
|
svga->x_add = (svga->monitor->mon_overscan_x >> 1);
|
2022-08-31 19:19:29 -04:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (svga->vc == svga->dispend) {
|
|
|
|
|
if (svga->vblank_start)
|
|
|
|
|
svga->vblank_start(svga);
|
2023-07-14 23:38:04 +02:00
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->dispon = 0;
|
|
|
|
|
blink_delay = (svga->crtc[11] & 0x60) >> 5;
|
|
|
|
|
if (svga->crtc[10] & 0x20)
|
|
|
|
|
svga->cursoron = 0;
|
|
|
|
|
else if (blink_delay == 2)
|
|
|
|
|
svga->cursoron = ((svga->blink % 96) >= 48);
|
|
|
|
|
else
|
|
|
|
|
svga->cursoron = svga->blink & (16 + (16 * blink_delay));
|
|
|
|
|
|
2023-11-21 19:32:43 +13:00
|
|
|
if (!(svga->blink & 15))
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->fullchange = 2;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->blink = (svga->blink + 1) & 0x7f;
|
|
|
|
|
|
|
|
|
|
for (x = 0; x < ((svga->vram_mask + 1) >> 12); x++) {
|
|
|
|
|
if (svga->changedvram[x])
|
|
|
|
|
svga->changedvram[x]--;
|
|
|
|
|
}
|
2024-11-02 20:50:06 +01:00
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
if (svga->fullchange)
|
|
|
|
|
svga->fullchange--;
|
|
|
|
|
}
|
|
|
|
|
if (svga->vc == svga->vsyncstart) {
|
|
|
|
|
svga->dispon = 0;
|
|
|
|
|
svga->cgastat |= 8;
|
|
|
|
|
x = svga->hdisp;
|
|
|
|
|
|
|
|
|
|
if (svga->interlace && !svga->oddeven)
|
|
|
|
|
svga->lastline++;
|
|
|
|
|
if (svga->interlace && svga->oddeven)
|
|
|
|
|
svga->firstline--;
|
|
|
|
|
|
|
|
|
|
wx = x;
|
|
|
|
|
|
|
|
|
|
if (!svga->override) {
|
|
|
|
|
if (svga->vertical_linedbl) {
|
|
|
|
|
wy = (svga->lastline - svga->firstline) << 1;
|
2024-08-12 19:52:52 +02:00
|
|
|
svga->vdisp = wy + 1;
|
2022-08-31 19:19:29 -04:00
|
|
|
svga_doblit(wx, wy, svga);
|
|
|
|
|
} else {
|
|
|
|
|
wy = svga->lastline - svga->firstline;
|
2024-08-12 19:52:52 +02:00
|
|
|
svga->vdisp = wy + 1;
|
2022-08-31 19:19:29 -04:00
|
|
|
svga_doblit(wx, wy, svga);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
svga->firstline = 2000;
|
|
|
|
|
svga->lastline = 0;
|
|
|
|
|
|
|
|
|
|
svga->firstline_draw = 2000;
|
|
|
|
|
svga->lastline_draw = 0;
|
|
|
|
|
|
|
|
|
|
svga->oddeven ^= 1;
|
|
|
|
|
|
2023-01-22 16:50:21 +06:00
|
|
|
svga->monitor->mon_changeframecount = svga->interlace ? 3 : 2;
|
2023-07-30 19:22:43 -04:00
|
|
|
svga->vslines = 0;
|
2022-08-31 19:19:29 -04:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (svga->interlace && svga->oddeven)
|
2024-02-23 17:02:42 +01:00
|
|
|
svga->ma = svga->maback = svga->ma_latch + (svga->rowoffset << 1) + svga->hblank_sub;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
else
|
2024-02-23 17:02:42 +01:00
|
|
|
svga->ma = svga->maback = svga->ma_latch + svga->hblank_sub;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
|
2023-07-30 19:22:43 -04:00
|
|
|
svga->ca = ((svga->crtc[0xe] << 8) | svga->crtc[0xf]) + ((svga->crtc[0xb] & 0x60) >> 5) + svga->ca_adj;
|
2024-05-03 11:18:28 +02:00
|
|
|
if (!(svga->adv_flags & FLAG_NO_SHIFT3)) {
|
|
|
|
|
svga->ma = (svga->ma << 2);
|
|
|
|
|
svga->maback = (svga->maback << 2);
|
|
|
|
|
}
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->ca = (svga->ca << 2);
|
|
|
|
|
|
|
|
|
|
if (svga->vsync_callback)
|
|
|
|
|
svga->vsync_callback(svga);
|
|
|
|
|
}
|
2023-08-06 20:29:39 -04:00
|
|
|
#if 0
|
|
|
|
|
if (svga->vc == lines_num) {
|
|
|
|
|
#endif
|
2022-08-31 19:19:29 -04:00
|
|
|
if (svga->vc == svga->vtotal) {
|
|
|
|
|
svga->vc = 0;
|
2024-01-07 09:04:25 +13:00
|
|
|
svga->sc = (svga->crtc[0x8] & 0x1f);
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->dispon = 1;
|
|
|
|
|
svga->displine = (svga->interlace && svga->oddeven) ? 1 : 0;
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
svga->scrollcache = (svga->attrregs[0x13] & 0x0f);
|
|
|
|
|
if (!(svga->gdcreg[6] & 1) && !(svga->attrregs[0x10] & 1)) { /*Text mode*/
|
|
|
|
|
if (svga->seqregs[1] & 1)
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->scrollcache &= 0x07;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
else {
|
|
|
|
|
svga->scrollcache++;
|
|
|
|
|
if (svga->scrollcache > 8)
|
|
|
|
|
svga->scrollcache = 0;
|
|
|
|
|
}
|
|
|
|
|
} else if ((svga->render == svga_render_2bpp_lowres) || (svga->render == svga_render_2bpp_highres) || (svga->render == svga_render_4bpp_lowres) || (svga->render == svga_render_4bpp_highres))
|
|
|
|
|
svga->scrollcache &= 0x07;
|
|
|
|
|
else
|
|
|
|
|
svga->scrollcache = (svga->scrollcache & 0x06) >> 1;
|
2022-08-31 19:19:29 -04:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if ((svga->seqregs[1] & 8) || (svga->render == svga_render_8bpp_lowres))
|
|
|
|
|
svga->scrollcache <<= 1;
|
2022-08-31 19:19:29 -04:00
|
|
|
|
2023-01-22 16:50:21 +06:00
|
|
|
svga->x_add = (svga->monitor->mon_overscan_x >> 1) - svga->scrollcache;
|
2022-08-31 19:19:29 -04:00
|
|
|
|
|
|
|
|
svga->linecountff = 0;
|
|
|
|
|
|
|
|
|
|
svga->hwcursor_on = 0;
|
|
|
|
|
svga->hwcursor_latch = svga->hwcursor;
|
|
|
|
|
|
|
|
|
|
svga->dac_hwcursor_on = 0;
|
|
|
|
|
svga->dac_hwcursor_latch = svga->dac_hwcursor;
|
|
|
|
|
|
|
|
|
|
svga->overlay_on = 0;
|
|
|
|
|
svga->overlay_latch = svga->overlay;
|
|
|
|
|
}
|
|
|
|
|
if (svga->sc == (svga->crtc[10] & 31))
|
|
|
|
|
svga->con = 1;
|
2018-04-25 23:51:13 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2023-12-25 15:24:52 +06:00
|
|
|
uint32_t
|
|
|
|
|
svga_conv_16to32(struct svga_t *svga, uint16_t color, uint8_t bpp)
|
|
|
|
|
{
|
|
|
|
|
return (bpp == 15) ? video_15to32[color] : video_16to32[color];
|
|
|
|
|
}
|
|
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
int
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_init(const device_t *info, svga_t *svga, void *priv, int memsize,
|
2022-08-31 19:19:29 -04:00
|
|
|
void (*recalctimings_ex)(struct svga_t *svga),
|
2023-06-09 23:46:54 -04:00
|
|
|
uint8_t (*video_in)(uint16_t addr, void *priv),
|
|
|
|
|
void (*video_out)(uint16_t addr, uint8_t val, void *priv),
|
2022-08-31 19:19:29 -04:00
|
|
|
void (*hwcursor_draw)(struct svga_t *svga, int displine),
|
|
|
|
|
void (*overlay_draw)(struct svga_t *svga, int displine))
|
2018-04-25 23:51:13 +02:00
|
|
|
{
|
2023-06-01 18:32:25 -04:00
|
|
|
int e;
|
2018-04-25 23:51:13 +02:00
|
|
|
|
2023-07-30 19:22:43 -04:00
|
|
|
svga->priv = priv;
|
2023-01-22 16:50:21 +06:00
|
|
|
svga->monitor_index = monitor_index_global;
|
2023-07-30 19:22:43 -04:00
|
|
|
svga->monitor = &monitors[svga->monitor_index];
|
2018-04-25 23:51:13 +02:00
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
for (int c = 0; c < 256; c++) {
|
2022-08-31 19:19:29 -04:00
|
|
|
e = c;
|
2023-07-14 23:38:04 +02:00
|
|
|
for (int d = 0; d < 8; d++) {
|
2022-08-31 19:19:29 -04:00
|
|
|
svga_rotate[d][c] = e;
|
|
|
|
|
e = (e >> 1) | ((e & 1) ? 0x80 : 0);
|
|
|
|
|
}
|
2018-04-25 23:51:13 +02:00
|
|
|
}
|
|
|
|
|
svga->readmode = 0;
|
|
|
|
|
|
|
|
|
|
svga->attrregs[0x11] = 0;
|
|
|
|
|
svga->overscan_color = 0x000000;
|
|
|
|
|
|
2023-07-30 19:22:43 -04:00
|
|
|
svga->monitor->mon_overscan_x = 16;
|
|
|
|
|
svga->monitor->mon_overscan_y = 32;
|
|
|
|
|
svga->x_add = 8;
|
|
|
|
|
svga->y_add = 16;
|
2018-04-25 23:51:13 +02:00
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->crtc[0] = 63;
|
|
|
|
|
svga->crtc[6] = 255;
|
2023-06-01 18:32:25 -04:00
|
|
|
svga->dispontime = 1000ULL << 32;
|
|
|
|
|
svga->dispofftime = 1000ULL << 32;
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->bpp = 8;
|
2024-07-28 03:44:45 +02:00
|
|
|
svga->vram = calloc(memsize + 8, 1);
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->vram_max = memsize;
|
2018-04-25 23:51:13 +02:00
|
|
|
svga->vram_display_mask = svga->vram_mask = memsize - 1;
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->decode_mask = 0x7fffff;
|
2024-07-02 17:54:44 -03:00
|
|
|
svga->changedvram = calloc((memsize >> 12) + 1, 1);
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->recalctimings_ex = recalctimings_ex;
|
|
|
|
|
svga->video_in = video_in;
|
|
|
|
|
svga->video_out = video_out;
|
|
|
|
|
svga->hwcursor_draw = hwcursor_draw;
|
|
|
|
|
svga->overlay_draw = overlay_draw;
|
2023-12-25 15:24:52 +06:00
|
|
|
svga->conv_16to32 = svga_conv_16to32;
|
2024-05-03 11:18:28 +02:00
|
|
|
svga->render = svga_render_blank;
|
2018-04-25 23:51:13 +02:00
|
|
|
|
2022-07-03 01:07:13 +06:00
|
|
|
svga->hwcursor.cur_xsize = svga->hwcursor.cur_ysize = 32;
|
2018-10-05 01:54:54 +02:00
|
|
|
|
2022-07-03 01:07:13 +06:00
|
|
|
svga->dac_hwcursor.cur_xsize = svga->dac_hwcursor.cur_ysize = 32;
|
2022-02-20 02:26:27 -05:00
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->translate_address = NULL;
|
2022-02-20 02:26:27 -05:00
|
|
|
svga->ksc5601_english_font_type = 0;
|
Added the IBM 5161 ISA expansion for PC and XT;
Cleaned up the parallel port emulation, added IRQ support, and made enabling/disabling per port;
Added the Award 430NX and the Intel Classic/PCI (Alfredo, 420TX);
Finished the 586MC1;
Added 8087 emulation;
Moved Cyrix 6x86'es to the Dev branch;
Sanitized/cleaned up memregs.c/h and intel.c/h;
Split the chipsets from machines and sanitized Port 92 emulation;
Added support for the 15bpp mode to the Compaq ATI 28800;
Moved the MR 386DX and 486 machines to the Dev branch;
Ported the new dynamic recompiler from PCem, but it remains in Dev branch until after v2.00;
Ported the new timer code from PCem;
Cleaned up the CPU table of unused stuff and better optimized its structure;
Ported the Open-XT and Open-AT from VARCem, the Open-AT is in the Dev branch;
Ported the XT MFM controller rewrite and adding of more controllers (incl. two RLL ones), from VARCem;
Added the AHA-1540A and the BusTek BT-542B;
Moved the Sumo SCSI-AT to the Dev branch;
Minor IDE, FDC, and floppy drive code clean-ups;
Made NCR 5380/53C400-based cards' BIOS address configurable;
Got rid of the legacy romset variable;
Unified (video) buffer and buffer32 into one and make the unified buffer 32-bit;
Added the Amstead PPC512 per PCem patch by John Elliott;
Switched memory mapping granularity from 16k to 4k (less than 1k not possible due to internal pages);
Rewrote the CL-GD 54xx blitter, fixes Win-OS/2 on the 54x6 among other thing;
Added the Image Manager 1024 and Professional Graphics Controller per PCem patch by John Elliott and work done on VARCem;
Added Headland HT-216, GC-205 and Video 7 VGA 1024i emulation based on PCem commit;
Implemented the fuction keys for the Toshiba T1000/T1200/T3100 enhancement;
Amstrad MegaPC does now works correctly with non-internal graphics card;
The SLiRP code no longer casts a packed struct type to a non-packed struct type;
The Xi8088 and PB410a no longer hang on 86Box when PS/2 mouse is not present;
The S3 Virge on BeOS is no longer broken (was broken by build #1591);
OS/2 2.0 build 6.167 now sees key presses again;
Xi8088 now work on CGA again;
86F images converted from either the old or new variants of the HxC MFM format now work correctly;
Hardware interrupts with a vector of 0xFF are now handled correctly;
OPTi 495SX boards no longer incorrectly have 64 MB maximum RAM when 32 MB is correct;
Fixed VNC keyboard input bugs;
Fixed AT RTC periodic interrupt - Chicago 58s / 73f / 73g / 81 MIDI play no longer hangs with the build's own VTD driver;
Fixed mouse polling with internal mice - Amstrad and Olivetti mice now work correctly;
Triones ATAPI DMA driver now correctly reads a file at the end of a CD image with a sectors number not divisible by 4;
Compaq Portable now works with all graphics cards;
Fixed various MDSI Genius bugs;
Added segment limit checks and improved page fault checks for several CPU instructions - Memphis 15xx WINSETUP and Chicago 58s WINDISK.CPL no longer issue a GPF, and some S3 drivers that used to have glitches, now work correctly;
Further improved the 808x emulation, also fixes the noticably choppy sound when using 808x CPU's, also fixes #355;
OS/2 installer no logner locks up on splash screen on PS/2 Model 70 and 80, fixes #400.
Fixed several Amstead bugs, GEM no longer crashes on the Amstrad 1640, fixes #391.
Ported John Elliott's Amstrad fixes and improvement from PCem, and fixed the default language so it's correctly Engliish, fixes #278, fixes #389.
Fixed a minor IDE timing bug, fixes #388.
Fixed Toshiba T1000 RAM issues, fixes #379.
Fixed EGA/(S)VGA overscan border handling, fixes #378;
Got rid of the now long useless IDE channel 2 auto-removal, fixes #370;
Fixed the BIOS files used by the AMSTRAD PC1512, fixes #366;
Ported the Unicode CD image file name fix from VARCem, fixes #365;
Fixed high density floppy disks on the Xi8088, fixes #359;
Fixed some bugs in the Hercules emulation, fixes #346, fixes #358;
Fixed the SCSI hard disk mode sense pages, fixes #356;
Removed the AMI Unknown 386SX because of impossibility to identify the chipset, closes #349;
Fixed bugs in the serial mouse emulation, fixes #344;
Compiled 86Box binaries now include all the required .DLL's, fixes #341;
Made some combo boxes in the Settings dialog slightly wider, fixes #276.
2019-09-20 14:02:30 +02:00
|
|
|
|
2021-10-24 19:06:05 +02:00
|
|
|
if ((info->flags & DEVICE_PCI) || (info->flags & DEVICE_VLB) || (info->flags & DEVICE_MCA)) {
|
2022-08-31 19:19:29 -04:00
|
|
|
mem_mapping_add(&svga->mapping, 0xa0000, 0x20000,
|
|
|
|
|
svga_read, svga_readw, svga_readl,
|
|
|
|
|
svga_write, svga_writew, svga_writel,
|
|
|
|
|
NULL, MEM_MAPPING_EXTERNAL, svga);
|
2020-05-06 00:23:07 +02:00
|
|
|
} else if ((info->flags & DEVICE_ISA) && (info->flags & DEVICE_AT)) {
|
2022-08-31 19:19:29 -04:00
|
|
|
mem_mapping_add(&svga->mapping, 0xa0000, 0x20000,
|
|
|
|
|
svga_read, svga_readw, NULL,
|
|
|
|
|
svga_write, svga_writew, NULL,
|
|
|
|
|
NULL, MEM_MAPPING_EXTERNAL, svga);
|
2020-05-06 00:23:07 +02:00
|
|
|
} else {
|
2022-08-31 19:19:29 -04:00
|
|
|
mem_mapping_add(&svga->mapping, 0xa0000, 0x20000,
|
|
|
|
|
svga_read, NULL, NULL,
|
|
|
|
|
svga_write, NULL, NULL,
|
|
|
|
|
NULL, MEM_MAPPING_EXTERNAL, svga);
|
2020-05-06 00:23:07 +02:00
|
|
|
}
|
2018-04-25 23:51:13 +02:00
|
|
|
|
Added the IBM 5161 ISA expansion for PC and XT;
Cleaned up the parallel port emulation, added IRQ support, and made enabling/disabling per port;
Added the Award 430NX and the Intel Classic/PCI (Alfredo, 420TX);
Finished the 586MC1;
Added 8087 emulation;
Moved Cyrix 6x86'es to the Dev branch;
Sanitized/cleaned up memregs.c/h and intel.c/h;
Split the chipsets from machines and sanitized Port 92 emulation;
Added support for the 15bpp mode to the Compaq ATI 28800;
Moved the MR 386DX and 486 machines to the Dev branch;
Ported the new dynamic recompiler from PCem, but it remains in Dev branch until after v2.00;
Ported the new timer code from PCem;
Cleaned up the CPU table of unused stuff and better optimized its structure;
Ported the Open-XT and Open-AT from VARCem, the Open-AT is in the Dev branch;
Ported the XT MFM controller rewrite and adding of more controllers (incl. two RLL ones), from VARCem;
Added the AHA-1540A and the BusTek BT-542B;
Moved the Sumo SCSI-AT to the Dev branch;
Minor IDE, FDC, and floppy drive code clean-ups;
Made NCR 5380/53C400-based cards' BIOS address configurable;
Got rid of the legacy romset variable;
Unified (video) buffer and buffer32 into one and make the unified buffer 32-bit;
Added the Amstead PPC512 per PCem patch by John Elliott;
Switched memory mapping granularity from 16k to 4k (less than 1k not possible due to internal pages);
Rewrote the CL-GD 54xx blitter, fixes Win-OS/2 on the 54x6 among other thing;
Added the Image Manager 1024 and Professional Graphics Controller per PCem patch by John Elliott and work done on VARCem;
Added Headland HT-216, GC-205 and Video 7 VGA 1024i emulation based on PCem commit;
Implemented the fuction keys for the Toshiba T1000/T1200/T3100 enhancement;
Amstrad MegaPC does now works correctly with non-internal graphics card;
The SLiRP code no longer casts a packed struct type to a non-packed struct type;
The Xi8088 and PB410a no longer hang on 86Box when PS/2 mouse is not present;
The S3 Virge on BeOS is no longer broken (was broken by build #1591);
OS/2 2.0 build 6.167 now sees key presses again;
Xi8088 now work on CGA again;
86F images converted from either the old or new variants of the HxC MFM format now work correctly;
Hardware interrupts with a vector of 0xFF are now handled correctly;
OPTi 495SX boards no longer incorrectly have 64 MB maximum RAM when 32 MB is correct;
Fixed VNC keyboard input bugs;
Fixed AT RTC periodic interrupt - Chicago 58s / 73f / 73g / 81 MIDI play no longer hangs with the build's own VTD driver;
Fixed mouse polling with internal mice - Amstrad and Olivetti mice now work correctly;
Triones ATAPI DMA driver now correctly reads a file at the end of a CD image with a sectors number not divisible by 4;
Compaq Portable now works with all graphics cards;
Fixed various MDSI Genius bugs;
Added segment limit checks and improved page fault checks for several CPU instructions - Memphis 15xx WINSETUP and Chicago 58s WINDISK.CPL no longer issue a GPF, and some S3 drivers that used to have glitches, now work correctly;
Further improved the 808x emulation, also fixes the noticably choppy sound when using 808x CPU's, also fixes #355;
OS/2 installer no logner locks up on splash screen on PS/2 Model 70 and 80, fixes #400.
Fixed several Amstead bugs, GEM no longer crashes on the Amstrad 1640, fixes #391.
Ported John Elliott's Amstrad fixes and improvement from PCem, and fixed the default language so it's correctly Engliish, fixes #278, fixes #389.
Fixed a minor IDE timing bug, fixes #388.
Fixed Toshiba T1000 RAM issues, fixes #379.
Fixed EGA/(S)VGA overscan border handling, fixes #378;
Got rid of the now long useless IDE channel 2 auto-removal, fixes #370;
Fixed the BIOS files used by the AMSTRAD PC1512, fixes #366;
Ported the Unicode CD image file name fix from VARCem, fixes #365;
Fixed high density floppy disks on the Xi8088, fixes #359;
Fixed some bugs in the Hercules emulation, fixes #346, fixes #358;
Fixed the SCSI hard disk mode sense pages, fixes #356;
Removed the AMI Unknown 386SX because of impossibility to identify the chipset, closes #349;
Fixed bugs in the serial mouse emulation, fixes #344;
Compiled 86Box binaries now include all the required .DLL's, fixes #341;
Made some combo boxes in the Settings dialog slightly wider, fixes #276.
2019-09-20 14:02:30 +02:00
|
|
|
timer_add(&svga->timer, svga_poll, svga, 1);
|
2018-04-25 23:51:13 +02:00
|
|
|
|
|
|
|
|
svga_pri = svga;
|
|
|
|
|
|
|
|
|
|
svga->ramdac_type = RAMDAC_6BIT;
|
|
|
|
|
|
2023-08-06 20:29:39 -04:00
|
|
|
svga->map8 = svga->pallook;
|
2019-10-20 15:09:38 +02:00
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
return 0;
|
2016-10-08 04:20:30 +02:00
|
|
|
}
|
|
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
void
|
|
|
|
|
svga_close(svga_t *svga)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2018-04-25 23:51:13 +02:00
|
|
|
free(svga->changedvram);
|
|
|
|
|
free(svga->vram);
|
|
|
|
|
|
2021-04-14 16:09:08 -03:00
|
|
|
if (svga->dpms_ui)
|
2022-08-31 19:19:29 -04:00
|
|
|
ui_sb_set_text_w(NULL);
|
2021-04-14 16:09:08 -03:00
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
svga_pri = NULL;
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2024-10-03 14:56:23 +02:00
|
|
|
uint32_t
|
2019-12-04 07:20:58 +01:00
|
|
|
svga_decode_addr(svga_t *svga, uint32_t addr, int write)
|
|
|
|
|
{
|
|
|
|
|
int memory_map_mode = (svga->gdcreg[6] >> 2) & 3;
|
|
|
|
|
|
|
|
|
|
addr &= 0x1ffff;
|
|
|
|
|
|
|
|
|
|
switch (memory_map_mode) {
|
2022-08-31 19:19:29 -04:00
|
|
|
case 0:
|
|
|
|
|
break;
|
|
|
|
|
case 1:
|
|
|
|
|
if (addr >= 0x10000)
|
|
|
|
|
return 0xffffffff;
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
addr -= 0x10000;
|
|
|
|
|
if (addr >= 0x8000)
|
|
|
|
|
return 0xffffffff;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
case 3:
|
|
|
|
|
addr -= 0x18000;
|
|
|
|
|
if (addr >= 0x8000)
|
|
|
|
|
return 0xffffffff;
|
|
|
|
|
break;
|
2019-12-04 07:20:58 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (memory_map_mode <= 1) {
|
2024-02-09 18:28:09 +01:00
|
|
|
if (write)
|
|
|
|
|
addr += svga->write_bank;
|
|
|
|
|
else
|
|
|
|
|
addr += svga->read_bank;
|
2019-12-04 07:20:58 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return addr;
|
|
|
|
|
}
|
|
|
|
|
|
2021-03-24 19:35:07 +01:00
|
|
|
static __inline void
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_write_common(uint32_t addr, uint8_t val, uint8_t linear, void *priv)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2023-08-11 20:32:56 -04:00
|
|
|
svga_t *svga = (svga_t *) priv;
|
2023-06-01 18:32:25 -04:00
|
|
|
int writemask2 = svga->writemask;
|
2023-07-30 19:22:43 -04:00
|
|
|
int reset_wm = 0;
|
2019-12-04 07:20:58 +01:00
|
|
|
latch_t vall;
|
2023-08-11 20:32:56 -04:00
|
|
|
uint8_t wm = svga->writemask;
|
2023-06-01 18:32:25 -04:00
|
|
|
uint8_t count;
|
|
|
|
|
uint8_t i;
|
2019-10-01 15:14:51 +02:00
|
|
|
|
|
|
|
|
if (svga->adv_flags & FLAG_ADDR_BY8)
|
2022-08-31 19:19:29 -04:00
|
|
|
writemask2 = svga->seqregs[2];
|
2018-04-25 23:51:13 +02:00
|
|
|
|
2023-01-22 16:50:21 +06:00
|
|
|
cycles -= svga->monitor->mon_video_timing_write_b;
|
2018-04-25 23:51:13 +02:00
|
|
|
|
|
|
|
|
if (!linear) {
|
2024-10-03 14:56:23 +02:00
|
|
|
xga_write_test(addr, val, svga);
|
2022-08-31 19:19:29 -04:00
|
|
|
addr = svga_decode_addr(svga, addr, 1);
|
2024-10-26 21:32:47 +02:00
|
|
|
if (addr == 0xffffffff) {
|
|
|
|
|
svga_log("WriteCommon Over.\n");
|
2022-08-31 19:19:29 -04:00
|
|
|
return;
|
2024-10-26 21:32:47 +02:00
|
|
|
}
|
2018-04-25 23:51:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (!(svga->gdcreg[6] & 1))
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->fullchange = 2;
|
2018-04-25 23:51:13 +02:00
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
if ((svga->adv_flags & FLAG_ADDR_BY16) && (svga->writemode == 4 || svga->writemode == 5))
|
|
|
|
|
addr <<= 4;
|
2021-05-30 23:40:56 +02:00
|
|
|
else if ((svga->adv_flags & FLAG_ADDR_BY8) && (svga->writemode < 4))
|
2022-08-31 19:19:29 -04:00
|
|
|
addr <<= 3;
|
2022-03-02 16:18:58 +01:00
|
|
|
else if (((svga->chain4 && (svga->packed_chain4 || svga->force_old_addr)) || svga->fb_only) && (svga->writemode < 4)) {
|
2022-08-31 19:19:29 -04:00
|
|
|
writemask2 = 1 << (addr & 3);
|
|
|
|
|
addr &= ~3;
|
|
|
|
|
} else if (svga->chain4 && (svga->writemode < 4)) {
|
|
|
|
|
writemask2 = 1 << (addr & 3);
|
|
|
|
|
if (!linear)
|
|
|
|
|
addr &= ~3;
|
|
|
|
|
addr = ((addr & 0xfffc) << 2) | ((addr & 0x30000) >> 14) | (addr & ~0x3ffff);
|
2018-04-25 23:51:13 +02:00
|
|
|
} else if (svga->chain2_write) {
|
2022-08-31 19:19:29 -04:00
|
|
|
writemask2 &= ~0xa;
|
|
|
|
|
if (addr & 1)
|
|
|
|
|
writemask2 <<= 1;
|
|
|
|
|
addr &= ~1;
|
2023-08-15 00:11:56 +02:00
|
|
|
addr <<= 2;
|
|
|
|
|
} else
|
|
|
|
|
addr <<= 2;
|
|
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
addr &= svga->decode_mask;
|
|
|
|
|
|
2020-05-12 00:37:30 +02:00
|
|
|
if (svga->translate_address)
|
2023-06-09 23:46:54 -04:00
|
|
|
addr = svga->translate_address(addr, priv);
|
2020-05-12 00:37:30 +02:00
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if (addr >= svga->vram_max) {
|
|
|
|
|
svga_log("WriteBankedOver=%08x, val=%02x.\n", addr & svga->vram_mask, val);
|
2022-08-31 19:19:29 -04:00
|
|
|
return;
|
2024-10-26 21:32:47 +02:00
|
|
|
}
|
2018-04-25 23:51:13 +02:00
|
|
|
|
|
|
|
|
addr &= svga->vram_mask;
|
|
|
|
|
|
2023-01-22 16:50:21 +06:00
|
|
|
svga->changedvram[addr >> 12] = svga->monitor->mon_changeframecount;
|
2018-04-25 23:51:13 +02:00
|
|
|
|
2019-12-04 07:20:58 +01:00
|
|
|
count = 4;
|
|
|
|
|
if (svga->adv_flags & FLAG_LATCH8)
|
2022-08-31 19:19:29 -04:00
|
|
|
count = 8;
|
2018-04-25 23:51:13 +02:00
|
|
|
|
2020-11-26 18:20:24 +01:00
|
|
|
/* Undocumented Cirrus Logic behavior: The datasheet says that, with EXT_WRITE and FLAG_ADDR_BY8, the write mask only
|
|
|
|
|
changes meaning in write modes 4 and 5, as well as write mode 1. In reality, however, all other write modes are also
|
|
|
|
|
affected, as proven by the Windows 3.1 CL-GD 5422/4 drivers in 8bpp modes. */
|
2018-04-25 23:51:13 +02:00
|
|
|
switch (svga->writemode) {
|
2022-08-31 19:19:29 -04:00
|
|
|
case 0:
|
|
|
|
|
val = ((val >> (svga->gdcreg[3] & 7)) | (val << (8 - (svga->gdcreg[3] & 7))));
|
|
|
|
|
if ((svga->gdcreg[8] == 0xff) && !(svga->gdcreg[3] & 0x18) && (!svga->gdcreg[1] || svga->set_reset_disabled)) {
|
|
|
|
|
for (i = 0; i < count; i++) {
|
|
|
|
|
if ((svga->adv_flags & FLAG_EXT_WRITE) && (svga->adv_flags & FLAG_ADDR_BY8)) {
|
|
|
|
|
if (writemask2 & (0x80 >> i))
|
|
|
|
|
svga->vram[addr | i] = val;
|
|
|
|
|
} else {
|
|
|
|
|
if (writemask2 & (1 << i))
|
|
|
|
|
svga->vram[addr | i] = val;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
return;
|
|
|
|
|
} else {
|
|
|
|
|
for (i = 0; i < count; i++) {
|
|
|
|
|
if (svga->gdcreg[1] & (1 << i))
|
|
|
|
|
vall.b[i] = !!(svga->gdcreg[0] & (1 << i)) * 0xff;
|
|
|
|
|
else
|
|
|
|
|
vall.b[i] = val;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 1:
|
|
|
|
|
for (i = 0; i < count; i++) {
|
|
|
|
|
if ((svga->adv_flags & FLAG_EXT_WRITE) && (svga->adv_flags & FLAG_ADDR_BY8)) {
|
|
|
|
|
if (writemask2 & (0x80 >> i))
|
|
|
|
|
svga->vram[addr | i] = svga->latch.b[i];
|
|
|
|
|
} else {
|
|
|
|
|
if (writemask2 & (1 << i))
|
|
|
|
|
svga->vram[addr | i] = svga->latch.b[i];
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
return;
|
|
|
|
|
case 2:
|
|
|
|
|
for (i = 0; i < count; i++)
|
|
|
|
|
vall.b[i] = !!(val & (1 << i)) * 0xff;
|
|
|
|
|
|
|
|
|
|
if (!(svga->gdcreg[3] & 0x18) && (!svga->gdcreg[1] || svga->set_reset_disabled)) {
|
|
|
|
|
for (i = 0; i < count; i++) {
|
|
|
|
|
if ((svga->adv_flags & FLAG_EXT_WRITE) && (svga->adv_flags & FLAG_ADDR_BY8)) {
|
|
|
|
|
if (writemask2 & (0x80 >> i))
|
|
|
|
|
svga->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) | (svga->latch.b[i] & ~svga->gdcreg[8]);
|
|
|
|
|
} else {
|
|
|
|
|
if (writemask2 & (1 << i))
|
|
|
|
|
svga->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) | (svga->latch.b[i] & ~svga->gdcreg[8]);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 3:
|
|
|
|
|
val = ((val >> (svga->gdcreg[3] & 7)) | (val << (8 - (svga->gdcreg[3] & 7))));
|
|
|
|
|
wm = svga->gdcreg[8];
|
|
|
|
|
svga->gdcreg[8] &= val;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < count; i++)
|
|
|
|
|
vall.b[i] = !!(svga->gdcreg[0] & (1 << i)) * 0xff;
|
|
|
|
|
|
|
|
|
|
reset_wm = 1;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
if (svga->ven_write)
|
|
|
|
|
svga->ven_write(svga, val, addr);
|
|
|
|
|
return;
|
2018-04-25 23:51:13 +02:00
|
|
|
}
|
|
|
|
|
|
2019-12-04 07:20:58 +01:00
|
|
|
switch (svga->gdcreg[3] & 0x18) {
|
2022-08-31 19:19:29 -04:00
|
|
|
case 0x00: /* Set */
|
|
|
|
|
for (i = 0; i < count; i++) {
|
|
|
|
|
if ((svga->adv_flags & FLAG_EXT_WRITE) && (svga->adv_flags & FLAG_ADDR_BY8)) {
|
|
|
|
|
if (writemask2 & (0x80 >> i))
|
|
|
|
|
svga->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) | (svga->latch.b[i] & ~svga->gdcreg[8]);
|
|
|
|
|
} else {
|
|
|
|
|
if (writemask2 & (1 << i))
|
|
|
|
|
svga->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) | (svga->latch.b[i] & ~svga->gdcreg[8]);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0x08: /* AND */
|
|
|
|
|
for (i = 0; i < count; i++) {
|
|
|
|
|
if ((svga->adv_flags & FLAG_EXT_WRITE) && (svga->adv_flags & FLAG_ADDR_BY8)) {
|
|
|
|
|
if (writemask2 & (0x80 >> i))
|
|
|
|
|
svga->vram[addr | i] = (vall.b[i] | ~svga->gdcreg[8]) & svga->latch.b[i];
|
|
|
|
|
} else {
|
|
|
|
|
if (writemask2 & (1 << i))
|
|
|
|
|
svga->vram[addr | i] = (vall.b[i] | ~svga->gdcreg[8]) & svga->latch.b[i];
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0x10: /* OR */
|
|
|
|
|
for (i = 0; i < count; i++) {
|
|
|
|
|
if ((svga->adv_flags & FLAG_EXT_WRITE) && (svga->adv_flags & FLAG_ADDR_BY8)) {
|
|
|
|
|
if (writemask2 & (0x80 >> i))
|
|
|
|
|
svga->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) | svga->latch.b[i];
|
|
|
|
|
} else {
|
|
|
|
|
if (writemask2 & (1 << i))
|
|
|
|
|
svga->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) | svga->latch.b[i];
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0x18: /* XOR */
|
|
|
|
|
for (i = 0; i < count; i++) {
|
|
|
|
|
if ((svga->adv_flags & FLAG_EXT_WRITE) && (svga->adv_flags & FLAG_ADDR_BY8)) {
|
|
|
|
|
if (writemask2 & (0x80 >> i))
|
|
|
|
|
svga->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) ^ svga->latch.b[i];
|
|
|
|
|
} else {
|
|
|
|
|
if (writemask2 & (1 << i))
|
|
|
|
|
svga->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) ^ svga->latch.b[i];
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
2023-07-30 19:22:43 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2018-04-25 23:51:13 +02:00
|
|
|
}
|
|
|
|
|
|
2019-12-04 07:20:58 +01:00
|
|
|
if (reset_wm)
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->gdcreg[8] = wm;
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2021-03-24 19:35:07 +01:00
|
|
|
static __inline uint8_t
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_read_common(uint32_t addr, uint8_t linear, void *priv)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_t *svga = (svga_t *) priv;
|
2019-10-01 15:14:51 +02:00
|
|
|
uint32_t latch_addr = 0;
|
2022-08-31 19:19:29 -04:00
|
|
|
int readplane = svga->readplane;
|
2023-06-01 18:32:25 -04:00
|
|
|
uint8_t count;
|
|
|
|
|
uint8_t temp;
|
2024-10-03 14:56:23 +02:00
|
|
|
uint8_t ret = 0x00;
|
2019-10-01 15:14:51 +02:00
|
|
|
|
|
|
|
|
if (svga->adv_flags & FLAG_ADDR_BY8)
|
2022-08-31 19:19:29 -04:00
|
|
|
readplane = svga->gdcreg[4] & 7;
|
2018-04-25 23:51:13 +02:00
|
|
|
|
2023-01-22 16:50:21 +06:00
|
|
|
cycles -= svga->monitor->mon_video_timing_read_b;
|
2018-04-25 23:51:13 +02:00
|
|
|
|
|
|
|
|
if (!linear) {
|
2024-10-03 14:56:23 +02:00
|
|
|
(void) xga_read_test(addr, svga);
|
2022-08-31 19:19:29 -04:00
|
|
|
addr = svga_decode_addr(svga, addr, 0);
|
|
|
|
|
if (addr == 0xffffffff)
|
|
|
|
|
return 0xff;
|
2018-04-25 23:51:13 +02:00
|
|
|
}
|
|
|
|
|
|
2019-12-04 07:20:58 +01:00
|
|
|
count = 2;
|
|
|
|
|
if (svga->adv_flags & FLAG_LATCH8)
|
2022-08-31 19:19:29 -04:00
|
|
|
count = 3;
|
2019-12-04 07:20:58 +01:00
|
|
|
|
|
|
|
|
latch_addr = (addr << count) & svga->decode_mask;
|
2022-08-31 19:19:29 -04:00
|
|
|
count = (1 << count);
|
2019-12-04 07:20:58 +01:00
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
if (svga->adv_flags & FLAG_ADDR_BY16)
|
|
|
|
|
addr <<= 4;
|
2021-05-30 23:40:56 +02:00
|
|
|
else if (svga->adv_flags & FLAG_ADDR_BY8)
|
2022-08-31 19:19:29 -04:00
|
|
|
addr <<= 3;
|
2022-03-02 16:18:58 +01:00
|
|
|
else if ((svga->chain4 && (svga->packed_chain4 || svga->force_old_addr)) || svga->fb_only) {
|
2022-08-31 19:19:29 -04:00
|
|
|
addr &= svga->decode_mask;
|
|
|
|
|
if (svga->translate_address)
|
2023-06-09 23:46:54 -04:00
|
|
|
addr = svga->translate_address(addr, priv);
|
2022-08-31 19:19:29 -04:00
|
|
|
if (addr >= svga->vram_max)
|
|
|
|
|
return 0xff;
|
|
|
|
|
latch_addr = (addr & svga->vram_mask) & ~3;
|
2023-06-01 18:32:25 -04:00
|
|
|
for (uint8_t i = 0; i < count; i++)
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->latch.b[i] = svga->vram[latch_addr | i];
|
|
|
|
|
return svga->vram[addr & svga->vram_mask];
|
|
|
|
|
} else if (svga->chain4 && !svga->force_old_addr) {
|
|
|
|
|
readplane = addr & 3;
|
|
|
|
|
addr = ((addr & 0xfffc) << 2) | ((addr & 0x30000) >> 14) | (addr & ~0x3ffff);
|
2018-04-25 23:51:13 +02:00
|
|
|
} else if (svga->chain2_read) {
|
2022-08-31 19:19:29 -04:00
|
|
|
readplane = (readplane & 2) | (addr & 1);
|
|
|
|
|
addr &= ~1;
|
2023-08-15 00:11:56 +02:00
|
|
|
addr <<= 2;
|
|
|
|
|
} else
|
|
|
|
|
addr <<= 2;
|
|
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
addr &= svga->decode_mask;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
2020-05-12 13:50:23 +02:00
|
|
|
if (svga->translate_address) {
|
2023-06-09 23:46:54 -04:00
|
|
|
latch_addr = svga->translate_address(latch_addr, priv);
|
|
|
|
|
addr = svga->translate_address(addr, priv);
|
2020-05-12 00:37:30 +02:00
|
|
|
}
|
2018-04-25 23:51:13 +02:00
|
|
|
|
|
|
|
|
/* standard VGA latched access */
|
2019-12-28 05:51:22 +01:00
|
|
|
if (latch_addr >= svga->vram_max) {
|
2023-06-01 18:32:25 -04:00
|
|
|
for (uint8_t i = 0; i < count; i++)
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->latch.b[i] = 0xff;
|
2018-04-25 23:51:13 +02:00
|
|
|
} else {
|
2022-08-31 19:19:29 -04:00
|
|
|
latch_addr &= svga->vram_mask;
|
2019-12-04 07:20:58 +01:00
|
|
|
|
2023-06-01 18:32:25 -04:00
|
|
|
for (uint8_t i = 0; i < count; i++)
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->latch.b[i] = svga->vram[latch_addr | i];
|
2019-12-28 05:51:22 +01:00
|
|
|
}
|
2018-04-25 23:51:13 +02:00
|
|
|
|
2019-12-28 05:51:22 +01:00
|
|
|
if (addr >= svga->vram_max)
|
2022-08-31 19:19:29 -04:00
|
|
|
return 0xff;
|
2018-04-25 23:51:13 +02:00
|
|
|
|
2019-12-28 05:51:22 +01:00
|
|
|
addr &= svga->vram_mask;
|
2018-04-25 23:51:13 +02:00
|
|
|
|
2019-12-04 07:20:58 +01:00
|
|
|
if (svga->readmode) {
|
2022-08-31 19:19:29 -04:00
|
|
|
temp = 0xff;
|
|
|
|
|
|
2023-06-01 18:32:25 -04:00
|
|
|
for (uint8_t pixel = 0; pixel < 8; pixel++) {
|
|
|
|
|
for (uint8_t plane = 0; plane < count; plane++) {
|
2022-08-31 19:19:29 -04:00
|
|
|
if (svga->colournocare & (1 << plane)) {
|
|
|
|
|
/* If we care about a plane, and the pixel has a mismatch on it, clear its bit. */
|
|
|
|
|
if (((svga->latch.b[plane] >> pixel) & 1) != ((svga->colourcompare >> plane) & 1))
|
|
|
|
|
temp &= ~(1 << pixel);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ret = temp;
|
2019-12-04 07:20:58 +01:00
|
|
|
} else
|
2022-08-31 19:19:29 -04:00
|
|
|
ret = svga->vram[addr | readplane];
|
2019-12-04 07:20:58 +01:00
|
|
|
|
|
|
|
|
return ret;
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
void
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_write(uint32_t addr, uint8_t val, void *priv)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_write_common(addr, val, 0, priv);
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
void
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_write_linear(uint32_t addr, uint8_t val, void *priv)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_write_common(addr, val, 1, priv);
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
uint8_t
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_read(uint32_t addr, void *priv)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2023-06-09 23:46:54 -04:00
|
|
|
return svga_read_common(addr, 0, priv);
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
uint8_t
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_read_linear(uint32_t addr, void *priv)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2023-06-09 23:46:54 -04:00
|
|
|
return svga_read_common(addr, 1, priv);
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
void
|
2021-09-13 23:19:10 +02:00
|
|
|
svga_doblit(int wx, int wy, svga_t *svga)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2023-06-01 18:32:25 -04:00
|
|
|
int y_add;
|
|
|
|
|
int x_add;
|
|
|
|
|
int y_start;
|
|
|
|
|
int x_start;
|
|
|
|
|
int bottom;
|
2018-04-25 23:51:13 +02:00
|
|
|
uint32_t *p;
|
2023-06-01 18:32:25 -04:00
|
|
|
int i;
|
|
|
|
|
int j;
|
|
|
|
|
int xs_temp;
|
|
|
|
|
int ys_temp;
|
|
|
|
|
|
|
|
|
|
y_add = enable_overscan ? svga->monitor->mon_overscan_y : 0;
|
|
|
|
|
x_add = enable_overscan ? svga->monitor->mon_overscan_x : 0;
|
|
|
|
|
y_start = enable_overscan ? 0 : (svga->monitor->mon_overscan_y >> 1);
|
|
|
|
|
x_start = enable_overscan ? 0 : (svga->monitor->mon_overscan_x >> 1);
|
2024-01-07 09:04:25 +13:00
|
|
|
bottom = (svga->monitor->mon_overscan_y >> 1);
|
2019-10-20 15:09:38 +02:00
|
|
|
|
2020-01-20 05:36:44 +01:00
|
|
|
if (svga->vertical_linedbl) {
|
2022-08-31 19:19:29 -04:00
|
|
|
y_add <<= 1;
|
|
|
|
|
y_start <<= 1;
|
|
|
|
|
bottom <<= 1;
|
2020-01-20 05:36:44 +01:00
|
|
|
}
|
|
|
|
|
|
2021-09-13 23:28:00 +02:00
|
|
|
if ((wx <= 0) || (wy <= 0))
|
2022-08-31 19:19:29 -04:00
|
|
|
return;
|
2018-04-25 23:51:13 +02:00
|
|
|
|
2020-01-20 05:36:44 +01:00
|
|
|
if (svga->vertical_linedbl)
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->y_add <<= 1;
|
2020-01-20 05:36:44 +01:00
|
|
|
|
2019-09-26 16:00:43 +02:00
|
|
|
xs_temp = wx;
|
|
|
|
|
ys_temp = wy + 1;
|
2020-01-20 05:36:44 +01:00
|
|
|
if (svga->vertical_linedbl)
|
2022-08-31 19:19:29 -04:00
|
|
|
ys_temp++;
|
2019-09-26 16:00:43 +02:00
|
|
|
if (xs_temp < 64)
|
2022-08-31 19:19:29 -04:00
|
|
|
xs_temp = 640;
|
2019-09-26 16:00:43 +02:00
|
|
|
if (ys_temp < 32)
|
2022-08-31 19:19:29 -04:00
|
|
|
ys_temp = 200;
|
2019-09-26 16:00:43 +02:00
|
|
|
|
2023-01-22 16:50:21 +06:00
|
|
|
if ((svga->crtc[0x17] & 0x80) && ((xs_temp != svga->monitor->mon_xsize) || (ys_temp != svga->monitor->mon_ysize) || video_force_resize_get_monitor(svga->monitor_index))) {
|
2022-08-31 19:19:29 -04:00
|
|
|
/* Screen res has changed.. fix up, and let them know. */
|
2023-01-22 16:50:21 +06:00
|
|
|
svga->monitor->mon_xsize = xs_temp;
|
|
|
|
|
svga->monitor->mon_ysize = ys_temp;
|
2022-08-31 19:19:29 -04:00
|
|
|
|
2023-01-22 16:50:21 +06:00
|
|
|
if ((svga->monitor->mon_xsize > 1984) || (svga->monitor->mon_ysize > 2016)) {
|
2022-08-31 19:19:29 -04:00
|
|
|
/* 2048x2048 is the biggest safe render texture, to account for overscan,
|
|
|
|
|
we suppress overscan starting from x 1984 and y 2016. */
|
|
|
|
|
x_add = 0;
|
|
|
|
|
y_add = 0;
|
|
|
|
|
suppress_overscan = 1;
|
|
|
|
|
} else
|
|
|
|
|
suppress_overscan = 0;
|
|
|
|
|
|
|
|
|
|
/* Block resolution changes while in DPMS mode to avoid getting a bogus
|
|
|
|
|
screen width (320). We're already rendering a blank screen anyway. */
|
|
|
|
|
if (!svga->dpms)
|
2023-01-22 16:50:21 +06:00
|
|
|
set_screen_size_monitor(svga->monitor->mon_xsize + x_add, svga->monitor->mon_ysize + y_add, svga->monitor_index);
|
2022-08-31 19:19:29 -04:00
|
|
|
|
2023-01-22 16:50:21 +06:00
|
|
|
if (video_force_resize_get_monitor(svga->monitor_index))
|
|
|
|
|
video_force_resize_set_monitor(0, svga->monitor_index);
|
2018-04-25 23:51:13 +02:00
|
|
|
}
|
|
|
|
|
|
2019-10-20 15:09:38 +02:00
|
|
|
if ((wx >= 160) && ((wy + 1) >= 120)) {
|
2022-08-31 19:19:29 -04:00
|
|
|
/* Draw (overscan_size - scroll size) lines of overscan on top and bottom. */
|
|
|
|
|
for (i = 0; i < svga->y_add; i++) {
|
2023-01-22 16:50:21 +06:00
|
|
|
p = &svga->monitor->target_buffer->line[i & 0x7ff][0];
|
2016-06-26 00:34:39 +02:00
|
|
|
|
2023-01-22 16:50:21 +06:00
|
|
|
for (j = 0; j < (svga->monitor->mon_xsize + x_add); j++)
|
2024-02-21 02:25:40 +06:00
|
|
|
p[j] = svga->dpms ? 0 : svga->overscan_color;
|
2022-08-31 19:19:29 -04:00
|
|
|
}
|
2017-05-19 04:35:59 +02:00
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
for (i = 0; i < bottom; i++) {
|
2023-01-22 16:50:21 +06:00
|
|
|
p = &svga->monitor->target_buffer->line[(svga->monitor->mon_ysize + svga->y_add + i) & 0x7ff][0];
|
2016-06-26 00:34:39 +02:00
|
|
|
|
2023-01-22 16:50:21 +06:00
|
|
|
for (j = 0; j < (svga->monitor->mon_xsize + x_add); j++)
|
2024-02-21 02:25:40 +06:00
|
|
|
p[j] = svga->dpms ? 0 : svga->overscan_color;
|
2022-08-31 19:19:29 -04:00
|
|
|
}
|
2018-04-25 23:51:13 +02:00
|
|
|
}
|
|
|
|
|
|
2023-01-22 16:50:21 +06:00
|
|
|
video_blit_memtoscreen_monitor(x_start, y_start, svga->monitor->mon_xsize + x_add, svga->monitor->mon_ysize + y_add, svga->monitor_index);
|
2020-01-20 05:36:44 +01:00
|
|
|
|
|
|
|
|
if (svga->vertical_linedbl)
|
2022-08-31 19:19:29 -04:00
|
|
|
svga->vertical_linedbl >>= 1;
|
2018-04-25 23:51:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_writeb_linear(uint32_t addr, uint8_t val, void *priv)
|
2018-04-25 23:51:13 +02:00
|
|
|
{
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_t *svga = (svga_t *) priv;
|
2018-04-25 23:51:13 +02:00
|
|
|
|
|
|
|
|
if (!svga->fast) {
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_write_linear(addr, val, priv);
|
2022-08-31 19:19:29 -04:00
|
|
|
return;
|
2018-04-25 23:51:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
addr &= svga->decode_mask;
|
|
|
|
|
if (addr >= svga->vram_max)
|
2022-08-31 19:19:29 -04:00
|
|
|
return;
|
2018-04-25 23:51:13 +02:00
|
|
|
addr &= svga->vram_mask;
|
2023-07-30 19:22:43 -04:00
|
|
|
svga->changedvram[addr >> 12] = svga->monitor->mon_changeframecount;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
svga->vram[addr] = val;
|
2018-04-25 23:51:13 +02:00
|
|
|
}
|
2016-06-26 00:34:39 +02:00
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
void
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_writew_common(uint32_t addr, uint16_t val, uint8_t linear, void *priv)
|
2018-04-25 23:51:13 +02:00
|
|
|
{
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_t *svga = (svga_t *) priv;
|
2018-04-25 23:51:13 +02:00
|
|
|
|
|
|
|
|
if (!svga->fast) {
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_write_common(addr, val, linear, priv);
|
|
|
|
|
svga_write_common(addr + 1, val >> 8, linear, priv);
|
2022-08-31 19:19:29 -04:00
|
|
|
return;
|
2018-04-25 23:51:13 +02:00
|
|
|
}
|
|
|
|
|
|
2023-01-22 16:50:21 +06:00
|
|
|
cycles -= svga->monitor->mon_video_timing_write_w;
|
2018-04-25 23:51:13 +02:00
|
|
|
|
2019-10-01 15:14:51 +02:00
|
|
|
if (!linear) {
|
2024-10-26 21:32:47 +02:00
|
|
|
xga_write_test(addr, val & 0xff, svga);
|
|
|
|
|
xga_write_test(addr + 1, val >> 8, svga);
|
2022-08-31 19:19:29 -04:00
|
|
|
addr = svga_decode_addr(svga, addr, 1);
|
2019-12-04 07:20:58 +01:00
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
if (addr == 0xffffffff)
|
|
|
|
|
return;
|
2019-10-01 15:14:51 +02:00
|
|
|
}
|
|
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
addr &= svga->decode_mask;
|
2022-08-31 19:19:29 -04:00
|
|
|
if (svga->translate_address) {
|
2023-06-09 23:46:54 -04:00
|
|
|
uint32_t addr2 = svga->translate_address(addr, priv);
|
2022-08-31 19:19:29 -04:00
|
|
|
if (addr2 < svga->vram_max) {
|
|
|
|
|
svga->vram[addr2 & svga->vram_mask] = val & 0xff;
|
2023-01-22 16:50:21 +06:00
|
|
|
svga->changedvram[addr2 >> 12] = svga->monitor->mon_changeframecount;
|
2022-08-31 19:19:29 -04:00
|
|
|
}
|
2023-06-09 23:46:54 -04:00
|
|
|
addr2 = svga->translate_address(addr + 1, priv);
|
2022-08-31 19:19:29 -04:00
|
|
|
if (addr2 < svga->vram_max) {
|
|
|
|
|
svga->vram[addr2 & svga->vram_mask] = (val >> 8) & 0xff;
|
2023-01-22 16:50:21 +06:00
|
|
|
svga->changedvram[addr2 >> 12] = svga->monitor->mon_changeframecount;
|
2022-08-31 19:19:29 -04:00
|
|
|
}
|
|
|
|
|
return;
|
2020-05-12 00:37:30 +02:00
|
|
|
}
|
2018-04-25 23:51:13 +02:00
|
|
|
if (addr >= svga->vram_max)
|
2022-08-31 19:19:29 -04:00
|
|
|
return;
|
2018-04-25 23:51:13 +02:00
|
|
|
addr &= svga->vram_mask;
|
Added the IBM 5161 ISA expansion for PC and XT;
Cleaned up the parallel port emulation, added IRQ support, and made enabling/disabling per port;
Added the Award 430NX and the Intel Classic/PCI (Alfredo, 420TX);
Finished the 586MC1;
Added 8087 emulation;
Moved Cyrix 6x86'es to the Dev branch;
Sanitized/cleaned up memregs.c/h and intel.c/h;
Split the chipsets from machines and sanitized Port 92 emulation;
Added support for the 15bpp mode to the Compaq ATI 28800;
Moved the MR 386DX and 486 machines to the Dev branch;
Ported the new dynamic recompiler from PCem, but it remains in Dev branch until after v2.00;
Ported the new timer code from PCem;
Cleaned up the CPU table of unused stuff and better optimized its structure;
Ported the Open-XT and Open-AT from VARCem, the Open-AT is in the Dev branch;
Ported the XT MFM controller rewrite and adding of more controllers (incl. two RLL ones), from VARCem;
Added the AHA-1540A and the BusTek BT-542B;
Moved the Sumo SCSI-AT to the Dev branch;
Minor IDE, FDC, and floppy drive code clean-ups;
Made NCR 5380/53C400-based cards' BIOS address configurable;
Got rid of the legacy romset variable;
Unified (video) buffer and buffer32 into one and make the unified buffer 32-bit;
Added the Amstead PPC512 per PCem patch by John Elliott;
Switched memory mapping granularity from 16k to 4k (less than 1k not possible due to internal pages);
Rewrote the CL-GD 54xx blitter, fixes Win-OS/2 on the 54x6 among other thing;
Added the Image Manager 1024 and Professional Graphics Controller per PCem patch by John Elliott and work done on VARCem;
Added Headland HT-216, GC-205 and Video 7 VGA 1024i emulation based on PCem commit;
Implemented the fuction keys for the Toshiba T1000/T1200/T3100 enhancement;
Amstrad MegaPC does now works correctly with non-internal graphics card;
The SLiRP code no longer casts a packed struct type to a non-packed struct type;
The Xi8088 and PB410a no longer hang on 86Box when PS/2 mouse is not present;
The S3 Virge on BeOS is no longer broken (was broken by build #1591);
OS/2 2.0 build 6.167 now sees key presses again;
Xi8088 now work on CGA again;
86F images converted from either the old or new variants of the HxC MFM format now work correctly;
Hardware interrupts with a vector of 0xFF are now handled correctly;
OPTi 495SX boards no longer incorrectly have 64 MB maximum RAM when 32 MB is correct;
Fixed VNC keyboard input bugs;
Fixed AT RTC periodic interrupt - Chicago 58s / 73f / 73g / 81 MIDI play no longer hangs with the build's own VTD driver;
Fixed mouse polling with internal mice - Amstrad and Olivetti mice now work correctly;
Triones ATAPI DMA driver now correctly reads a file at the end of a CD image with a sectors number not divisible by 4;
Compaq Portable now works with all graphics cards;
Fixed various MDSI Genius bugs;
Added segment limit checks and improved page fault checks for several CPU instructions - Memphis 15xx WINSETUP and Chicago 58s WINDISK.CPL no longer issue a GPF, and some S3 drivers that used to have glitches, now work correctly;
Further improved the 808x emulation, also fixes the noticably choppy sound when using 808x CPU's, also fixes #355;
OS/2 installer no logner locks up on splash screen on PS/2 Model 70 and 80, fixes #400.
Fixed several Amstead bugs, GEM no longer crashes on the Amstrad 1640, fixes #391.
Ported John Elliott's Amstrad fixes and improvement from PCem, and fixed the default language so it's correctly Engliish, fixes #278, fixes #389.
Fixed a minor IDE timing bug, fixes #388.
Fixed Toshiba T1000 RAM issues, fixes #379.
Fixed EGA/(S)VGA overscan border handling, fixes #378;
Got rid of the now long useless IDE channel 2 auto-removal, fixes #370;
Fixed the BIOS files used by the AMSTRAD PC1512, fixes #366;
Ported the Unicode CD image file name fix from VARCem, fixes #365;
Fixed high density floppy disks on the Xi8088, fixes #359;
Fixed some bugs in the Hercules emulation, fixes #346, fixes #358;
Fixed the SCSI hard disk mode sense pages, fixes #356;
Removed the AMI Unknown 386SX because of impossibility to identify the chipset, closes #349;
Fixed bugs in the serial mouse emulation, fixes #344;
Compiled 86Box binaries now include all the required .DLL's, fixes #341;
Made some combo boxes in the Settings dialog slightly wider, fixes #276.
2019-09-20 14:02:30 +02:00
|
|
|
|
2023-01-22 16:50:21 +06:00
|
|
|
svga->changedvram[addr >> 12] = svga->monitor->mon_changeframecount;
|
2022-08-31 19:19:29 -04:00
|
|
|
*(uint16_t *) &svga->vram[addr] = val;
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
void
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_writew(uint32_t addr, uint16_t val, void *priv)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_writew_common(addr, val, 0, priv);
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
void
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_writew_linear(uint32_t addr, uint16_t val, void *priv)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_writew_common(addr, val, 1, priv);
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
void
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_writel_common(uint32_t addr, uint32_t val, uint8_t linear, void *priv)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_t *svga = (svga_t *) priv;
|
2018-04-25 23:51:13 +02:00
|
|
|
|
|
|
|
|
if (!svga->fast) {
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_write_common(addr, val, linear, priv);
|
|
|
|
|
svga_write_common(addr + 1, val >> 8, linear, priv);
|
|
|
|
|
svga_write_common(addr + 2, val >> 16, linear, priv);
|
|
|
|
|
svga_write_common(addr + 3, val >> 24, linear, priv);
|
2022-08-31 19:19:29 -04:00
|
|
|
return;
|
2018-04-25 23:51:13 +02:00
|
|
|
}
|
|
|
|
|
|
2023-01-22 16:50:21 +06:00
|
|
|
cycles -= svga->monitor->mon_video_timing_write_l;
|
2018-04-25 23:51:13 +02:00
|
|
|
|
2019-10-01 15:14:51 +02:00
|
|
|
if (!linear) {
|
2024-10-26 21:32:47 +02:00
|
|
|
xga_write_test(addr, val & 0xff, svga);
|
|
|
|
|
xga_write_test(addr + 1, (val >> 8) & 0xff, svga);
|
|
|
|
|
xga_write_test(addr + 2, (val >> 16) & 0xff, svga);
|
|
|
|
|
xga_write_test(addr + 3, (val >> 24) & 0xff, svga);
|
2022-08-31 19:19:29 -04:00
|
|
|
addr = svga_decode_addr(svga, addr, 1);
|
2019-12-04 07:20:58 +01:00
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
if (addr == 0xffffffff)
|
|
|
|
|
return;
|
2019-10-01 15:14:51 +02:00
|
|
|
}
|
|
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
addr &= svga->decode_mask;
|
2020-05-12 00:37:30 +02:00
|
|
|
if (svga->translate_address) {
|
2023-06-09 23:46:54 -04:00
|
|
|
uint32_t addr2 = svga->translate_address(addr, priv);
|
2022-08-31 19:19:29 -04:00
|
|
|
if (addr2 < svga->vram_max) {
|
|
|
|
|
svga->vram[addr2 & svga->vram_mask] = val & 0xff;
|
2023-01-22 16:50:21 +06:00
|
|
|
svga->changedvram[addr2 >> 12] = svga->monitor->mon_changeframecount;
|
2022-08-31 19:19:29 -04:00
|
|
|
}
|
2023-06-09 23:46:54 -04:00
|
|
|
addr2 = svga->translate_address(addr + 1, priv);
|
2022-08-31 19:19:29 -04:00
|
|
|
if (addr2 < svga->vram_max) {
|
|
|
|
|
svga->vram[addr2 & svga->vram_mask] = (val >> 8) & 0xff;
|
2023-01-22 16:50:21 +06:00
|
|
|
svga->changedvram[addr2 >> 12] = svga->monitor->mon_changeframecount;
|
2022-08-31 19:19:29 -04:00
|
|
|
}
|
2023-06-09 23:46:54 -04:00
|
|
|
addr2 = svga->translate_address(addr + 2, priv);
|
2022-08-31 19:19:29 -04:00
|
|
|
if (addr2 < svga->vram_max) {
|
|
|
|
|
svga->vram[addr2 & svga->vram_mask] = (val >> 16) & 0xff;
|
2023-01-22 16:50:21 +06:00
|
|
|
svga->changedvram[addr2 >> 12] = svga->monitor->mon_changeframecount;
|
2022-08-31 19:19:29 -04:00
|
|
|
}
|
2023-06-09 23:46:54 -04:00
|
|
|
addr2 = svga->translate_address(addr + 3, priv);
|
2022-08-31 19:19:29 -04:00
|
|
|
if (addr2 < svga->vram_max) {
|
|
|
|
|
svga->vram[addr2 & svga->vram_mask] = (val >> 24) & 0xff;
|
2023-01-22 16:50:21 +06:00
|
|
|
svga->changedvram[addr2 >> 12] = svga->monitor->mon_changeframecount;
|
2022-08-31 19:19:29 -04:00
|
|
|
}
|
|
|
|
|
return;
|
2020-05-12 00:37:30 +02:00
|
|
|
}
|
2018-04-25 23:51:13 +02:00
|
|
|
if (addr >= svga->vram_max)
|
2022-08-31 19:19:29 -04:00
|
|
|
return;
|
2024-10-26 21:32:47 +02:00
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
addr &= svga->vram_mask;
|
|
|
|
|
|
2023-01-22 16:50:21 +06:00
|
|
|
svga->changedvram[addr >> 12] = svga->monitor->mon_changeframecount;
|
2022-08-31 19:19:29 -04:00
|
|
|
*(uint32_t *) &svga->vram[addr] = val;
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
void
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_writel(uint32_t addr, uint32_t val, void *priv)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_writel_common(addr, val, 0, priv);
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
void
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_writel_linear(uint32_t addr, uint32_t val, void *priv)
|
2018-03-01 23:05:59 +01:00
|
|
|
{
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_writel_common(addr, val, 1, priv);
|
2018-03-01 23:05:59 +01:00
|
|
|
}
|
|
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
uint8_t
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_readb_linear(uint32_t addr, void *priv)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2023-07-30 19:22:43 -04:00
|
|
|
const svga_t *svga = (svga_t *) priv;
|
2018-04-25 23:51:13 +02:00
|
|
|
|
|
|
|
|
if (!svga->fast)
|
2023-06-09 23:46:54 -04:00
|
|
|
return svga_read_linear(addr, priv);
|
2018-04-25 23:51:13 +02:00
|
|
|
|
|
|
|
|
addr &= svga->decode_mask;
|
|
|
|
|
if (addr >= svga->vram_max)
|
2022-08-31 19:19:29 -04:00
|
|
|
return 0xff;
|
2018-04-25 23:51:13 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
return svga->vram[addr & svga->vram_mask];
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
uint16_t
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_readw_common(uint32_t addr, uint8_t linear, void *priv)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_t *svga = (svga_t *) priv;
|
2018-04-25 23:51:13 +02:00
|
|
|
|
|
|
|
|
if (!svga->fast)
|
2023-06-09 23:46:54 -04:00
|
|
|
return svga_read_common(addr, linear, priv) | (svga_read_common(addr + 1, linear, priv) << 8);
|
2018-04-25 23:51:13 +02:00
|
|
|
|
2023-01-22 16:50:21 +06:00
|
|
|
cycles -= svga->monitor->mon_video_timing_read_w;
|
2018-04-25 23:51:13 +02:00
|
|
|
|
2019-10-20 15:09:38 +02:00
|
|
|
if (!linear) {
|
2022-08-31 19:19:29 -04:00
|
|
|
addr = svga_decode_addr(svga, addr, 0);
|
|
|
|
|
if (addr == 0xffffffff)
|
|
|
|
|
return 0xffff;
|
2019-10-20 15:09:38 +02:00
|
|
|
}
|
|
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
addr &= svga->decode_mask;
|
2020-05-12 00:37:30 +02:00
|
|
|
if (svga->translate_address) {
|
2023-07-30 19:22:43 -04:00
|
|
|
uint8_t val1 = 0xff;
|
|
|
|
|
uint8_t val2 = 0xff;
|
2023-06-09 23:46:54 -04:00
|
|
|
uint32_t addr2 = svga->translate_address(addr, priv);
|
2022-08-31 19:19:29 -04:00
|
|
|
if (addr2 < svga->vram_max)
|
|
|
|
|
val1 = svga->vram[addr2 & svga->vram_mask];
|
2023-06-09 23:46:54 -04:00
|
|
|
addr2 = svga->translate_address(addr + 1, priv);
|
2022-08-31 19:19:29 -04:00
|
|
|
if (addr2 < svga->vram_max)
|
|
|
|
|
val2 = svga->vram[addr2 & svga->vram_mask];
|
|
|
|
|
return (val2 << 8) | val1;
|
2020-05-12 00:37:30 +02:00
|
|
|
}
|
2018-04-25 23:51:13 +02:00
|
|
|
if (addr >= svga->vram_max)
|
2022-08-31 19:19:29 -04:00
|
|
|
return 0xffff;
|
2018-04-25 23:51:13 +02:00
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
return *(uint16_t *) &svga->vram[addr & svga->vram_mask];
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
uint16_t
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_readw(uint32_t addr, void *priv)
|
2018-03-01 23:05:59 +01:00
|
|
|
{
|
2023-06-09 23:46:54 -04:00
|
|
|
return svga_readw_common(addr, 0, priv);
|
2018-03-01 23:05:59 +01:00
|
|
|
}
|
|
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
uint16_t
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_readw_linear(uint32_t addr, void *priv)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2023-06-09 23:46:54 -04:00
|
|
|
return svga_readw_common(addr, 1, priv);
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
uint32_t
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_readl_common(uint32_t addr, uint8_t linear, void *priv)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_t *svga = (svga_t *) priv;
|
2018-04-25 23:51:13 +02:00
|
|
|
|
2023-12-18 13:42:32 +01:00
|
|
|
if (!svga->fast)
|
2023-06-09 23:46:54 -04:00
|
|
|
return svga_read_common(addr, linear, priv) | (svga_read_common(addr + 1, linear, priv) << 8) | (svga_read_common(addr + 2, linear, priv) << 16) | (svga_read_common(addr + 3, linear, priv) << 24);
|
2016-06-26 00:34:39 +02:00
|
|
|
|
2023-01-22 16:50:21 +06:00
|
|
|
cycles -= svga->monitor->mon_video_timing_read_l;
|
2016-06-26 00:34:39 +02:00
|
|
|
|
2019-10-20 15:09:38 +02:00
|
|
|
if (!linear) {
|
2022-08-31 19:19:29 -04:00
|
|
|
addr = svga_decode_addr(svga, addr, 0);
|
|
|
|
|
if (addr == 0xffffffff)
|
|
|
|
|
return 0xffffffff;
|
2019-10-20 15:09:38 +02:00
|
|
|
}
|
|
|
|
|
|
2018-04-25 23:51:13 +02:00
|
|
|
addr &= svga->decode_mask;
|
2020-05-12 00:37:30 +02:00
|
|
|
if (svga->translate_address) {
|
2023-07-30 19:22:43 -04:00
|
|
|
uint8_t val1 = 0xff;
|
|
|
|
|
uint8_t val2 = 0xff;
|
|
|
|
|
uint8_t val3 = 0xff;
|
|
|
|
|
uint8_t val4 = 0xff;
|
2023-06-09 23:46:54 -04:00
|
|
|
uint32_t addr2 = svga->translate_address(addr, priv);
|
2022-08-31 19:19:29 -04:00
|
|
|
if (addr2 < svga->vram_max)
|
|
|
|
|
val1 = svga->vram[addr2 & svga->vram_mask];
|
2023-06-09 23:46:54 -04:00
|
|
|
addr2 = svga->translate_address(addr + 1, priv);
|
2022-08-31 19:19:29 -04:00
|
|
|
if (addr2 < svga->vram_max)
|
|
|
|
|
val2 = svga->vram[addr2 & svga->vram_mask];
|
2023-06-09 23:46:54 -04:00
|
|
|
addr2 = svga->translate_address(addr + 2, priv);
|
2022-08-31 19:19:29 -04:00
|
|
|
if (addr2 < svga->vram_max)
|
|
|
|
|
val3 = svga->vram[addr2 & svga->vram_mask];
|
2023-06-09 23:46:54 -04:00
|
|
|
addr2 = svga->translate_address(addr + 3, priv);
|
2022-08-31 19:19:29 -04:00
|
|
|
if (addr2 < svga->vram_max)
|
|
|
|
|
val4 = svga->vram[addr2 & svga->vram_mask];
|
|
|
|
|
return (val4 << 24) | (val3 << 16) | (val2 << 8) | val1;
|
2020-05-12 00:37:30 +02:00
|
|
|
}
|
2018-04-25 23:51:13 +02:00
|
|
|
if (addr >= svga->vram_max)
|
2022-08-31 19:19:29 -04:00
|
|
|
return 0xffffffff;
|
2018-04-25 23:51:13 +02:00
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
return *(uint32_t *) &svga->vram[addr & svga->vram_mask];
|
2018-04-25 23:51:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
uint32_t
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_readl(uint32_t addr, void *priv)
|
2018-04-25 23:51:13 +02:00
|
|
|
{
|
2023-06-09 23:46:54 -04:00
|
|
|
return svga_readl_common(addr, 0, priv);
|
2018-04-25 23:51:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
uint32_t
|
2023-06-09 23:46:54 -04:00
|
|
|
svga_readl_linear(uint32_t addr, void *priv)
|
2018-04-25 23:51:13 +02:00
|
|
|
{
|
2023-06-09 23:46:54 -04:00
|
|
|
return svga_readl_common(addr, 1, priv);
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|