2022-02-20 02:26:27 -05:00
|
|
|
|
/*
|
2023-01-06 15:36:05 -05:00
|
|
|
|
* 86Box A hypervisor and IBM PC system emulator that specializes in
|
|
|
|
|
|
* running old operating systems and software designed for IBM
|
|
|
|
|
|
* PC systems and compatibles from 1981 through fairly recent
|
|
|
|
|
|
* system designs based on the PCI bus.
|
2017-11-05 20:43:01 -05:00
|
|
|
|
*
|
2023-01-06 15:36:05 -05:00
|
|
|
|
* This file is part of the 86Box distribution.
|
2017-11-05 20:43:01 -05:00
|
|
|
|
*
|
2023-01-06 15:36:05 -05:00
|
|
|
|
* Emulation of the TI CF62011 SVGA chip.
|
2017-11-05 20:43:01 -05:00
|
|
|
|
*
|
2023-01-06 15:36:05 -05:00
|
|
|
|
* This chip was used in several of IBM's later machines, such
|
|
|
|
|
|
* as the PS/1 Model 2121, and a number of PS/2 models. As noted
|
|
|
|
|
|
* in an article on Usenet:
|
2017-11-05 20:43:01 -05:00
|
|
|
|
*
|
2023-01-06 15:36:05 -05:00
|
|
|
|
* "In the early 90s IBM looked for some cheap VGA card to
|
|
|
|
|
|
* substitute the (relatively) expensive XGA-2 adapter for
|
|
|
|
|
|
* *servers*, where the primary purpose is supervision of the
|
|
|
|
|
|
* machine rather than real *work* with it in Hi-Res. It was
|
|
|
|
|
|
* just to supply a base video, where a XGA-2 were a waste of
|
|
|
|
|
|
* potential. They had a contract with TI for some DSPs in
|
|
|
|
|
|
* multimedia already (the MWave for instance is based on
|
|
|
|
|
|
* TI-DSPs as well as many Thinkpad internal chipsets) and TI
|
|
|
|
|
|
* offered them a rather cheap – and inexpensive – chipset
|
|
|
|
|
|
* and combined it with a cheap clock oscillator and an Inmos
|
|
|
|
|
|
* RAMDAC. That chipset was already pretty much outdated at
|
|
|
|
|
|
* that time but IBM decided it would suffice for that low
|
|
|
|
|
|
* end purpose.
|
2017-11-05 20:43:01 -05:00
|
|
|
|
*
|
2023-01-06 15:36:05 -05:00
|
|
|
|
* Driver support was given under DOS and OS/2 only for base
|
|
|
|
|
|
* functions like selection of the vertical refresh and few
|
|
|
|
|
|
* different modes only. Not even the Win 3.x support has
|
|
|
|
|
|
* been finalized. Technically the adapter could do better
|
|
|
|
|
|
* than VGA, but its video BIOS is largely undocumented and
|
|
|
|
|
|
* intentionally crippled down to a few functions."
|
2017-11-05 20:43:01 -05:00
|
|
|
|
*
|
2023-01-06 15:36:05 -05:00
|
|
|
|
* This chip is reportedly the same one as used in the MCA
|
|
|
|
|
|
* IBM SVGA Adapter/A (ID 090EEh), which mostly had faster
|
|
|
|
|
|
* VRAM and RAMDAC. The VESA DOS graphics driver for that
|
|
|
|
|
|
* card can be used: m95svga.exe
|
2017-11-05 20:43:01 -05:00
|
|
|
|
*
|
2023-01-06 15:36:05 -05:00
|
|
|
|
* The controller responds at ports in the range 0x2100-0x210F,
|
|
|
|
|
|
* which are the same as the XGA. It supports up to 1MB of VRAM,
|
|
|
|
|
|
* but we lock it down to 512K. The PS/1 2122 had 256K.
|
2017-11-05 20:43:01 -05:00
|
|
|
|
*
|
2020-03-25 00:46:02 +02:00
|
|
|
|
*
|
2017-11-05 20:43:01 -05:00
|
|
|
|
*
|
2023-01-06 15:36:29 -05:00
|
|
|
|
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
|
2023-01-06 15:36:05 -05:00
|
|
|
|
* Miran Grca, <mgrca8@gmail.com>
|
|
|
|
|
|
* Fred N. van Kempen, <decwiz@yahoo.com>
|
2017-11-05 20:43:01 -05:00
|
|
|
|
*
|
2023-01-06 15:36:05 -05:00
|
|
|
|
* Copyright 2008-2018 Sarah Walker.
|
|
|
|
|
|
* Copyright 2016-2018 Miran Grca.
|
2023-01-06 15:36:29 -05:00
|
|
|
|
* Copyright 2017-2018 Fred N. van Kempen.
|
2017-11-05 20:43:01 -05:00
|
|
|
|
*/
|
|
|
|
|
|
#include <stdio.h>
|
|
|
|
|
|
#include <stdint.h>
|
|
|
|
|
|
#include <stdlib.h>
|
|
|
|
|
|
#include <string.h>
|
|
|
|
|
|
#include <wchar.h>
|
2020-03-29 14:24:42 +02:00
|
|
|
|
#include <86box/86box.h>
|
|
|
|
|
|
#include <86box/io.h>
|
|
|
|
|
|
#include <86box/timer.h>
|
|
|
|
|
|
#include <86box/mem.h>
|
|
|
|
|
|
#include <86box/rom.h>
|
|
|
|
|
|
#include <86box/device.h>
|
|
|
|
|
|
#include <86box/video.h>
|
|
|
|
|
|
#include <86box/vid_svga.h>
|
2017-11-05 20:43:01 -05:00
|
|
|
|
|
|
|
|
|
|
typedef struct {
|
2022-08-31 19:19:29 -04:00
|
|
|
|
svga_t svga;
|
2017-11-05 20:43:01 -05:00
|
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
|
rom_t bios_rom;
|
2017-11-05 20:43:01 -05:00
|
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
|
int enabled;
|
2017-11-08 16:29:54 -05:00
|
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
|
uint32_t vram_size;
|
2017-11-05 20:43:01 -05:00
|
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
|
uint8_t banking;
|
|
|
|
|
|
uint8_t reg_2100;
|
|
|
|
|
|
uint8_t reg_210a;
|
2017-11-05 20:43:01 -05:00
|
|
|
|
} tivga_t;
|
|
|
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
|
static video_timings_t timing_ti_cf62011 = { .type = VIDEO_ISA, .write_b = 6, .write_w = 8, .write_l = 16, .read_b = 6, .read_w = 8, .read_l = 16 };
|
2017-11-05 20:43:01 -05:00
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
|
vid_out(uint16_t addr, uint8_t val, void *priv)
|
|
|
|
|
|
{
|
2022-08-31 19:19:29 -04:00
|
|
|
|
tivga_t *ti = (tivga_t *) priv;
|
|
|
|
|
|
svga_t *svga = &ti->svga;
|
|
|
|
|
|
uint8_t old;
|
2017-11-05 20:43:01 -05:00
|
|
|
|
|
2017-11-08 16:29:54 -05:00
|
|
|
|
#if 0
|
|
|
|
|
|
if (((addr & 0xfff0) == 0x03d0 || (addr & 0xfff0) == 0x03b0) &&
|
2023-08-11 20:32:56 -04:00
|
|
|
|
!(svga->miscout & 1)) addr ^= 0x60;
|
2017-11-08 16:29:54 -05:00
|
|
|
|
#endif
|
2017-11-05 20:43:01 -05:00
|
|
|
|
|
|
|
|
|
|
switch (addr) {
|
2022-08-31 19:19:29 -04:00
|
|
|
|
case 0x0102:
|
|
|
|
|
|
ti->enabled = (val & 0x01);
|
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
|
|
case 0x03d4:
|
|
|
|
|
|
svga->crtcreg = val & 0x3f;
|
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
|
|
case 0x03d5:
|
|
|
|
|
|
if (svga->crtcreg & 0x20)
|
|
|
|
|
|
return;
|
|
|
|
|
|
if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80))
|
|
|
|
|
|
return;
|
|
|
|
|
|
if ((svga->crtcreg == 7) && (svga->crtc[0x11] & 0x80))
|
|
|
|
|
|
val = (svga->crtc[7] & ~0x10) | (val & 0x10);
|
|
|
|
|
|
old = svga->crtc[svga->crtcreg];
|
|
|
|
|
|
svga->crtc[svga->crtcreg] = val;
|
|
|
|
|
|
if (old != val) {
|
|
|
|
|
|
if (svga->crtcreg < 0xe || svga->crtcreg > 0x10) {
|
|
|
|
|
|
svga->fullchange = changeframecount;
|
|
|
|
|
|
svga_recalctimings(svga);
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 0x2100:
|
|
|
|
|
|
ti->reg_2100 = val;
|
|
|
|
|
|
if ((val & 7) < 4)
|
|
|
|
|
|
svga->read_bank = svga->write_bank = 0;
|
|
|
|
|
|
else
|
|
|
|
|
|
svga->read_bank = svga->write_bank = (ti->banking & 0x7) * 0x10000;
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 0x2108:
|
|
|
|
|
|
if ((ti->reg_2100 & 7) >= 4)
|
|
|
|
|
|
svga->read_bank = svga->write_bank = (val & 0x7) * 0x10000;
|
|
|
|
|
|
ti->banking = val;
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 0x210a:
|
|
|
|
|
|
ti->reg_210a = val;
|
|
|
|
|
|
break;
|
2023-08-21 20:25:05 -04:00
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
|
break;
|
2017-11-05 20:43:01 -05:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
svga_out(addr, val, svga);
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static uint8_t
|
|
|
|
|
|
vid_in(uint16_t addr, void *priv)
|
|
|
|
|
|
{
|
2022-08-31 19:19:29 -04:00
|
|
|
|
tivga_t *ti = (tivga_t *) priv;
|
|
|
|
|
|
svga_t *svga = &ti->svga;
|
|
|
|
|
|
uint8_t ret;
|
2017-11-05 20:43:01 -05:00
|
|
|
|
|
2017-11-08 16:29:54 -05:00
|
|
|
|
#if 0
|
|
|
|
|
|
if (((addr & 0xfff0) == 0x03d0 || (addr & 0xfff0) == 0x03b0) &&
|
2023-08-11 20:32:56 -04:00
|
|
|
|
!(svga->miscout & 1)) addr ^= 0x60;
|
2017-11-08 16:29:54 -05:00
|
|
|
|
#endif
|
2017-11-05 20:43:01 -05:00
|
|
|
|
|
|
|
|
|
|
switch (addr) {
|
2022-08-31 19:19:29 -04:00
|
|
|
|
case 0x0100:
|
|
|
|
|
|
ret = 0xfe;
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 0x0101:
|
|
|
|
|
|
ret = 0xe8;
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 0x0102:
|
|
|
|
|
|
ret = ti->enabled;
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 0x03d4:
|
|
|
|
|
|
ret = svga->crtcreg;
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 0x03d5:
|
|
|
|
|
|
if (svga->crtcreg & 0x20)
|
|
|
|
|
|
ret = 0xff;
|
|
|
|
|
|
else
|
|
|
|
|
|
ret = svga->crtc[svga->crtcreg];
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 0x2100:
|
|
|
|
|
|
ret = ti->reg_2100;
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 0x2108:
|
|
|
|
|
|
ret = ti->banking;
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
case 0x210a:
|
|
|
|
|
|
ret = ti->reg_210a;
|
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
|
ret = svga_in(addr, svga);
|
|
|
|
|
|
break;
|
2017-11-05 20:43:01 -05:00
|
|
|
|
}
|
|
|
|
|
|
|
2023-06-01 18:32:25 -04:00
|
|
|
|
return ret;
|
2017-11-05 20:43:01 -05:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
|
vid_speed_changed(void *priv)
|
|
|
|
|
|
{
|
2022-08-31 19:19:29 -04:00
|
|
|
|
tivga_t *ti = (tivga_t *) priv;
|
2017-11-05 20:43:01 -05:00
|
|
|
|
|
|
|
|
|
|
svga_recalctimings(&ti->svga);
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
|
vid_force_redraw(void *priv)
|
|
|
|
|
|
{
|
2022-08-31 19:19:29 -04:00
|
|
|
|
tivga_t *ti = (tivga_t *) priv;
|
2017-11-05 20:43:01 -05:00
|
|
|
|
|
|
|
|
|
|
ti->svga.fullchange = changeframecount;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
|
vid_close(void *priv)
|
|
|
|
|
|
{
|
2022-08-31 19:19:29 -04:00
|
|
|
|
tivga_t *ti = (tivga_t *) priv;
|
2017-11-05 20:43:01 -05:00
|
|
|
|
|
|
|
|
|
|
svga_close(&ti->svga);
|
|
|
|
|
|
|
|
|
|
|
|
free(ti);
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void *
|
2018-03-19 01:02:04 +01:00
|
|
|
|
vid_init(const device_t *info)
|
2017-11-05 20:43:01 -05:00
|
|
|
|
{
|
|
|
|
|
|
tivga_t *ti;
|
|
|
|
|
|
|
|
|
|
|
|
/* Allocate control block and initialize. */
|
2022-08-31 19:19:29 -04:00
|
|
|
|
ti = (tivga_t *) malloc(sizeof(tivga_t));
|
2017-11-05 20:43:01 -05:00
|
|
|
|
memset(ti, 0x00, sizeof(tivga_t));
|
|
|
|
|
|
|
|
|
|
|
|
/* Set amount of VRAM in KB. */
|
|
|
|
|
|
if (info->local == 0)
|
2022-08-31 19:19:29 -04:00
|
|
|
|
ti->vram_size = device_get_config_int("vram_size");
|
2018-09-19 20:13:32 +02:00
|
|
|
|
else
|
2022-08-31 19:19:29 -04:00
|
|
|
|
ti->vram_size = info->local;
|
2017-11-05 20:43:01 -05:00
|
|
|
|
|
2018-09-19 20:13:32 +02:00
|
|
|
|
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_ti_cf62011);
|
|
|
|
|
|
|
2020-05-06 00:23:07 +02:00
|
|
|
|
svga_init(info, &ti->svga, ti,
|
2022-08-31 19:19:29 -04:00
|
|
|
|
ti->vram_size << 10,
|
|
|
|
|
|
NULL, vid_in, vid_out, NULL, NULL);
|
2017-11-05 20:43:01 -05:00
|
|
|
|
|
2017-11-08 16:29:54 -05:00
|
|
|
|
io_sethandler(0x0100, 2, vid_in, NULL, NULL, NULL, NULL, NULL, ti);
|
2017-11-05 20:43:01 -05:00
|
|
|
|
io_sethandler(0x03c0, 32, vid_in, NULL, NULL, vid_out, NULL, NULL, ti);
|
|
|
|
|
|
io_sethandler(0x2100, 16, vid_in, NULL, NULL, vid_out, NULL, NULL, ti);
|
|
|
|
|
|
|
2022-08-31 19:19:29 -04:00
|
|
|
|
ti->svga.bpp = 8;
|
2017-11-05 20:43:01 -05:00
|
|
|
|
ti->svga.miscout = 1;
|
|
|
|
|
|
|
2023-06-01 18:32:25 -04:00
|
|
|
|
return ti;
|
2017-11-05 20:43:01 -05:00
|
|
|
|
}
|
|
|
|
|
|
|
2018-03-19 01:02:04 +01:00
|
|
|
|
const device_t ibm_ps1_2121_device = {
|
2022-08-31 19:19:29 -04:00
|
|
|
|
.name = "IBM PS/1 Model 2121 SVGA",
|
2022-03-13 21:43:45 -04:00
|
|
|
|
.internal_name = "ibm_ps1_2121",
|
2022-08-31 19:19:29 -04:00
|
|
|
|
.flags = DEVICE_ISA,
|
|
|
|
|
|
.local = 512,
|
|
|
|
|
|
.init = vid_init,
|
|
|
|
|
|
.close = vid_close,
|
|
|
|
|
|
.reset = NULL,
|
2022-03-13 21:43:45 -04:00
|
|
|
|
{ .available = NULL },
|
|
|
|
|
|
.speed_changed = vid_speed_changed,
|
2022-08-31 19:19:29 -04:00
|
|
|
|
.force_redraw = vid_force_redraw,
|
|
|
|
|
|
.config = NULL
|
2017-11-05 20:43:01 -05:00
|
|
|
|
};
|