395 lines
14 KiB
C
395 lines
14 KiB
C
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static int opMOV_w_seg_a16(uint32_t fetchdat)
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{
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fetch_ea_16(fetchdat);
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switch (rmdat & 0x38)
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{
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case 0x00: /*ES*/
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seteaw(ES);
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break;
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case 0x08: /*CS*/
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seteaw(CS);
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break;
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case 0x18: /*DS*/
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seteaw(DS);
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break;
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case 0x10: /*SS*/
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seteaw(SS);
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break;
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case 0x20: /*FS*/
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seteaw(FS);
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break;
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case 0x28: /*GS*/
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seteaw(GS);
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break;
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}
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CLOCK_CYCLES((mod == 3) ? 2 : 3);
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return abrt;
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}
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static int opMOV_w_seg_a32(uint32_t fetchdat)
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{
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fetch_ea_32(fetchdat);
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switch (rmdat & 0x38)
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{
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case 0x00: /*ES*/
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seteaw(ES);
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break;
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case 0x08: /*CS*/
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seteaw(CS);
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break;
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case 0x18: /*DS*/
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seteaw(DS);
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break;
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case 0x10: /*SS*/
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seteaw(SS);
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break;
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case 0x20: /*FS*/
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seteaw(FS);
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break;
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case 0x28: /*GS*/
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seteaw(GS);
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break;
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}
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CLOCK_CYCLES((mod == 3) ? 2 : 3);
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return abrt;
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}
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static int opMOV_l_seg_a16(uint32_t fetchdat)
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{
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fetch_ea_16(fetchdat);
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switch (rmdat & 0x38)
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{
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case 0x00: /*ES*/
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if (mod == 3) cpu_state.regs[rm].l = ES;
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else seteaw(ES);
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break;
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case 0x08: /*CS*/
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if (mod == 3) cpu_state.regs[rm].l = CS;
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else seteaw(CS);
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break;
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case 0x18: /*DS*/
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if (mod == 3) cpu_state.regs[rm].l = DS;
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else seteaw(DS);
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break;
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case 0x10: /*SS*/
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if (mod == 3) cpu_state.regs[rm].l = SS;
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else seteaw(SS);
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break;
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case 0x20: /*FS*/
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if (mod == 3) cpu_state.regs[rm].l = FS;
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else seteaw(FS);
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break;
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case 0x28: /*GS*/
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if (mod == 3) cpu_state.regs[rm].l = GS;
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else seteaw(GS);
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break;
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}
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CLOCK_CYCLES((mod == 3) ? 2 : 3);
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return abrt;
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}
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static int opMOV_l_seg_a32(uint32_t fetchdat)
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{
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fetch_ea_32(fetchdat);
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switch (rmdat & 0x38)
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{
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case 0x00: /*ES*/
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if (mod == 3) cpu_state.regs[rm].l = ES;
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else seteaw(ES);
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break;
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case 0x08: /*CS*/
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if (mod == 3) cpu_state.regs[rm].l = CS;
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else seteaw(CS);
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break;
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case 0x18: /*DS*/
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if (mod == 3) cpu_state.regs[rm].l = DS;
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else seteaw(DS);
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break;
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case 0x10: /*SS*/
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if (mod == 3) cpu_state.regs[rm].l = SS;
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else seteaw(SS);
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break;
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case 0x20: /*FS*/
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if (mod == 3) cpu_state.regs[rm].l = FS;
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else seteaw(FS);
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break;
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case 0x28: /*GS*/
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if (mod == 3) cpu_state.regs[rm].l = GS;
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else seteaw(GS);
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break;
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}
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CLOCK_CYCLES((mod == 3) ? 2 : 3);
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return abrt;
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}
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static int opMOV_seg_w_a16(uint32_t fetchdat)
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{
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uint16_t new_seg;
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fetch_ea_16(fetchdat);
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new_seg=geteaw(); if (abrt) return 1;
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switch (rmdat & 0x38)
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{
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case 0x00: /*ES*/
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loadseg(new_seg, &_es);
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break;
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case 0x18: /*DS*/
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loadseg(new_seg, &_ds);
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break;
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case 0x10: /*SS*/
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loadseg(new_seg, &_ss);
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if (abrt) return 1;
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oldpc = cpu_state.pc;
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op32 = use32;
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ssegs = 0;
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ea_seg = &_ds;
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fetchdat = fastreadl(cs + cpu_state.pc);
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cpu_state.pc++;
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if (abrt) return 1;
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x86_opcodes[(fetchdat & 0xff) | op32](fetchdat >> 8);
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return 1;
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case 0x20: /*FS*/
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loadseg(new_seg, &_fs);
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break;
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case 0x28: /*GS*/
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loadseg(new_seg, &_gs);
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break;
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}
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CLOCK_CYCLES((mod == 3) ? 2 : 5);
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return abrt;
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}
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static int opMOV_seg_w_a32(uint32_t fetchdat)
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{
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uint16_t new_seg;
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fetch_ea_32(fetchdat);
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new_seg=geteaw(); if (abrt) return 1;
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switch (rmdat & 0x38)
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{
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case 0x00: /*ES*/
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loadseg(new_seg, &_es);
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break;
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case 0x18: /*DS*/
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loadseg(new_seg, &_ds);
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break;
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case 0x10: /*SS*/
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loadseg(new_seg, &_ss);
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if (abrt) return 1;
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oldpc = cpu_state.pc;
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op32 = use32;
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ssegs = 0;
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ea_seg = &_ds;
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fetchdat = fastreadl(cs + cpu_state.pc);
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cpu_state.pc++;
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if (abrt) return 1;
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x86_opcodes[(fetchdat & 0xff) | op32](fetchdat >> 8);
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return 1;
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case 0x20: /*FS*/
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loadseg(new_seg, &_fs);
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break;
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case 0x28: /*GS*/
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loadseg(new_seg, &_gs);
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break;
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}
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CLOCK_CYCLES((mod == 3) ? 2 : 5);
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return abrt;
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}
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static int opLDS_w_a16(uint32_t fetchdat)
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{
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uint16_t addr, seg;
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fetch_ea_16(fetchdat);
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ILLEGAL_ON(mod == 3);
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addr = readmemw(easeg, eaaddr);
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seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
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loadseg(seg, &_ds); if (abrt) return 1;
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cpu_state.regs[reg].w = addr;
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CLOCK_CYCLES(7);
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return 0;
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}
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static int opLDS_w_a32(uint32_t fetchdat)
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{
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uint16_t addr, seg;
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fetch_ea_32(fetchdat);
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ILLEGAL_ON(mod == 3);
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addr = readmemw(easeg, eaaddr);
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seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
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loadseg(seg, &_ds); if (abrt) return 1;
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cpu_state.regs[reg].w = addr;
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CLOCK_CYCLES(7);
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return 0;
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}
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static int opLDS_l_a16(uint32_t fetchdat)
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{
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uint32_t addr;
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uint16_t seg;
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fetch_ea_16(fetchdat);
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ILLEGAL_ON(mod == 3);
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addr = readmeml(easeg, eaaddr);
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seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1;
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loadseg(seg, &_ds); if (abrt) return 1;
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cpu_state.regs[reg].l = addr;
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CLOCK_CYCLES(7);
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return 0;
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}
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static int opLDS_l_a32(uint32_t fetchdat)
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{
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uint32_t addr;
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uint16_t seg;
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fetch_ea_32(fetchdat);
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ILLEGAL_ON(mod == 3);
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addr = readmeml(easeg, eaaddr);
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seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1;
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loadseg(seg, &_ds); if (abrt) return 1;
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cpu_state.regs[reg].l = addr;
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CLOCK_CYCLES(7);
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return 0;
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}
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static int opLSS_w_a16(uint32_t fetchdat)
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{
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uint16_t addr, seg;
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fetch_ea_16(fetchdat);
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ILLEGAL_ON(mod == 3);
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addr = readmemw(easeg, eaaddr);
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seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
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loadseg(seg, &_ss); if (abrt) return 1;
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cpu_state.regs[reg].w = addr;
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CLOCK_CYCLES(7);
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return 1;
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}
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static int opLSS_w_a32(uint32_t fetchdat)
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{
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uint16_t addr, seg;
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fetch_ea_32(fetchdat);
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ILLEGAL_ON(mod == 3);
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addr = readmemw(easeg, eaaddr);
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seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1;
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loadseg(seg, &_ss); if (abrt) return 1;
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cpu_state.regs[reg].w = addr;
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CLOCK_CYCLES(7);
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return 1;
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}
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static int opLSS_l_a16(uint32_t fetchdat)
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{
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uint32_t addr;
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uint16_t seg;
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fetch_ea_16(fetchdat);
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ILLEGAL_ON(mod == 3);
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addr = readmeml(easeg, eaaddr);
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seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1;
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loadseg(seg, &_ss); if (abrt) return 1;
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cpu_state.regs[reg].l = addr;
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CLOCK_CYCLES(7);
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return 1;
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}
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static int opLSS_l_a32(uint32_t fetchdat)
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{
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uint32_t addr;
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uint16_t seg;
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fetch_ea_32(fetchdat);
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ILLEGAL_ON(mod == 3);
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addr = readmeml(easeg, eaaddr);
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seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1;
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loadseg(seg, &_ss); if (abrt) return 1;
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cpu_state.regs[reg].l = addr;
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CLOCK_CYCLES(7);
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return 1;
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}
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#define opLsel(name, sel) \
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static int opL ## name ## _w_a16(uint32_t fetchdat) \
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{ \
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uint16_t addr, seg; \
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\
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fetch_ea_16(fetchdat); \
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ILLEGAL_ON(mod == 3); \
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addr = readmemw(easeg, eaaddr); \
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seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1; \
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loadseg(seg, &sel); if (abrt) return 1; \
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cpu_state.regs[reg].w = addr; \
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\
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CLOCK_CYCLES(7); \
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return 0; \
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} \
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\
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static int opL ## name ## _w_a32(uint32_t fetchdat) \
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{ \
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uint16_t addr, seg; \
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\
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fetch_ea_32(fetchdat); \
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ILLEGAL_ON(mod == 3); \
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addr = readmemw(easeg, eaaddr); \
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seg = readmemw(easeg, eaaddr + 2); if (abrt) return 1; \
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loadseg(seg, &sel); if (abrt) return 1; \
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cpu_state.regs[reg].w = addr; \
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\
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CLOCK_CYCLES(7); \
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return 0; \
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} \
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\
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static int opL ## name ## _l_a16(uint32_t fetchdat) \
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{ \
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uint32_t addr; \
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uint16_t seg; \
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\
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fetch_ea_16(fetchdat); \
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ILLEGAL_ON(mod == 3); \
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addr = readmeml(easeg, eaaddr); \
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seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1; \
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loadseg(seg, &sel); if (abrt) return 1; \
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cpu_state.regs[reg].l = addr; \
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\
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CLOCK_CYCLES(7); \
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return 0; \
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} \
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\
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static int opL ## name ## _l_a32(uint32_t fetchdat) \
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{ \
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uint32_t addr; \
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uint16_t seg; \
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\
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fetch_ea_32(fetchdat); \
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|
|
ILLEGAL_ON(mod == 3); \
|
||
|
|
addr = readmeml(easeg, eaaddr); \
|
||
|
|
seg = readmemw(easeg, eaaddr + 4); if (abrt) return 1; \
|
||
|
|
loadseg(seg, &sel); if (abrt) return 1; \
|
||
|
|
cpu_state.regs[reg].l = addr; \
|
||
|
|
\
|
||
|
|
CLOCK_CYCLES(7); \
|
||
|
|
return 0; \
|
||
|
|
}
|
||
|
|
|
||
|
|
opLsel(ES, _es)
|
||
|
|
opLsel(FS, _fs)
|
||
|
|
opLsel(GS, _gs)
|