398 lines
13 KiB
C++
398 lines
13 KiB
C++
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/*
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* This file is part of libsidplayfp, a SID player engine.
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*
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* Copyright 2011-2023 Leandro Nini <drfiemost@users.sourceforge.net>
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* Copyright 2007-2010 Antti Lankila
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* Copyright 2004 Dag Lem <resid@nimrod.no>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#define WAVEFORMGENERATOR_CPP
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#include "WaveformGenerator.h"
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namespace reSIDfp
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{
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/**
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* Number of cycles after which the waveform output fades to 0 when setting
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* the waveform register to 0.
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* Values measured on warm chips (6581R3/R4 and 8580R5)
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* checking OSC3.
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* Times vary wildly with temperature and may differ
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* from chip to chip so the numbers here represent
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* only the big difference between the old and new models.
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*
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* See [VICE Bug #290](http://sourceforge.net/p/vice-emu/bugs/290/)
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* and [VICE Bug #1128](http://sourceforge.net/p/vice-emu/bugs/1128/)
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*/
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// ~95ms
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const unsigned int FLOATING_OUTPUT_TTL_6581R3 = 54000;
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const unsigned int FLOATING_OUTPUT_FADE_6581R3 = 1400;
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// ~1s
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const unsigned int FLOATING_OUTPUT_TTL_6581R4 = 1000000;
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// ~1s
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const unsigned int FLOATING_OUTPUT_TTL_8580R5 = 800000;
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const unsigned int FLOATING_OUTPUT_FADE_8580R5 = 50000;
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/**
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* Number of cycles after which the shift register is reset
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* when the test bit is set.
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* Values measured on warm chips (6581R3/R4 and 8580R5)
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* checking OSC3.
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* Times vary wildly with temperature and may differ
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* from chip to chip so the numbers here represent
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* only the big difference between the old and new models.
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*/
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// ~210ms
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const unsigned int SHIFT_REGISTER_RESET_6581R3 = 50000;
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const unsigned int SHIFT_REGISTER_FADE_6581R3 = 15000;
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// ~2.15s
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const unsigned int SHIFT_REGISTER_RESET_6581R4 = 2150000;
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// ~2.8s
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const unsigned int SHIFT_REGISTER_RESET_8580R5 = 986000;
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const unsigned int SHIFT_REGISTER_FADE_8580R5 = 314300;
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const unsigned int shift_mask =
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~(
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(1u << 2) | // Bit 20
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(1u << 4) | // Bit 18
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(1u << 8) | // Bit 14
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(1u << 11) | // Bit 11
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(1u << 13) | // Bit 9
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(1u << 17) | // Bit 5
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(1u << 20) | // Bit 2
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(1u << 22) // Bit 0
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);
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/*
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* This is what happens when the lfsr is clocked:
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*
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* cycle 0: bit 19 of the accumulator goes from low to high, the noise register acts normally,
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* the output may pulldown a bit;
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*
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* cycle 1: first phase of the shift, the bits are interconnected and the output of each bit
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* is latched into the following. The output may overwrite the latched value.
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*
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* cycle 2: second phase of the shift, the latched value becomes active in the first
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* half of the clock and from the second half the register returns to normal operation.
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*
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* When the test or reset lines are active the first phase is executed at every cyle
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* until the signal is released triggering the second phase.
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*
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* | | bit n | bit n+1
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* | bit19 | latch output | latch output
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* -----+-------+--------------+--------------
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* phi1 | 0 | A <-> A | B <-> B
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* phi2 | 0 | A <-> A | B <-> B
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* -----+-------+--------------+--------------
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* phi1 | 1 | A <-> A | B <-> B <- bit19 raises
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* phi2 | 1 | A <-> A | B <-> B
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* -----+-------+--------------+--------------
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* phi1 | 1 | X A --|-> A B <- shift phase 1
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* phi2 | 1 | X A --|-> A B
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* -----+-------+--------------+--------------
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* phi1 | 1 | X --> X | A --> A <- shift phase 2
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* phi2 | 1 | X <-> X | A <-> A
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*/
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inline bool do_writeback(unsigned int waveform_old, unsigned int waveform_new, bool is6581)
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{
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// no writeback without combined waveforms
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if (waveform_new <= 8)
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return false;
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if (waveform_old <= 8)
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return false; // fixes SID/noisewriteback/noise_writeback_test2-{old,new}
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// What's happening here?
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if (is6581 &&
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((((waveform_old & 0x3) == 0x1) && ((waveform_new & 0x3) == 0x2))
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|| (((waveform_old & 0x3) == 0x2) && ((waveform_new & 0x3) == 0x1))))
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{
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// fixes
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// noise_writeback_check_9_to_A_old
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// noise_writeback_check_9_to_E_old
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// noise_writeback_check_A_to_9_old
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// noise_writeback_check_A_to_D_old
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// noise_writeback_check_D_to_A_old
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// noise_writeback_check_E_to_9_old
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return false;
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}
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if (waveform_old == 0xc)
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{
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// fixes
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// noise_writeback_check_C_to_A_new
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return false;
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}
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if (waveform_new == 0xc)
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{
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// fixes
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// noise_writeback_check_9_to_C_old
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// noise_writeback_check_A_to_C_old
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return false;
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}
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// ok do the writeback
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return true;
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}
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inline unsigned int get_noise_writeback(unsigned int waveform_output)
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{
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return
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((waveform_output & (1u << 11)) >> 9) | // Bit 11 -> bit 20
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((waveform_output & (1u << 10)) >> 6) | // Bit 10 -> bit 18
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((waveform_output & (1u << 9)) >> 1) | // Bit 9 -> bit 14
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((waveform_output & (1u << 8)) << 3) | // Bit 8 -> bit 11
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((waveform_output & (1u << 7)) << 6) | // Bit 7 -> bit 9
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((waveform_output & (1u << 6)) << 11) | // Bit 6 -> bit 5
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((waveform_output & (1u << 5)) << 15) | // Bit 5 -> bit 2
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((waveform_output & (1u << 4)) << 18); // Bit 4 -> bit 0
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}
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/*
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* Perform the actual shifting, moving the latched value into following bits.
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* The XORing for bit0 is done in this cycle using the test bit latched during
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* the previous phi2 cycle.
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*/
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void WaveformGenerator::shift_phase2(unsigned int waveform_old, unsigned int waveform_new)
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{
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if (do_writeback(waveform_old, waveform_new, is6581))
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{
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// if noise is combined with another waveform the output drives the SR bits
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shift_latch = (shift_register & shift_mask) | get_noise_writeback(waveform_output);
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}
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// bit0 = (bit22 | test | reset) ^ bit17 = 1 ^ bit17 = ~bit17
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const unsigned int bit22 = ((test_or_reset ? 1 : 0) | shift_latch) << 22;
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const unsigned int bit0 = (bit22 ^ (shift_latch << 17)) & (1 << 22);
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shift_register = (shift_latch >> 1) | bit0;
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#ifdef TRACE
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std::cout << std::hex << shift_latch << " -> " << shift_register << std::endl;
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#endif
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set_noise_output();
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}
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void WaveformGenerator::write_shift_register()
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{
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if (unlikely(waveform > 0x8))
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{
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if (waveform == 0xc)
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return; // breaks SID/wf12nsr/wf12nsr
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// Write changes to the shift register output caused by combined waveforms
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// back into the shift register.
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if (likely(shift_pipeline != 1) && !test)
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{
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#ifdef TRACE
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std::cout << "write shift_register" << std::endl;
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#endif
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// the output pulls down the SR bits
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shift_register = shift_register & (shift_mask | get_noise_writeback(waveform_output));
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noise_output &= waveform_output;
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}
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else
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{
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#ifdef TRACE
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std::cout << "write shift_latch" << std::endl;
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#endif
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// shift phase 1: the output drives the SR bits
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noise_output = waveform_output;
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}
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set_no_noise_or_noise_output();
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}
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}
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void WaveformGenerator::set_noise_output()
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{
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noise_output =
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((shift_register & (1u << 2)) << 9) | // Bit 20 -> bit 11
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((shift_register & (1u << 4)) << 6) | // Bit 18 -> bit 10
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((shift_register & (1u << 8)) << 1) | // Bit 14 -> bit 9
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((shift_register & (1u << 11)) >> 3) | // Bit 11 -> bit 8
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((shift_register & (1u << 13)) >> 6) | // Bit 9 -> bit 7
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((shift_register & (1u << 17)) >> 11) | // Bit 5 -> bit 6
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((shift_register & (1u << 20)) >> 15) | // Bit 2 -> bit 5
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((shift_register & (1u << 22)) >> 18); // Bit 0 -> bit 4
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set_no_noise_or_noise_output();
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}
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void WaveformGenerator::setWaveformModels(matrix_t* models)
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{
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model_wave = models;
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}
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void WaveformGenerator::setPulldownModels(matrix_t* models)
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{
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model_pulldown = models;
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}
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void WaveformGenerator::synchronize(WaveformGenerator* syncDest, const WaveformGenerator* syncSource) const
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{
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// A special case occurs when a sync source is synced itself on the same
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// cycle as when its MSB is set high. In this case the destination will
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// not be synced. This has been verified by sampling OSC3.
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if (unlikely(msb_rising) && syncDest->sync && !(sync && syncSource->msb_rising))
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{
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syncDest->accumulator = 0;
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}
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}
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void WaveformGenerator::set_no_noise_or_noise_output()
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{
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no_noise_or_noise_output = no_noise | noise_output;
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}
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void WaveformGenerator::writeCONTROL_REG(unsigned char control)
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{
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const unsigned int waveform_prev = waveform;
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const bool test_prev = test;
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waveform = (control >> 4) & 0x0f;
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test = (control & 0x08) != 0;
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sync = (control & 0x02) != 0;
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// Substitution of accumulator MSB when sawtooth = 0, ring_mod = 1.
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ring_msb_mask = ((~control >> 5) & (control >> 2) & 0x1) << 23;
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if (waveform != waveform_prev)
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{
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// Set up waveform tables
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wave = (*model_wave)[waveform & 0x3];
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// We assume tha combinations including noise
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// behave the same as without
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switch (waveform & 0x7)
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{
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case 3:
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pulldown = (*model_pulldown)[0];
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break;
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case 4:
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pulldown = (waveform & 0x8) ? (*model_pulldown)[4] : nullptr;
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break;
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case 5:
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pulldown = (*model_pulldown)[1];
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break;
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case 6:
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pulldown = (*model_pulldown)[2];
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break;
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case 7:
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pulldown = (*model_pulldown)[3];
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break;
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default:
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pulldown = nullptr;
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break;
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}
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// no_noise and no_pulse are used in set_waveform_output() as bitmasks to
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// only let the noise or pulse influence the output when the noise or pulse
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// waveforms are selected.
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no_noise = (waveform & 0x8) != 0 ? 0x000 : 0xfff;
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set_no_noise_or_noise_output();
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no_pulse = (waveform & 0x4) != 0 ? 0x000 : 0xfff;
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if (waveform == 0)
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{
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// Change to floating DAC input.
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// Reset fading time for floating DAC input.
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floating_output_ttl = is6581 ? FLOATING_OUTPUT_TTL_6581R3 : FLOATING_OUTPUT_TTL_8580R5;
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}
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}
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if (test != test_prev)
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{
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if (test)
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{
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// Reset accumulator.
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accumulator = 0;
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// Flush shift pipeline.
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shift_pipeline = 0;
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// Latch the shift register value.
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shift_latch = shift_register;
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#ifdef TRACE
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std::cout << "shift phase 1 (test)" << std::endl;
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#endif
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// Set reset time for shift register.
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shift_register_reset = is6581 ? SHIFT_REGISTER_RESET_6581R3 : SHIFT_REGISTER_RESET_8580R5;
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}
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else
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{
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// When the test bit is falling, the second phase of the shift is
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// completed by enabling SRAM write.
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shift_phase2(waveform_prev, waveform);
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}
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}
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}
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void WaveformGenerator::waveBitfade()
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{
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waveform_output &= waveform_output >> 1;
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osc3 = waveform_output;
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if (waveform_output != 0)
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floating_output_ttl = is6581 ? FLOATING_OUTPUT_FADE_6581R3 : FLOATING_OUTPUT_FADE_8580R5;
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}
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void WaveformGenerator::shiftregBitfade()
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{
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shift_register |= shift_register >> 1;
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shift_register |= 0x400000;
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if (shift_register != 0x7fffff)
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||
|
|
shift_register_reset = is6581 ? SHIFT_REGISTER_FADE_6581R3 : SHIFT_REGISTER_FADE_8580R5;
|
||
|
|
}
|
||
|
|
|
||
|
|
void WaveformGenerator::reset()
|
||
|
|
{
|
||
|
|
// accumulator is not changed on reset
|
||
|
|
freq = 0;
|
||
|
|
pw = 0;
|
||
|
|
|
||
|
|
msb_rising = false;
|
||
|
|
|
||
|
|
waveform = 0;
|
||
|
|
osc3 = 0;
|
||
|
|
|
||
|
|
test = false;
|
||
|
|
sync = false;
|
||
|
|
|
||
|
|
wave = model_wave ? (*model_wave)[0] : nullptr;
|
||
|
|
pulldown = nullptr;
|
||
|
|
|
||
|
|
ring_msb_mask = 0;
|
||
|
|
no_noise = 0xfff;
|
||
|
|
no_pulse = 0xfff;
|
||
|
|
pulse_output = 0xfff;
|
||
|
|
|
||
|
|
shift_register_reset = 0;
|
||
|
|
shift_register = 0x7fffff;
|
||
|
|
// when reset is released the shift register is clocked once
|
||
|
|
// so the lower bit is zeroed out
|
||
|
|
// bit0 = (bit22 | test) ^ bit17 = 1 ^ 1 = 0
|
||
|
|
test_or_reset = true;
|
||
|
|
shift_latch = shift_register;
|
||
|
|
shift_phase2(0, 0);
|
||
|
|
|
||
|
|
shift_pipeline = 0;
|
||
|
|
|
||
|
|
waveform_output = 0;
|
||
|
|
floating_output_ttl = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
} // namespace reSIDfp
|