2020-03-25 21:35:35 -03:00
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/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Emulation of SPD (Serial Presence Detect) devices.
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*
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2020-04-26 19:24:15 -03:00
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*
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2020-03-25 21:35:35 -03:00
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*
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* Authors: RichardG, <richardg867@gmail.com>
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*
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* Copyright 2020 RichardG.
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*/
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#include <stdarg.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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2020-03-29 14:24:42 +02:00
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#include <86box/86box.h>
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#include <86box/device.h>
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#include <86box/smbus.h>
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#include <86box/spd.h>
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2020-06-26 13:26:42 +02:00
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#include <86box/version.h>
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2020-06-26 21:03:46 -03:00
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#include <86box/machine.h>
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2020-03-25 21:35:35 -03:00
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2020-05-16 20:32:28 -03:00
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#define MIN(a, b) ((a) < (b) ? (a) : (b))
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#define SPD_ROLLUP(x) ((x) >= 16 ? ((x) - 15) : (x))
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2020-03-25 21:35:35 -03:00
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2020-06-26 18:05:27 -03:00
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int spd_present = 0;
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2020-05-16 20:32:28 -03:00
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spd_t *spd_devices[SPD_MAX_SLOTS];
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2020-03-25 21:35:35 -03:00
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uint8_t spd_data[SPD_MAX_SLOTS][SPD_DATA_SIZE];
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static uint8_t spd_read_byte(uint8_t addr, void *priv);
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static uint8_t spd_read_byte_cmd(uint8_t addr, uint8_t cmd, void *priv);
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static void spd_write_byte(uint8_t addr, uint8_t val, void *priv);
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2020-06-26 22:15:36 -03:00
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2020-03-25 21:35:35 -03:00
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#ifdef ENABLE_SPD_LOG
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int spd_do_log = ENABLE_SPD_LOG;
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static void
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spd_log(const char *fmt, ...)
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{
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va_list ap;
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if (spd_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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#define spd_log(fmt, ...)
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#endif
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uint8_t
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spd_read_byte(uint8_t addr, void *priv)
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{
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spd_t *dev = (spd_t *) priv;
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return spd_read_byte_cmd(addr, dev->addr_register, priv);
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}
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uint8_t
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spd_read_byte_cmd(uint8_t addr, uint8_t cmd, void *priv)
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{
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spd_t *dev = (spd_t *) priv;
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uint8_t ret = *(spd_data[dev->slot] + cmd);
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2020-05-18 23:00:05 -03:00
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spd_log("SPD: read(%02X, %02X) = %02X\n", addr, cmd, ret);
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2020-03-25 21:35:35 -03:00
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return ret;
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}
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2020-05-16 20:32:28 -03:00
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uint16_t
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spd_read_word_cmd(uint8_t addr, uint8_t cmd, void *priv)
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{
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return (spd_read_byte_cmd(addr, cmd + 1, priv) << 8) | spd_read_byte_cmd(addr, cmd, priv);
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}
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uint8_t
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spd_read_block_cmd(uint8_t addr, uint8_t cmd, uint8_t *data, uint8_t len, void *priv)
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{
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uint8_t read = 0;
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for (uint8_t i = cmd; i < len && i < SPD_DATA_SIZE; i++) {
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data[read++] = spd_read_byte_cmd(addr, i, priv);
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}
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return read;
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}
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2020-03-25 21:35:35 -03:00
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void
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spd_write_byte(uint8_t addr, uint8_t val, void *priv)
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{
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spd_t *dev = (spd_t *) priv;
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dev->addr_register = val;
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}
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static void
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spd_close(void *priv)
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{
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spd_t *dev = (spd_t *) priv;
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spd_log("SPD: closing slot %d (SMBus %02Xh)\n", dev->slot, SPD_BASE_ADDR + dev->slot);
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smbus_removehandler(SPD_BASE_ADDR + dev->slot, 1,
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2020-05-16 20:32:28 -03:00
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spd_read_byte, spd_read_byte_cmd, spd_read_word_cmd, spd_read_block_cmd,
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2020-03-25 21:35:35 -03:00
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spd_write_byte, NULL, NULL, NULL,
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dev);
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2020-06-26 18:24:15 -03:00
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spd_present = 0;
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2020-03-25 21:35:35 -03:00
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free(dev);
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}
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static void *
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spd_init(const device_t *info)
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{
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2020-05-16 20:32:28 -03:00
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spd_t *dev = spd_devices[info->local];
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2020-03-25 21:35:35 -03:00
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spd_log("SPD: initializing slot %d (SMBus %02Xh)\n", dev->slot, SPD_BASE_ADDR + dev->slot);
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smbus_sethandler(SPD_BASE_ADDR + dev->slot, 1,
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2020-05-16 20:32:28 -03:00
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spd_read_byte, spd_read_byte_cmd, spd_read_word_cmd, spd_read_block_cmd,
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spd_write_byte, NULL, NULL, NULL,
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dev);
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2020-03-25 21:35:35 -03:00
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2020-06-26 18:24:15 -03:00
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spd_present = 1;
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2020-03-25 21:35:35 -03:00
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return dev;
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}
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uint8_t
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log2_ui16(uint16_t i)
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{
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uint8_t ret = 0;
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while ((i >>= 1))
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ret++;
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return ret;
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}
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int
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comp_ui16_rev(const void *elem1, const void *elem2)
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{
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2020-05-16 20:32:28 -03:00
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uint16_t a = *((uint16_t *) elem1);
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uint16_t b = *((uint16_t *) elem2);
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2020-03-25 21:35:35 -03:00
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return ((a > b) ? -1 : ((a < b) ? 1 : 0));
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}
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void
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2020-06-26 18:05:27 -03:00
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spd_populate(uint16_t *vslots, uint8_t slot_count, uint16_t total_size, uint16_t min_module_size, uint16_t max_module_size, uint8_t enable_asym)
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2020-03-25 21:35:35 -03:00
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{
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2020-06-26 18:05:27 -03:00
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uint8_t vslot, next_empty_vslot, split, i;
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uint16_t asym;
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2020-03-25 21:35:35 -03:00
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/* populate vslots with modules in power-of-2 capacities */
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2020-06-26 18:05:27 -03:00
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memset(vslots, 0x00, SPD_MAX_SLOTS << 1);
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2020-03-25 21:35:35 -03:00
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for (vslot = 0; vslot < slot_count && total_size; vslot++) {
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/* populate slot */
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vslots[vslot] = (1 << log2_ui16(MIN(total_size, max_module_size)));
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2020-03-27 12:11:00 -03:00
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if (total_size >= vslots[vslot]) {
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2020-05-18 23:00:05 -03:00
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spd_log("SPD: initial vslot %d = %d MB\n", vslot, vslots[vslot]);
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2020-03-27 12:11:00 -03:00
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total_size -= vslots[vslot];
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} else {
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2020-03-29 19:32:37 -03:00
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vslots[vslot] = 0;
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2020-03-27 12:11:00 -03:00
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break;
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}
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2020-03-25 21:35:35 -03:00
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}
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2020-05-16 20:32:28 -03:00
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/* did we populate all the RAM? */
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if (total_size) {
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2020-06-26 18:05:27 -03:00
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/* work backwards to add the missing RAM as asymmetric modules if possible */
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if (enable_asym) {
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vslot = slot_count - 1;
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do {
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asym = (1 << log2_ui16(MIN(total_size, vslots[vslot])));
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if (vslots[vslot] + asym <= max_module_size) {
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vslots[vslot] += asym;
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total_size -= asym;
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}
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} while ((vslot-- > 0) && total_size);
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}
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2020-05-16 20:32:28 -03:00
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if (total_size) /* still not enough */
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spd_log("SPD: not enough RAM slots (%d) to cover memory (%d MB short)\n", slot_count, total_size);
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}
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2020-03-25 21:35:35 -03:00
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2020-04-26 19:24:15 -03:00
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/* populate empty vslots by splitting modules... */
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split = (total_size == 0); /* ...if possible */
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2020-03-25 21:35:35 -03:00
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while (split) {
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/* look for a module to split */
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split = 0;
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for (vslot = 0; vslot < slot_count; vslot++) {
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2020-05-16 20:32:28 -03:00
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if ((vslots[vslot] < (min_module_size << 1)) || (vslots[vslot] != (1 << log2_ui16(vslots[vslot]))))
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continue; /* no module here, module is too small to be split, or asymmetric module */
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2020-03-25 21:35:35 -03:00
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/* find next empty vslot */
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next_empty_vslot = 0;
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for (i = vslot + 1; i < slot_count && !next_empty_vslot; i++) {
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if (!vslots[i])
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next_empty_vslot = i;
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}
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if (!next_empty_vslot)
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break; /* no empty vslots left */
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/* split the module into its own vslot and the next empty vslot */
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2020-03-27 12:11:00 -03:00
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spd_log("SPD: splitting vslot %d (%d MB) into %d and %d (%d MB each)\n", vslot, vslots[vslot], vslot, next_empty_vslot, (vslots[vslot] >> 1));
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vslots[vslot] = vslots[next_empty_vslot] = (vslots[vslot] >> 1);
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2020-03-25 21:35:35 -03:00
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split = 1;
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2020-06-26 18:05:27 -03:00
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break;
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2020-03-25 21:35:35 -03:00
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}
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2020-06-26 18:05:27 -03:00
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/* sort vslots by descending capacity if any were split */
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2020-03-25 21:35:35 -03:00
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if (split)
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qsort(vslots, slot_count, sizeof(uint16_t), comp_ui16_rev);
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}
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2020-06-26 18:05:27 -03:00
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}
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void
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spd_register(uint8_t ram_type, uint8_t slot_mask, uint16_t max_module_size)
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{
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uint8_t slot, slot_count, vslot, i;
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uint16_t min_module_size, vslots[SPD_MAX_SLOTS], asym;
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device_t *info;
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spd_edo_t *edo_data;
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spd_sdram_t *sdram_data;
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/* determine the minimum module size for this RAM type */
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switch (ram_type) {
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case SPD_TYPE_FPM:
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case SPD_TYPE_EDO:
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min_module_size = SPD_MIN_SIZE_EDO;
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break;
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case SPD_TYPE_SDRAM:
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min_module_size = SPD_MIN_SIZE_SDRAM;
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break;
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default:
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spd_log("SPD: unknown RAM type 0x%02X\n", ram_type);
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return;
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}
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/* count how many (real) slots are enabled */
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slot_count = 0;
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for (slot = 0; slot < SPD_MAX_SLOTS; slot++) {
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vslots[slot] = 0;
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if (slot_mask & (1 << slot)) {
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slot_count++;
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}
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}
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/* populate vslots */
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spd_populate(vslots, slot_count, (mem_size >> 10), min_module_size, max_module_size, 1);
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2020-03-25 21:35:35 -03:00
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/* register SPD devices and populate their data according to the vslots */
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vslot = 0;
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2020-03-27 12:11:00 -03:00
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for (slot = 0; slot < SPD_MAX_SLOTS && vslots[vslot]; slot++) {
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2020-03-25 21:35:35 -03:00
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if (!(slot_mask & (1 << slot)))
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continue; /* slot disabled */
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2020-05-16 20:32:28 -03:00
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info = (device_t *) malloc(sizeof(device_t));
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memset(info, 0, sizeof(device_t));
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info->name = "Serial Presence Detect ROM";
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info->local = slot;
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info->init = spd_init;
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info->close = spd_close;
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spd_devices[slot] = (spd_t *) malloc(sizeof(spd_t));
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memset(spd_devices[slot], 0, sizeof(spd_t));
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spd_devices[slot]->info = info;
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spd_devices[slot]->slot = slot;
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spd_devices[slot]->size = vslots[vslot];
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|
|
/* determine the second row size, from which the first row size can be obtained */
|
|
|
|
|
asym = (vslots[vslot] - (1 << log2_ui16(vslots[vslot]))); /* separate the powers of 2 */
|
|
|
|
|
if (!asym) /* is the module asymmetric? */
|
|
|
|
|
asym = (vslots[vslot] >> 1); /* symmetric, therefore divide by 2 */
|
|
|
|
|
|
|
|
|
|
spd_devices[slot]->row1 = (vslots[vslot] - asym);
|
|
|
|
|
spd_devices[slot]->row2 = asym;
|
2020-03-25 21:35:35 -03:00
|
|
|
|
2020-05-16 20:32:28 -03:00
|
|
|
spd_log("SPD: registering slot %d = vslot %d = %d MB (%d/%d)\n", slot, vslot, vslots[vslot], spd_devices[slot]->row1, spd_devices[slot]->row2);
|
2020-03-25 21:35:35 -03:00
|
|
|
|
|
|
|
|
switch (ram_type) {
|
2020-04-26 19:24:15 -03:00
|
|
|
case SPD_TYPE_FPM:
|
|
|
|
|
case SPD_TYPE_EDO:
|
|
|
|
|
edo_data = (spd_edo_t *) &spd_data[slot];
|
|
|
|
|
memset(edo_data, 0, sizeof(spd_edo_t));
|
|
|
|
|
|
2020-05-16 20:32:28 -03:00
|
|
|
/* EDO SPD is specified by JEDEC and present in some modules, but
|
|
|
|
|
most utilities cannot interpret it correctly. SIV32 at least gets
|
|
|
|
|
the module capacities right, so it was used as a reference here. */
|
2020-04-26 19:24:15 -03:00
|
|
|
edo_data->bytes_used = 0x80;
|
|
|
|
|
edo_data->spd_size = 0x08;
|
|
|
|
|
edo_data->mem_type = ram_type;
|
2020-05-16 20:32:28 -03:00
|
|
|
edo_data->row_bits = SPD_ROLLUP(7 + log2_ui16(spd_devices[slot]->row1)); /* first row */
|
2020-04-26 19:24:15 -03:00
|
|
|
edo_data->col_bits = 9;
|
2020-05-16 20:32:28 -03:00
|
|
|
if (spd_devices[slot]->row1 != spd_devices[slot]->row2) { /* the upper 4 bits of row_bits/col_bits should be 0 on a symmetric module */
|
|
|
|
|
edo_data->row_bits |= (SPD_ROLLUP(7 + log2_ui16(spd_devices[slot]->row2)) << 4); /* second row, if different from first */
|
|
|
|
|
edo_data->col_bits |= (9 << 4); /* same as first row, but just in case */
|
|
|
|
|
}
|
2020-04-26 19:24:15 -03:00
|
|
|
edo_data->banks = 2;
|
|
|
|
|
edo_data->data_width_lsb = 64;
|
|
|
|
|
edo_data->signal_level = SPD_SIGNAL_LVTTL;
|
|
|
|
|
edo_data->trac = 50;
|
|
|
|
|
edo_data->tcac = 13;
|
|
|
|
|
edo_data->refresh_rate = SPD_REFRESH_NORMAL;
|
|
|
|
|
edo_data->dram_width = 8;
|
|
|
|
|
|
|
|
|
|
edo_data->spd_rev = 0x12;
|
2020-05-16 20:32:28 -03:00
|
|
|
sprintf(edo_data->part_no, EMU_NAME "-%s-%03dM", (ram_type == SPD_TYPE_FPM) ? "FPM" : "EDO", vslots[vslot]);
|
2020-04-26 19:24:15 -03:00
|
|
|
for (i = strlen(edo_data->part_no); i < sizeof(edo_data->part_no); i++)
|
2020-05-16 20:32:28 -03:00
|
|
|
edo_data->part_no[i] = ' '; /* part number should be space-padded */
|
|
|
|
|
edo_data->rev_code[0] = EMU_VERSION_MAJ;
|
|
|
|
|
edo_data->rev_code[1] = (((EMU_VERSION_MIN / 10) << 4) | (EMU_VERSION_MIN % 10));
|
2020-04-26 19:24:15 -03:00
|
|
|
edo_data->mfg_year = 20;
|
|
|
|
|
edo_data->mfg_week = 17;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < 63; i++)
|
|
|
|
|
edo_data->checksum += spd_data[slot][i];
|
|
|
|
|
for (i = 0; i < 129; i++)
|
|
|
|
|
edo_data->checksum2 += spd_data[slot][i];
|
|
|
|
|
break;
|
|
|
|
|
|
2020-03-25 21:35:35 -03:00
|
|
|
case SPD_TYPE_SDRAM:
|
2020-04-26 19:24:15 -03:00
|
|
|
sdram_data = (spd_sdram_t *) &spd_data[slot];
|
2020-03-25 21:35:35 -03:00
|
|
|
memset(sdram_data, 0, sizeof(spd_sdram_t));
|
|
|
|
|
|
|
|
|
|
sdram_data->bytes_used = 0x80;
|
|
|
|
|
sdram_data->spd_size = 0x08;
|
|
|
|
|
sdram_data->mem_type = ram_type;
|
2020-05-16 20:32:28 -03:00
|
|
|
sdram_data->row_bits = SPD_ROLLUP(6 + log2_ui16(spd_devices[slot]->row1)); /* first row */
|
2020-03-25 21:35:35 -03:00
|
|
|
sdram_data->col_bits = 9;
|
2020-05-16 20:32:28 -03:00
|
|
|
if (spd_devices[slot]->row1 != spd_devices[slot]->row2) { /* the upper 4 bits of row_bits/col_bits should be 0 on a symmetric module */
|
|
|
|
|
sdram_data->row_bits |= (SPD_ROLLUP(6 + log2_ui16(spd_devices[slot]->row2)) << 4); /* second row, if different from first */
|
|
|
|
|
sdram_data->col_bits |= (9 << 4); /* same as first row, but just in case */
|
|
|
|
|
}
|
2020-03-25 21:35:35 -03:00
|
|
|
sdram_data->rows = 2;
|
|
|
|
|
sdram_data->data_width_lsb = 64;
|
2020-04-26 19:24:15 -03:00
|
|
|
sdram_data->signal_level = SPD_SIGNAL_LVTTL;
|
2020-03-27 22:33:35 -03:00
|
|
|
sdram_data->tclk = 0x75; /* 7.5 ns = 133.3 MHz */
|
|
|
|
|
sdram_data->tac = 0x10;
|
2020-04-26 19:24:15 -03:00
|
|
|
sdram_data->refresh_rate = SPD_SDR_REFRESH_SELF | SPD_REFRESH_NORMAL;
|
2020-03-25 21:35:35 -03:00
|
|
|
sdram_data->sdram_width = 8;
|
|
|
|
|
sdram_data->tccd = 1;
|
|
|
|
|
sdram_data->burst = SPD_SDR_BURST_PAGE | 1 | 2 | 4 | 8;
|
|
|
|
|
sdram_data->banks = 4;
|
2020-05-16 20:32:28 -03:00
|
|
|
sdram_data->cas = 0x1c; /* CAS 5/4/3 supported */
|
|
|
|
|
sdram_data->cslat = sdram_data->we = 0x7f;
|
2020-03-25 21:35:35 -03:00
|
|
|
sdram_data->dev_attr = SPD_SDR_ATTR_EARLY_RAS | SPD_SDR_ATTR_AUTO_PC | SPD_SDR_ATTR_PC_ALL | SPD_SDR_ATTR_W1R_BURST;
|
2020-03-27 22:33:35 -03:00
|
|
|
sdram_data->tclk2 = 0xA0; /* 10 ns = 100 MHz */
|
|
|
|
|
sdram_data->tclk3 = 0xF0; /* 15 ns = 66.7 MHz */
|
|
|
|
|
sdram_data->tac2 = sdram_data->tac3 = 0x10;
|
2020-03-25 21:35:35 -03:00
|
|
|
sdram_data->trp = sdram_data->trrd = sdram_data->trcd = sdram_data->tras = 1;
|
2020-05-16 20:32:28 -03:00
|
|
|
if (spd_devices[slot]->row1 != spd_devices[slot]->row2) {
|
|
|
|
|
/* Utilities interpret bank_density a bit differently on asymmetric modules. */
|
|
|
|
|
sdram_data->bank_density = (1 << (log2_ui16(spd_devices[slot]->row1 >> 1) - 2)); /* first row */
|
|
|
|
|
sdram_data->bank_density |= (1 << (log2_ui16(spd_devices[slot]->row2 >> 1) - 2)); /* second row */
|
|
|
|
|
} else {
|
|
|
|
|
sdram_data->bank_density = (1 << (log2_ui16(spd_devices[slot]->row1 >> 1) - 1)); /* symmetric module = only one bit is set */
|
|
|
|
|
}
|
2020-03-25 21:35:35 -03:00
|
|
|
sdram_data->ca_setup = sdram_data->data_setup = 0x15;
|
|
|
|
|
sdram_data->ca_hold = sdram_data->data_hold = 0x08;
|
2020-04-26 19:24:15 -03:00
|
|
|
|
2020-03-25 21:35:35 -03:00
|
|
|
sdram_data->spd_rev = 0x12;
|
2020-05-16 20:32:28 -03:00
|
|
|
sprintf(sdram_data->part_no, EMU_NAME "-SDR-%03dM", vslots[vslot]);
|
2020-03-27 22:13:28 -03:00
|
|
|
for (i = strlen(sdram_data->part_no); i < sizeof(sdram_data->part_no); i++)
|
2020-05-16 20:32:28 -03:00
|
|
|
sdram_data->part_no[i] = ' '; /* part number should be space-padded */
|
|
|
|
|
sdram_data->rev_code[0] = EMU_VERSION_MAJ;
|
|
|
|
|
sdram_data->rev_code[1] = (((EMU_VERSION_MIN / 10) << 4) | (EMU_VERSION_MIN % 10));
|
2020-04-26 19:24:15 -03:00
|
|
|
sdram_data->mfg_year = 20;
|
|
|
|
|
sdram_data->mfg_week = 13;
|
|
|
|
|
|
2020-03-25 21:35:35 -03:00
|
|
|
sdram_data->freq = 100;
|
|
|
|
|
sdram_data->features = 0xFF;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < 63; i++)
|
|
|
|
|
sdram_data->checksum += spd_data[slot][i];
|
2020-04-26 19:24:15 -03:00
|
|
|
for (i = 0; i < 129; i++)
|
|
|
|
|
sdram_data->checksum2 += spd_data[slot][i];
|
2020-03-25 21:35:35 -03:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
2020-06-26 21:03:46 -03:00
|
|
|
device_add(info);
|
2020-03-25 21:35:35 -03:00
|
|
|
vslot++;
|
|
|
|
|
}
|
|
|
|
|
}
|
2020-06-26 21:03:46 -03:00
|
|
|
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
spd_write_drbs(uint8_t *regs, uint8_t reg_min, uint8_t reg_max, uint8_t drb_unit)
|
|
|
|
|
{
|
2020-06-26 22:05:32 -03:00
|
|
|
uint8_t row, dimm, drb, apollo = 0;
|
2020-06-26 21:03:46 -03:00
|
|
|
uint16_t size, vslots[SPD_MAX_SLOTS];
|
|
|
|
|
|
2020-06-26 22:05:32 -03:00
|
|
|
/* Special case for VIA Apollo Pro family, which jumps from 5F to 56. */
|
|
|
|
|
if (reg_max < reg_min) {
|
|
|
|
|
apollo = reg_max;
|
2020-06-26 22:15:21 -03:00
|
|
|
reg_max = reg_min + 7;
|
2020-06-26 22:05:32 -03:00
|
|
|
}
|
2020-06-26 21:03:46 -03:00
|
|
|
|
|
|
|
|
/* No SPD: split SIMMs into pairs as if they were "DIMM"s. */
|
|
|
|
|
if (!spd_present) {
|
|
|
|
|
dimm = ((reg_max - reg_min) + 1) >> 1; /* amount of "DIMM"s, also used to determine the maximum "DIMM" size */
|
|
|
|
|
spd_populate(vslots, dimm, (mem_size >> 10), drb_unit, 1 << (log2_ui16(machines[machine].max_ram / dimm)), 0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Write DRBs for each row. */
|
|
|
|
|
spd_log("Writing DRBs... regs=[%02X:%02X] unit=%d\n", reg_min, reg_max, drb_unit);
|
|
|
|
|
for (row = 0; row <= (reg_max - reg_min); row++) {
|
|
|
|
|
dimm = (row >> 1);
|
|
|
|
|
size = 0;
|
|
|
|
|
|
|
|
|
|
if (spd_present) {
|
|
|
|
|
/* SPD enabled: use SPD info for this slot, if present. */
|
|
|
|
|
if (spd_devices[dimm]) {
|
|
|
|
|
if (spd_devices[dimm]->row1 < drb_unit) /* hack within a hack: turn a double-sided DIMM that is too small into a single-sided one */
|
|
|
|
|
size = ((row & 1) ? 0 : drb_unit);
|
|
|
|
|
else
|
|
|
|
|
size = ((row & 1) ? spd_devices[dimm]->row2 : spd_devices[dimm]->row1);
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
/* No SPD: use the values calculated above. */
|
|
|
|
|
size = (vslots[dimm] >> 1);
|
|
|
|
|
}
|
|
|
|
|
|
2020-06-26 22:05:32 -03:00
|
|
|
/* Determine the DRB register to write. */
|
|
|
|
|
drb = reg_min + row;
|
2020-06-26 22:15:21 -03:00
|
|
|
if ((apollo) && ((drb & 0xf) < 0xa))
|
|
|
|
|
drb = apollo + (drb & 0xf);
|
|
|
|
|
|
|
|
|
|
/* Write DRB register, adding the previous DRB's value. */
|
|
|
|
|
if (row == 0)
|
|
|
|
|
regs[drb] = 0;
|
|
|
|
|
else if ((apollo) && (drb == apollo))
|
|
|
|
|
regs[drb] = regs[drb | 0xf]; /* 5F comes before 56 */
|
|
|
|
|
else
|
|
|
|
|
regs[drb] = regs[drb - 1];
|
2020-06-26 21:03:46 -03:00
|
|
|
if (size)
|
2020-06-26 22:15:21 -03:00
|
|
|
regs[drb] += (size / drb_unit); /* this will intentionally overflow on 440GX with 2 GB */
|
2020-06-26 22:05:32 -03:00
|
|
|
spd_log("DRB[%d] = %d MB (%02Xh raw)\n", row, size, regs[drb]);
|
2020-06-26 21:03:46 -03:00
|
|
|
}
|
|
|
|
|
}
|