434 lines
9.1 KiB
C
434 lines
9.1 KiB
C
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/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the Intel PCISet chips from 420TX to 440FX.
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*
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* Version: @(#)intel_4x0.c 1.0.0 2019/05/13
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*
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* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
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* Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2019 Miran Grca.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#include "../86box.h"
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#include "../mem.h"
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#include "../io.h"
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#include "../rom.h"
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#include "../pci.h"
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#include "../device.h"
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#include "../keyboard.h"
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#include "chipset.h"
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enum
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{
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INTEL_420TX,
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INTEL_430LX,
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INTEL_430NX,
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INTEL_430FX,
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INTEL_430FX_PB640,
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INTEL_430HX,
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INTEL_430VX
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#if defined(DEV_BRANCH) && defined(USE_I686)
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,INTEL_440FX
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#endif
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};
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typedef struct
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{
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uint8_t regs[256];
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int type;
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} i4x0_t;
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static void
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i4x0_map(uint32_t addr, uint32_t size, int state)
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{
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switch (state & 3) {
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case 0:
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mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
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break;
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case 1:
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mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
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break;
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case 2:
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mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
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break;
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case 3:
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mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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break;
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}
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flushmmucache_nopc();
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}
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static void
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i4x0_write(int func, int addr, uint8_t val, void *priv)
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{
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i4x0_t *dev = (i4x0_t *) priv;
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if (func)
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return;
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if ((addr >= 0x10) && (addr < 0x4f))
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return;
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switch (addr) {
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case 0x00: case 0x01: case 0x02: case 0x03:
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case 0x08: case 0x09: case 0x0a: case 0x0b:
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case 0x0c: case 0x0e:
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return;
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case 0x04: /*Command register*/
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if (dev->type >= INTEL_430FX) {
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if (dev->type == INTEL_430FX_PB640)
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val &= 0x06;
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else
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val &= 0x02;
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} else
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val &= 0x42;
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val |= 0x04;
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break;
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case 0x05:
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if (dev->type >= INTEL_430FX)
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val = 0;
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else
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val &= 0x01;
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break;
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case 0x06: /*Status*/
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val = 0;
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break;
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case 0x07:
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if (dev->type >= INTEL_430HX) {
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val &= 0x80;
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val |= 0x02;
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} else {
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val = 0x02;
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if (dev->type == INTEL_430FX_PB640)
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val |= 0x20;
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}
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break;
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case 0x59: /*PAM0*/
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if ((dev->regs[0x59] ^ val) & 0xf0) {
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i4x0_map(0xf0000, 0x10000, val >> 4);
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shadowbios = (val & 0x10);
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}
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break;
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case 0x5a: /*PAM1*/
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if ((dev->regs[0x5a] ^ val) & 0x0f)
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i4x0_map(0xc0000, 0x04000, val & 0xf);
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if ((dev->regs[0x5a] ^ val) & 0xf0)
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i4x0_map(0xc4000, 0x04000, val >> 4);
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break;
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case 0x5b: /*PAM2*/
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if ((dev->regs[0x5b] ^ val) & 0x0f)
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i4x0_map(0xc8000, 0x04000, val & 0xf);
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if ((dev->regs[0x5b] ^ val) & 0xf0)
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i4x0_map(0xcc000, 0x04000, val >> 4);
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break;
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case 0x5c: /*PAM3*/
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if ((dev->regs[0x5c] ^ val) & 0x0f)
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i4x0_map(0xd0000, 0x04000, val & 0xf);
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if ((dev->regs[0x5c] ^ val) & 0xf0)
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i4x0_map(0xd4000, 0x04000, val >> 4);
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break;
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case 0x5d: /*PAM4*/
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if ((dev->regs[0x5d] ^ val) & 0x0f)
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i4x0_map(0xd8000, 0x04000, val & 0xf);
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if ((dev->regs[0x5d] ^ val) & 0xf0)
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i4x0_map(0xdc000, 0x04000, val >> 4);
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break;
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case 0x5e: /*PAM5*/
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if ((dev->regs[0x5e] ^ val) & 0x0f)
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i4x0_map(0xe0000, 0x04000, val & 0xf);
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if ((dev->regs[0x5e] ^ val) & 0xf0)
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i4x0_map(0xe4000, 0x04000, val >> 4);
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break;
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case 0x5f: /*PAM6*/
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if ((dev->regs[0x5f] ^ val) & 0x0f)
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i4x0_map(0xe8000, 0x04000, val & 0xf);
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if ((dev->regs[0x5f] ^ val) & 0xf0)
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i4x0_map(0xec000, 0x04000, val >> 4);
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break;
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case 0x72: /*SMRAM*/
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if ((dev->type >= INTEL_430FX) && ((dev->regs[0x72] ^ val) & 0x48))
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i4x0_map(0xa0000, 0x20000, ((val & 0x48) == 0x48) ? 3 : 0);
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else if ((dev->type < INTEL_430FX) && ((dev->regs[0x72] ^ val) & 0x20))
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i4x0_map(0xa0000, 0x20000, ((val & 0x20) == 0x20) ? 3 : 0);
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break;
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}
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dev->regs[addr] = val;
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}
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static uint8_t
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i4x0_read(int func, int addr, void *priv)
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{
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i4x0_t *dev = (i4x0_t *) priv;
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if (func)
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return 0xff;
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return dev->regs[addr];
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}
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static void
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i4x0_reset(void *priv)
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{
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i4x0_t *i4x0 = (i4x0_t *)priv;
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i4x0_write(0, 0x59, 0x00, priv);
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if (i4x0->type >= INTEL_430FX)
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i4x0_write(0, 0x72, 0x02, priv);
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}
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static void
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i4x0_close(void *p)
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{
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i4x0_t *i4x0 = (i4x0_t *)p;
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free(i4x0);
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}
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static void
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*i4x0_init(const device_t *info)
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{
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i4x0_t *i4x0 = (i4x0_t *) malloc(sizeof(i4x0_t));
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memset(i4x0, 0, sizeof(i4x0_t));
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i4x0->type = info->local;
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i4x0->regs[0x00] = 0x86; i4x0->regs[0x01] = 0x80; /*Intel*/
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switch(i4x0->type) {
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case INTEL_420TX:
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i4x0->regs[0x02] = 0x83; i4x0->regs[0x03] = 0x04; /*82424TX/ZX*/
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i4x0->regs[0x08] = 0x03; /*A3 stepping*/
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i4x0->regs[0x50] = 0x80;
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i4x0->regs[0x52] = 0x40; /*256kb PLB cache*/
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break;
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case INTEL_430LX:
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i4x0->regs[0x02] = 0xa3; i4x0->regs[0x03] = 0x04; /*82434LX/NX*/
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i4x0->regs[0x08] = 0x03; /*A3 stepping*/
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i4x0->regs[0x50] = 0x80;
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i4x0->regs[0x52] = 0x40; /*256kb PLB cache*/
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break;
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case INTEL_430NX:
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i4x0->regs[0x02] = 0xa3; i4x0->regs[0x03] = 0x04; /*82434LX/NX*/
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i4x0->regs[0x08] = 0x10; /*A0 stepping*/
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i4x0->regs[0x50] = 0xA0;
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i4x0->regs[0x52] = 0x44; /*256kb PLB cache*/
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i4x0->regs[0x66] = i4x0->regs[0x67] = 0x02;
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break;
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case INTEL_430FX:
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case INTEL_430FX_PB640:
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i4x0->regs[0x02] = 0x2d; i4x0->regs[0x03] = 0x12; /*SB82437FX-66*/
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if (i4x0->type == INTEL_430FX_PB640)
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i4x0->regs[0x08] = 0x02; /*???? stepping*/
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else
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i4x0->regs[0x08] = 0x00; /*A0 stepping*/
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i4x0->regs[0x52] = 0x40; /*256kb PLB cache*/
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break;
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case INTEL_430HX:
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i4x0->regs[0x02] = 0x50; i4x0->regs[0x03] = 0x12; /*82439HX*/
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i4x0->regs[0x08] = 0x00; /*A0 stepping*/
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i4x0->regs[0x51] = 0x20;
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i4x0->regs[0x52] = 0xB5; /*512kb cache*/
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i4x0->regs[0x56] = 0x52; /*DRAM control*/
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i4x0->regs[0x59] = 0x40;
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i4x0->regs[0x5A] = i4x0->regs[0x5B] = i4x0->regs[0x5C] = i4x0->regs[0x5D] = 0x44;
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i4x0->regs[0x5E] = i4x0->regs[0x5F] = 0x44;
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i4x0->regs[0x65] = i4x0->regs[0x66] = i4x0->regs[0x67] = 0x02;
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i4x0->regs[0x68] = 0x11;
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break;
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case INTEL_430VX:
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i4x0->regs[0x02] = 0x30; i4x0->regs[0x03] = 0x70; /*82437VX*/
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i4x0->regs[0x08] = 0x00; /*A0 stepping*/
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i4x0->regs[0x52] = 0x42; /*256kb PLB cache*/
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i4x0->regs[0x53] = 0x14;
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i4x0->regs[0x56] = 0x52; /*DRAM control*/
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i4x0->regs[0x67] = 0x11;
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i4x0->regs[0x69] = 0x03;
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i4x0->regs[0x70] = 0x20;
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i4x0->regs[0x74] = 0x0e;
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i4x0->regs[0x78] = 0x23;
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break;
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#if defined(DEV_BRANCH) && defined(USE_I686)
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case INTEL_440FX:
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i4x0->regs[0x02] = 0x37; i4x0->regs[0x03] = 0x12; /*82441FX*/
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i4x0->regs[0x08] = 0x02; /*A0 stepping*/
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i4x0->regs[0x2c] = 0xf4;
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i4x0->regs[0x2d] = 0x1a;
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i4x0->regs[0x2f] = 0x11;
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i4x0->regs[0x51] = 0x01;
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i4x0->regs[0x53] = 0x80;
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i4x0->regs[0x58] = 0x10;
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i4x0->regs[0x5a] = i4x0->regs[0x5b] = i4x0->regs[0x5c] = i4x0->regs[0x5d] = 0x11;
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i4x0->regs[0x5e] = 0x11;
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i4x0->regs[0x5f] = 0x31;
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break;
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#endif
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}
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i4x0->regs[0x04] = 0x06; i4x0->regs[0x05] = 0x00;
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#if defined(DEV_BRANCH) && defined(USE_I686)
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if (i4x0->type == INTEL_440FX)
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i4x0->regs[0x06] = 0x80;
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#endif
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if (i4x0->type == INTEL_430FX)
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i4x0->regs[0x07] = 0x82;
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#if defined(DEV_BRANCH) && defined(USE_I686)
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else if (i4x0->type != INTEL_440FX)
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#else
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else
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#endif
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i4x0->regs[0x07] = 0x02;
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i4x0->regs[0x0b] = 0x06;
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if (i4x0->type >= INTEL_430FX)
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i4x0->regs[0x57] = 0x01;
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else
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i4x0->regs[0x57] = 0x31;
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i4x0->regs[0x60] = i4x0->regs[0x61] = i4x0->regs[0x62] = i4x0->regs[0x63] = 0x02;
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i4x0->regs[0x64] = 0x02;
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if (i4x0->type >= INTEL_430FX)
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i4x0->regs[0x72] = 0x02;
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pci_add_card(0, i4x0_read, i4x0_write, i4x0);
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return i4x0;
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}
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const device_t i420tx_device =
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{
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"Intel 82424TX",
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DEVICE_PCI,
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INTEL_420TX,
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i4x0_init,
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i4x0_close,
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i4x0_reset,
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NULL,
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NULL,
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NULL,
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NULL
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};
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const device_t i430lx_device =
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|
|
{
|
||
|
|
"Intel 82434LX",
|
||
|
|
DEVICE_PCI,
|
||
|
|
INTEL_430LX,
|
||
|
|
i4x0_init,
|
||
|
|
i4x0_close,
|
||
|
|
i4x0_reset,
|
||
|
|
NULL,
|
||
|
|
NULL,
|
||
|
|
NULL,
|
||
|
|
NULL
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
const device_t i430nx_device =
|
||
|
|
{
|
||
|
|
"Intel 82434NX",
|
||
|
|
DEVICE_PCI,
|
||
|
|
INTEL_430NX,
|
||
|
|
i4x0_init,
|
||
|
|
i4x0_close,
|
||
|
|
i4x0_reset,
|
||
|
|
NULL,
|
||
|
|
NULL,
|
||
|
|
NULL,
|
||
|
|
NULL
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
const device_t i430fx_device =
|
||
|
|
{
|
||
|
|
"Intel SB82437FX-66",
|
||
|
|
DEVICE_PCI,
|
||
|
|
INTEL_430FX,
|
||
|
|
i4x0_init,
|
||
|
|
i4x0_close,
|
||
|
|
i4x0_reset,
|
||
|
|
NULL,
|
||
|
|
NULL,
|
||
|
|
NULL,
|
||
|
|
NULL
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
const device_t i430fx_pb640_device =
|
||
|
|
{
|
||
|
|
"Intel SB82437FX-66 (PB640)",
|
||
|
|
DEVICE_PCI,
|
||
|
|
INTEL_430FX_PB640,
|
||
|
|
i4x0_init,
|
||
|
|
i4x0_close,
|
||
|
|
i4x0_reset,
|
||
|
|
NULL,
|
||
|
|
NULL,
|
||
|
|
NULL,
|
||
|
|
NULL
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
const device_t i430hx_device =
|
||
|
|
{
|
||
|
|
"Intel 82439HX",
|
||
|
|
DEVICE_PCI,
|
||
|
|
INTEL_430HX,
|
||
|
|
i4x0_init,
|
||
|
|
i4x0_close,
|
||
|
|
i4x0_reset,
|
||
|
|
NULL,
|
||
|
|
NULL,
|
||
|
|
NULL,
|
||
|
|
NULL
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
const device_t i430vx_device =
|
||
|
|
{
|
||
|
|
"Intel 82437VX",
|
||
|
|
DEVICE_PCI,
|
||
|
|
INTEL_430VX,
|
||
|
|
i4x0_init,
|
||
|
|
i4x0_close,
|
||
|
|
i4x0_reset,
|
||
|
|
NULL,
|
||
|
|
NULL,
|
||
|
|
NULL,
|
||
|
|
NULL
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
#if defined(DEV_BRANCH) && defined(USE_I686)
|
||
|
|
const device_t i440fx_device =
|
||
|
|
{
|
||
|
|
"Intel 82441FX",
|
||
|
|
DEVICE_PCI,
|
||
|
|
INTEL_440FX,
|
||
|
|
i4x0_init,
|
||
|
|
i4x0_close,
|
||
|
|
i4x0_reset,
|
||
|
|
NULL,
|
||
|
|
NULL,
|
||
|
|
NULL,
|
||
|
|
NULL
|
||
|
|
};
|
||
|
|
#endif
|