2023-07-14 23:38:04 +02:00
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/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Emulation of the 8514/A-compatible Mach8 and Mach32 graphics
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* chips from ATI for the ISA/VLB/MCA/PCI buses.
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*
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*
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*
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* Authors: TheCollector1995.
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*
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2024-01-15 21:43:33 +01:00
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* Copyright 2022-2024 TheCollector1995.
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2023-07-14 23:38:04 +02:00
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include <wchar.h>
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#include <stdatomic.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include <86box/device.h>
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#include <86box/io.h>
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#include <86box/mem.h>
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2025-03-06 19:26:11 +06:00
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#include "cpu.h"
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2023-07-14 23:38:04 +02:00
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#include <86box/timer.h>
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#include <86box/mca.h>
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#include <86box/pci.h>
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#include <86box/rom.h>
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#include <86box/plat.h>
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#include <86box/thread.h>
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#include <86box/video.h>
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#include <86box/i2c.h>
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#include <86box/vid_ddc.h>
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2023-10-09 20:14:03 +02:00
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#include <86box/vid_8514a.h>
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2024-10-03 14:56:23 +02:00
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#include <86box/vid_xga.h>
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2023-07-14 23:38:04 +02:00
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#include <86box/vid_svga.h>
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#include <86box/vid_svga_render.h>
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#include <86box/vid_ati_eeprom.h>
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2024-01-15 21:43:33 +01:00
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#include <86box/vid_ati_mach8.h>
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2023-07-14 23:38:04 +02:00
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2024-01-15 21:43:33 +01:00
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#define BIOS_MACH8_VGA_ROM_PATH "roms/video/mach8/BIOS.BIN"
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2023-08-15 22:12:30 +02:00
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#define BIOS_MACH32_ISA_ROM_PATH "roms/video/mach32/ATi Mach32 Graphics Pro ISA.BIN"
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2023-08-11 20:32:56 -04:00
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#define BIOS_MACH32_VLB_ROM_PATH "roms/video/mach32/MACH32VLB.VBI"
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#define BIOS_MACH32_MCA_ROM_PATH "roms/video/mach32/MACH32MCA_Olivetti.BIN"
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#define BIOS_MACH32_PCI_ROM_PATH "roms/video/mach32/intelopt_00000.rom"
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2023-07-14 23:38:04 +02:00
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2025-02-01 03:29:03 -05:00
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static video_timings_t timing_gfxultra_isa = { .type = VIDEO_ISA, .write_b = 3, .write_w = 3, .write_l = 6, .read_b = 5, .read_w = 5, .read_l = 10 };
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static video_timings_t timing_mach32_vlb = { .type = VIDEO_BUS, .write_b = 2, .write_w = 2, .write_l = 1, .read_b = 20, .read_w = 20, .read_l = 21 };
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static video_timings_t timing_mach32_mca = { .type = VIDEO_MCA, .write_b = 4, .write_w = 5, .write_l = 10, .read_b = 5, .read_w = 5, .read_l = 10 };
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static video_timings_t timing_mach32_pci = { .type = VIDEO_PCI, .write_b = 2, .write_w = 2, .write_l = 1, .read_b = 20, .read_w = 20, .read_l = 21 };
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2023-07-14 23:38:04 +02:00
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2023-06-09 23:46:54 -04:00
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static void mach_accel_outb(uint16_t port, uint8_t val, void *priv);
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static void mach_accel_outw(uint16_t port, uint16_t val, void *priv);
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2024-11-13 22:55:16 +01:00
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static void mach_accel_outl(uint16_t port, uint32_t val, void *priv);
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2023-06-09 23:46:54 -04:00
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static uint8_t mach_accel_inb(uint16_t port, void *priv);
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static uint16_t mach_accel_inw(uint16_t port, void *priv);
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2024-11-13 22:55:16 +01:00
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static uint32_t mach_accel_inl(uint16_t port, void *priv);
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2023-07-14 23:38:04 +02:00
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2024-01-26 19:03:43 +01:00
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static void ati8514_accel_outb(uint16_t port, uint8_t val, void *priv);
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static void ati8514_accel_outw(uint16_t port, uint16_t val, void *priv);
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static void ati8514_accel_outl(uint16_t port, uint32_t val, void *priv);
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static uint8_t ati8514_accel_inb(uint16_t port, void *priv);
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static uint16_t ati8514_accel_inw(uint16_t port, void *priv);
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static uint32_t ati8514_accel_inl(uint16_t port, void *priv);
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static void mach32_updatemapping(mach_t *mach, svga_t *svga);
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2023-07-14 23:38:04 +02:00
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#ifdef ENABLE_MACH_LOG
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int mach_do_log = ENABLE_MACH_LOG;
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static void
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mach_log(const char *fmt, ...)
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{
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va_list ap;
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if (mach_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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# define mach_log(fmt, ...)
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#endif
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2025-02-01 03:29:03 -05:00
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#define WRITE8(addr, var, val) \
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switch ((addr) & 1) { \
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case 0: \
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var = (var & 0xff00) | (val); \
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break; \
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case 1: \
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var = (var & 0x00ff) | ((val) << 8); \
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break; \
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Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
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}
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#define READ8(addr, var) \
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switch ((addr) & 1) { \
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case 0: \
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temp = (var) & 0xff; \
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break; \
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case 1: \
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temp = ((var) >> 8) & 0xff; \
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break; \
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}
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#define READ_PIXTRANS_BYTE_IO(cx, n) \
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2023-07-14 23:38:04 +02:00
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if ((mach->accel.cmd_type == 2) || (mach->accel.cmd_type == 5)) { \
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2025-02-01 03:29:03 -05:00
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if (dev->bpp) { \
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if (n == 0) \
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Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
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mach->accel.pix_trans[(n)] = vram_w[(dev->accel.dest + (cx) + (n)) & (dev->vram_mask >> 1)] & 0xff; \
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2025-02-01 03:29:03 -05:00
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else \
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mach->accel.pix_trans[(n)] = vram_w[(dev->accel.dest + (cx) + (n)) & (dev->vram_mask >> 1)] >> 8; \
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} else \
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mach->accel.pix_trans[(n)] = dev->vram[(dev->accel.dest + (cx) + (n)) & dev->vram_mask]; \
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2023-07-14 23:38:04 +02:00
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}
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2025-02-01 03:29:03 -05:00
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#define READ_PIXTRANS_WORD(cx, n) \
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if ((cmd == 0) || (cmd == 1) || (cmd == 5) || (mach->accel.cmd_type == -1)) { \
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if (dev->bpp) \
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temp = vram_w[((dev->accel.cy * dev->pitch) + (cx) + (n)) & (dev->vram_mask >> 1)]; \
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else { \
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temp = dev->vram[((dev->accel.cy * dev->pitch) + (cx) + (n)) & dev->vram_mask]; \
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temp |= (dev->vram[((dev->accel.cy * dev->pitch) + (cx) + (n + 1)) & dev->vram_mask] << 8); \
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} \
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} else if ((mach->accel.cmd_type == 2) || (mach->accel.cmd_type == 5)) { \
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if (dev->bpp) \
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temp = vram_w[((dev->accel.dest) + (cx) + (n)) & (dev->vram_mask >> 1)]; \
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else { \
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temp = dev->vram[((dev->accel.dest) + (cx) + (n)) & dev->vram_mask]; \
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temp |= (dev->vram[((dev->accel.dest) + (cx) + (n + 1)) & dev->vram_mask] << 8); \
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} \
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} else if ((mach->accel.cmd_type == 3) || (mach->accel.cmd_type == 4)) { \
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if (dev->bpp) \
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temp = vram_w[((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (cx) + (n)) & (dev->vram_mask >> 1)]; \
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else { \
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temp = dev->vram[((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (cx) + (n)) & dev->vram_mask]; \
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Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
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temp |= (dev->vram[((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (cx) + (n + 1)) & dev->vram_mask] << 8); \
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2025-02-01 03:29:03 -05:00
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} \
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2023-07-14 23:38:04 +02:00
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}
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2025-02-01 03:29:03 -05:00
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#define READ(addr, dat) \
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if (dev->bpp) \
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2024-11-02 20:50:06 +01:00
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dat = vram_w[(addr) & (dev->vram_mask >> 1)]; \
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2025-02-01 03:29:03 -05:00
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else \
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2024-11-02 20:50:06 +01:00
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dat = (dev->vram[(addr) & (dev->vram_mask)]);
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2023-07-14 23:38:04 +02:00
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2025-02-01 03:29:03 -05:00
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#define READ_HIGH(addr, dat) \
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2024-11-02 20:50:06 +01:00
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dat |= (dev->vram[(addr) & (dev->vram_mask)] << 8);
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2024-10-26 21:32:47 +02:00
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2025-02-01 03:29:03 -05:00
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#define MIX(mixmode, dest_dat, src_dat) \
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{ \
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switch ((mixmode) ? (dev->accel.frgd_mix & 0x1f) : (dev->accel.bkgd_mix & 0x1f)) { \
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case 0x00: \
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dest_dat = ~dest_dat; \
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break; \
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case 0x01: \
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dest_dat = 0; \
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break; \
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case 0x02: \
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dest_dat = ~0; \
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break; \
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case 0x03: \
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dest_dat = dest_dat; \
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break; \
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case 0x04: \
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dest_dat = ~src_dat; \
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break; \
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case 0x05: \
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dest_dat = src_dat ^ dest_dat; \
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break; \
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case 0x06: \
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dest_dat = ~(src_dat ^ dest_dat); \
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break; \
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case 0x07: \
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dest_dat = src_dat; \
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break; \
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case 0x08: \
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dest_dat = ~(src_dat & dest_dat); \
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break; \
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case 0x09: \
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dest_dat = ~src_dat | dest_dat; \
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break; \
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case 0x0a: \
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dest_dat = src_dat | ~dest_dat; \
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break; \
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case 0x0b: \
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dest_dat = src_dat | dest_dat; \
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break; \
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case 0x0c: \
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dest_dat = src_dat & dest_dat; \
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break; \
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case 0x0d: \
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dest_dat = src_dat & ~dest_dat; \
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break; \
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case 0x0e: \
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dest_dat = ~src_dat & dest_dat; \
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break; \
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case 0x0f: \
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dest_dat = ~(src_dat | dest_dat); \
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break; \
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case 0x10: \
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dest_dat = MIN(src_dat, dest_dat); \
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break; \
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case 0x11: \
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|
|
dest_dat = dest_dat - src_dat; \
|
|
|
|
|
break; \
|
|
|
|
|
case 0x12: \
|
|
|
|
|
dest_dat = src_dat - dest_dat; \
|
|
|
|
|
break; \
|
|
|
|
|
case 0x13: \
|
|
|
|
|
dest_dat = src_dat + dest_dat; \
|
|
|
|
|
break; \
|
|
|
|
|
case 0x14: \
|
|
|
|
|
dest_dat = MAX(src_dat, dest_dat); \
|
|
|
|
|
break; \
|
|
|
|
|
case 0x15: \
|
|
|
|
|
dest_dat = (dest_dat - src_dat) / 2; \
|
|
|
|
|
break; \
|
|
|
|
|
case 0x16: \
|
|
|
|
|
dest_dat = (src_dat - dest_dat) / 2; \
|
|
|
|
|
break; \
|
|
|
|
|
case 0x17: \
|
|
|
|
|
dest_dat = (dest_dat + src_dat) / 2; \
|
|
|
|
|
break; \
|
|
|
|
|
case 0x18: \
|
|
|
|
|
dest_dat = MAX(0, (dest_dat - src_dat)); \
|
|
|
|
|
break; \
|
|
|
|
|
case 0x19: \
|
|
|
|
|
dest_dat = MAX(0, (dest_dat - src_dat)); \
|
|
|
|
|
break; \
|
|
|
|
|
case 0x1a: \
|
|
|
|
|
dest_dat = MAX(0, (src_dat - dest_dat)); \
|
|
|
|
|
break; \
|
|
|
|
|
case 0x1b: \
|
|
|
|
|
if (dev->bpp) \
|
|
|
|
|
dest_dat = MIN(0xffff, (dest_dat + src_dat)); \
|
|
|
|
|
else \
|
|
|
|
|
dest_dat = MIN(0xff, (dest_dat + src_dat)); \
|
|
|
|
|
break; \
|
|
|
|
|
case 0x1c: \
|
|
|
|
|
dest_dat = MAX(0, (dest_dat - src_dat)) / 2; \
|
|
|
|
|
break; \
|
|
|
|
|
case 0x1d: \
|
|
|
|
|
dest_dat = MAX(0, (dest_dat - src_dat)) / 2; \
|
|
|
|
|
break; \
|
|
|
|
|
case 0x1e: \
|
|
|
|
|
dest_dat = MAX(0, (src_dat - dest_dat)) / 2; \
|
|
|
|
|
break; \
|
|
|
|
|
case 0x1f: \
|
|
|
|
|
if (dev->bpp) \
|
2024-10-26 21:32:47 +02:00
|
|
|
dest_dat = (0xffff < (src_dat + dest_dat)) ? 0xffff : ((src_dat + dest_dat) / 2); \
|
2025-02-01 03:29:03 -05:00
|
|
|
else \
|
|
|
|
|
dest_dat = (0xff < (src_dat + dest_dat)) ? 0xff : ((src_dat + dest_dat) / 2); \
|
|
|
|
|
break; \
|
|
|
|
|
} \
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2025-02-01 03:29:03 -05:00
|
|
|
#define WRITE(addr, dat) \
|
|
|
|
|
if (dev->bpp) { \
|
|
|
|
|
vram_w[((addr)) & (dev->vram_mask >> 1)] = dat; \
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
dev->changedvram[(((addr)) & (dev->vram_mask >> 1)) >> 11] = changeframecount; \
|
2025-02-01 03:29:03 -05:00
|
|
|
} else { \
|
|
|
|
|
dev->vram[((addr)) & (dev->vram_mask)] = dat; \
|
|
|
|
|
dev->changedvram[(((addr)) & (dev->vram_mask)) >> 12] = changeframecount; \
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
mach_pixel_write(mach_t *mach)
|
|
|
|
|
{
|
|
|
|
|
if (mach->accel.dp_config & 1)
|
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
mach_pixel_read(mach_t *mach)
|
|
|
|
|
{
|
|
|
|
|
if (mach->accel.dp_config & 1)
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2025-01-26 15:15:53 -05:00
|
|
|
mach_accel_start(int cmd_type, int cpu_input, int count, uint32_t mix_dat, uint32_t cpu_dat, UNUSED(svga_t *svga), mach_t *mach, ibm8514_t *dev)
|
2023-07-14 23:38:04 +02:00
|
|
|
{
|
2023-08-11 20:32:56 -04:00
|
|
|
int compare_mode;
|
2024-01-05 21:22:01 +01:00
|
|
|
uint16_t poly_src = 0;
|
2023-08-11 20:32:56 -04:00
|
|
|
uint16_t rd_mask = dev->accel.rd_mask;
|
|
|
|
|
uint16_t wrt_mask = dev->accel.wrt_mask;
|
|
|
|
|
uint16_t dest_cmp_clr = dev->accel.color_cmp;
|
|
|
|
|
int frgd_sel;
|
|
|
|
|
int bkgd_sel;
|
|
|
|
|
int mono_src;
|
|
|
|
|
int compare = 0;
|
|
|
|
|
uint16_t src_dat = 0;
|
|
|
|
|
uint16_t dest_dat = 0;
|
|
|
|
|
uint16_t old_dest_dat;
|
|
|
|
|
uint16_t *vram_w = (uint16_t *) dev->vram;
|
|
|
|
|
uint16_t mix = 0;
|
|
|
|
|
uint32_t mono_dat0 = 0;
|
|
|
|
|
uint32_t mono_dat1 = 0;
|
2024-11-02 20:50:06 +01:00
|
|
|
int16_t clip_t = dev->accel.clip_top;
|
|
|
|
|
int16_t clip_l = dev->accel.clip_left;
|
|
|
|
|
int16_t clip_b = dev->accel.clip_bottom;
|
|
|
|
|
int16_t clip_r = dev->accel.clip_right;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (!dev->bpp) {
|
2023-07-14 23:38:04 +02:00
|
|
|
rd_mask &= 0xff;
|
|
|
|
|
dest_cmp_clr &= 0xff;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
compare_mode = (mach->accel.dest_cmp_fn >> 3) & 7;
|
2023-07-30 18:33:29 -04:00
|
|
|
frgd_sel = (mach->accel.dp_config >> 13) & 7;
|
|
|
|
|
bkgd_sel = (mach->accel.dp_config >> 7) & 3;
|
|
|
|
|
mono_src = (mach->accel.dp_config >> 5) & 3;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
|
|
|
|
if ((mono_src == 2) || (bkgd_sel == 2) || (frgd_sel == 2) || mach_pixel_read(mach)) {
|
2023-07-30 18:33:29 -04:00
|
|
|
mach->force_busy = 1;
|
|
|
|
|
dev->force_busy = 1;
|
|
|
|
|
dev->force_busy2 = 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (cpu_input) {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (dev->bpp) {
|
2024-10-26 21:32:47 +02:00
|
|
|
if ((mach->accel.dp_config & 0x200) && (count == 2))
|
2023-07-14 23:38:04 +02:00
|
|
|
count >>= 1;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if ((dev->accel_bpp == 8) || (dev->accel_bpp == 15) || (dev->accel_bpp == 16) || (dev->accel_bpp == 24))
|
2025-02-20 15:35:56 +01:00
|
|
|
mach_log("RdMask=%04x, DPCONFIG=%04x, Clipping: l=%d, r=%d, t=%d, b=%d, LineDrawOpt=%04x, BPP=%d, CMDType = %d, offs=%08x, cnt = %d, input = %d, mono_src = %d, frgdsel = %d, d(%d,%d), dstxend = %d, pitch = %d, extcrt = %d, rw = %x, monopattern = %x.\n",
|
2025-02-01 03:29:03 -05:00
|
|
|
dev->accel.rd_mask, mach->accel.dp_config, clip_l, clip_r, clip_t, clip_b, mach->accel.linedraw_opt, dev->accel_bpp, cmd_type, mach->accel.ge_offset, count, cpu_input, mono_src, frgd_sel, dev->accel.cur_x, dev->accel.cur_y,
|
|
|
|
|
mach->accel.dest_x_end, dev->ext_pitch, dev->ext_crt_pitch, mach->accel.dp_config & 1, mach->accel.mono_pattern_enable);
|
2023-07-14 23:38:04 +02:00
|
|
|
|
|
|
|
|
switch (cmd_type) {
|
|
|
|
|
case 1: /*Extended Raw Linedraw from bres_count register (0x96ee)*/
|
|
|
|
|
if (!cpu_input) {
|
|
|
|
|
dev->accel.dx = dev->accel.cur_x;
|
|
|
|
|
if (dev->accel.cur_x >= 0x600)
|
|
|
|
|
dev->accel.dx |= ~0x5ff;
|
2024-10-26 21:32:47 +02:00
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->accel.dy = dev->accel.cur_y;
|
|
|
|
|
if (dev->accel.cur_y >= 0x600)
|
|
|
|
|
dev->accel.dy |= ~0x5ff;
|
|
|
|
|
|
|
|
|
|
dev->accel.cx = dev->accel.destx_distp;
|
|
|
|
|
if (dev->accel.destx_distp >= 0x600)
|
|
|
|
|
dev->accel.cx |= ~0x5ff;
|
2024-10-26 21:32:47 +02:00
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->accel.cy = dev->accel.desty_axstp;
|
|
|
|
|
if (dev->accel.desty_axstp >= 0x600)
|
|
|
|
|
dev->accel.cy |= ~0x5ff;
|
|
|
|
|
|
2023-07-30 18:33:29 -04:00
|
|
|
mach->accel.width = mach->accel.bres_count;
|
|
|
|
|
dev->accel.sx = 0;
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.poly_fill = 0;
|
|
|
|
|
|
|
|
|
|
mach->accel.stepx = (mach->accel.linedraw_opt & 0x20) ? 1 : -1;
|
|
|
|
|
mach->accel.stepy = (mach->accel.linedraw_opt & 0x80) ? 1 : -1;
|
|
|
|
|
|
2025-02-01 03:29:03 -05:00
|
|
|
mach_log("Extended bresenham, CUR(%d,%d), DEST(%d,%d), width = %d, options = %04x, dpconfig = %04x, opt_ena = %03x.\n",
|
|
|
|
|
dev->accel.dx, dev->accel.dy, dev->accel.cx, dev->accel.cy, mach->accel.width, mach->accel.linedraw_opt,
|
|
|
|
|
mach->accel.dp_config, mach->accel.max_waitstates & 0x100);
|
2023-07-14 23:38:04 +02:00
|
|
|
|
|
|
|
|
if ((mono_src == 2) || (bkgd_sel == 2) || (frgd_sel == 2) || mach_pixel_read(mach)) {
|
|
|
|
|
if (mach_pixel_write(mach)) {
|
2023-07-30 18:33:29 -04:00
|
|
|
dev->data_available = 0;
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->data_available2 = 0;
|
|
|
|
|
return;
|
|
|
|
|
} else if (mach_pixel_read(mach)) {
|
2023-07-30 18:33:29 -04:00
|
|
|
dev->data_available = 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->data_available2 = 1;
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mono_src == 1) {
|
2024-10-26 21:32:47 +02:00
|
|
|
count = mach->accel.width;
|
|
|
|
|
mix_dat = mach->accel.mono_pattern_normal[0];
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->accel.temp_cnt = 8;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mach->accel.linedraw_opt & 0x08) { /*Vector Line*/
|
|
|
|
|
while (count--) {
|
|
|
|
|
switch (mono_src) {
|
|
|
|
|
case 0:
|
|
|
|
|
mix = 1;
|
|
|
|
|
break;
|
|
|
|
|
case 1:
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (!dev->accel.temp_cnt) {
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->accel.temp_cnt = 8;
|
|
|
|
|
mix_dat >>= 8;
|
|
|
|
|
}
|
2024-10-26 21:32:47 +02:00
|
|
|
mix = !!(mix_dat & 0x80);
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->accel.temp_cnt--;
|
|
|
|
|
mix_dat <<= 1;
|
|
|
|
|
mix_dat |= 1;
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
if (mach->accel.dp_config & 0x1000) {
|
|
|
|
|
mix = mix_dat >> 0x1f;
|
|
|
|
|
mix_dat <<= 1;
|
|
|
|
|
} else {
|
|
|
|
|
if (mach->accel.dp_config & 0x200) {
|
2024-10-26 21:32:47 +02:00
|
|
|
mix = mix_dat & 0x01;
|
2023-07-14 23:38:04 +02:00
|
|
|
mix_dat >>= 1;
|
|
|
|
|
} else {
|
2024-10-26 21:32:47 +02:00
|
|
|
mix = !!(mix_dat & 0x80);
|
2023-07-14 23:38:04 +02:00
|
|
|
mix_dat <<= 1;
|
|
|
|
|
mix_dat |= 1;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 3:
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (dev->bpp) {
|
|
|
|
|
READ((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), mix);
|
2023-07-14 23:38:04 +02:00
|
|
|
} else {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
READ((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), mix);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
mix = (mix & rd_mask) == rd_mask;
|
|
|
|
|
break;
|
2023-06-09 23:46:54 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if ((dev->accel.dx >= clip_l) &&
|
|
|
|
|
(dev->accel.dx <= clip_r) &&
|
|
|
|
|
(dev->accel.dy >= clip_t) &&
|
|
|
|
|
(dev->accel.dy <= clip_b)) {
|
2024-01-05 21:22:01 +01:00
|
|
|
switch (mix ? frgd_sel : bkgd_sel) {
|
|
|
|
|
case 0:
|
|
|
|
|
src_dat = dev->accel.bkgd_color;
|
|
|
|
|
break;
|
|
|
|
|
case 1:
|
|
|
|
|
src_dat = dev->accel.frgd_color;
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
src_dat = cpu_dat;
|
|
|
|
|
break;
|
|
|
|
|
case 3:
|
|
|
|
|
if (mach_pixel_read(mach))
|
|
|
|
|
src_dat = cpu_dat;
|
|
|
|
|
else {
|
|
|
|
|
if (dev->bpp) {
|
2024-10-26 21:32:47 +02:00
|
|
|
READ((mach->accel.ge_offset << 1) + (dev->accel.cy * dev->pitch) + dev->accel.cx, src_dat);
|
2024-01-05 21:22:01 +01:00
|
|
|
} else {
|
2024-10-26 21:32:47 +02:00
|
|
|
READ((mach->accel.ge_offset << 2) + (dev->accel.cy * dev->pitch) + dev->accel.cx, src_dat);
|
2024-01-05 21:22:01 +01:00
|
|
|
}
|
2024-10-26 21:32:47 +02:00
|
|
|
if (mono_src == 3)
|
2024-01-05 21:22:01 +01:00
|
|
|
src_dat = (src_dat & rd_mask) == rd_mask;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 5:
|
2024-10-26 21:32:47 +02:00
|
|
|
src_dat = mach->accel.color_pattern[mach->accel.color_pattern_idx];
|
|
|
|
|
if (dev->bpp)
|
|
|
|
|
src_dat |= (mach->accel.color_pattern[mach->accel.color_pattern_idx + 1] << 8);
|
2024-01-05 21:22:01 +01:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
if (mach->accel.linedraw_opt & 0x02) {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (dev->bpp) {
|
|
|
|
|
READ((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), poly_src);
|
2023-07-14 23:38:04 +02:00
|
|
|
} else {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
READ((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), poly_src);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
poly_src = ((poly_src & rd_mask) == rd_mask);
|
|
|
|
|
if (poly_src)
|
|
|
|
|
mach->accel.poly_fill = !mach->accel.poly_fill;
|
|
|
|
|
}
|
|
|
|
|
|
2024-01-05 21:22:01 +01:00
|
|
|
if (mach->accel.poly_fill || !(mach->accel.linedraw_opt & 0x02)) {
|
|
|
|
|
if (dev->bpp) {
|
|
|
|
|
READ((mach->accel.ge_offset << 1) + ((dev->accel.dy) * (dev->pitch)) + (dev->accel.dx), dest_dat);
|
|
|
|
|
} else {
|
|
|
|
|
READ((mach->accel.ge_offset << 2) + ((dev->accel.dy) * (dev->pitch)) + (dev->accel.dx), dest_dat);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
switch (compare_mode) {
|
2023-07-14 23:38:04 +02:00
|
|
|
case 1:
|
2024-01-05 21:22:01 +01:00
|
|
|
compare = 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 2:
|
2024-01-05 21:22:01 +01:00
|
|
|
compare = (dest_dat >= dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 3:
|
2024-01-05 21:22:01 +01:00
|
|
|
compare = (dest_dat < dest_cmp_clr) ? 0 : 1;
|
|
|
|
|
break;
|
|
|
|
|
case 4:
|
|
|
|
|
compare = (dest_dat != dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 5:
|
2024-01-05 21:22:01 +01:00
|
|
|
compare = (dest_dat == dest_cmp_clr) ? 0 : 1;
|
|
|
|
|
break;
|
|
|
|
|
case 6:
|
|
|
|
|
compare = (dest_dat <= dest_cmp_clr) ? 0 : 1;
|
|
|
|
|
break;
|
|
|
|
|
case 7:
|
|
|
|
|
compare = (dest_dat > dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
2023-06-09 23:46:54 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
2024-01-05 21:22:01 +01:00
|
|
|
if (!compare) {
|
|
|
|
|
if (mach_pixel_write(mach)) {
|
|
|
|
|
old_dest_dat = dest_dat;
|
|
|
|
|
MIX(mix, dest_dat, src_dat);
|
|
|
|
|
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
|
|
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
2024-01-05 21:22:01 +01:00
|
|
|
if (mach->accel.dp_config & 0x10) {
|
|
|
|
|
if (mach->accel.linedraw_opt & 0x04) {
|
|
|
|
|
if (((mono_src != 1) && (dev->accel.sx < mach->accel.width)) || ((mono_src == 1) && count)) {
|
|
|
|
|
if (dev->bpp) {
|
|
|
|
|
WRITE((mach->accel.ge_offset << 1) + ((dev->accel.dy) * (dev->pitch)) + (dev->accel.dx), dest_dat);
|
|
|
|
|
} else {
|
|
|
|
|
WRITE((mach->accel.ge_offset << 2) + ((dev->accel.dy) * (dev->pitch)) + (dev->accel.dx), dest_dat);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
} else {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (dev->bpp) {
|
|
|
|
|
WRITE((mach->accel.ge_offset << 1) + ((dev->accel.dy) * (dev->pitch)) + (dev->accel.dx), dest_dat);
|
2023-07-14 23:38:04 +02:00
|
|
|
} else {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
WRITE((mach->accel.ge_offset << 2) + ((dev->accel.dy) * (dev->pitch)) + (dev->accel.dx), dest_dat);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2024-11-02 20:50:06 +01:00
|
|
|
if ((mono_src == 1) && !count) {
|
|
|
|
|
dev->accel.cmd_back = 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
2024-11-02 20:50:06 +01:00
|
|
|
} else if ((mono_src != 1) && (dev->accel.sx >= mach->accel.width)) {
|
|
|
|
|
dev->accel.cmd_back = 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
2024-11-02 20:50:06 +01:00
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (dev->bpp)
|
2023-07-14 23:38:04 +02:00
|
|
|
cpu_dat >>= 16;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
else
|
|
|
|
|
cpu_dat >>= 8;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if (dev->bpp)
|
|
|
|
|
mach->accel.color_pattern_idx += 2;
|
|
|
|
|
else
|
|
|
|
|
mach->accel.color_pattern_idx++;
|
|
|
|
|
|
|
|
|
|
if (mach->accel.color_pattern_idx > mach->accel.patt_len)
|
|
|
|
|
mach->accel.color_pattern_idx = 0;
|
|
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
switch (mach->accel.linedraw_opt & 0xe0) {
|
|
|
|
|
case 0x00:
|
|
|
|
|
dev->accel.cx++;
|
|
|
|
|
dev->accel.dx++;
|
|
|
|
|
break;
|
|
|
|
|
case 0x20:
|
|
|
|
|
dev->accel.cx++;
|
|
|
|
|
dev->accel.dx++;
|
|
|
|
|
dev->accel.cy--;
|
|
|
|
|
dev->accel.dy--;
|
|
|
|
|
break;
|
|
|
|
|
case 0x40:
|
|
|
|
|
dev->accel.cy--;
|
|
|
|
|
dev->accel.dy--;
|
|
|
|
|
break;
|
|
|
|
|
case 0x60:
|
|
|
|
|
dev->accel.cx--;
|
|
|
|
|
dev->accel.dx--;
|
|
|
|
|
dev->accel.cy--;
|
|
|
|
|
dev->accel.dy--;
|
|
|
|
|
break;
|
|
|
|
|
case 0x80:
|
|
|
|
|
dev->accel.cx--;
|
|
|
|
|
dev->accel.dx--;
|
|
|
|
|
break;
|
|
|
|
|
case 0xa0:
|
|
|
|
|
dev->accel.cx--;
|
|
|
|
|
dev->accel.dx--;
|
|
|
|
|
dev->accel.cy++;
|
|
|
|
|
dev->accel.dy++;
|
|
|
|
|
break;
|
|
|
|
|
case 0xc0:
|
|
|
|
|
dev->accel.cy++;
|
|
|
|
|
dev->accel.dy++;
|
|
|
|
|
break;
|
|
|
|
|
case 0xe0:
|
|
|
|
|
dev->accel.cx++;
|
|
|
|
|
dev->accel.dx++;
|
|
|
|
|
dev->accel.cy++;
|
|
|
|
|
dev->accel.dy++;
|
|
|
|
|
break;
|
2023-06-09 23:46:54 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dev->accel.sx++;
|
|
|
|
|
}
|
|
|
|
|
} else { /*Bresenham*/
|
|
|
|
|
while (count--) {
|
|
|
|
|
switch (mono_src) {
|
|
|
|
|
case 0:
|
|
|
|
|
mix = 1;
|
|
|
|
|
break;
|
|
|
|
|
case 1:
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (!dev->accel.temp_cnt) {
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->accel.temp_cnt = 8;
|
|
|
|
|
mix_dat >>= 8;
|
|
|
|
|
}
|
|
|
|
|
mix = (mix_dat & 0x80);
|
|
|
|
|
dev->accel.temp_cnt--;
|
|
|
|
|
mix_dat <<= 1;
|
|
|
|
|
mix_dat |= 1;
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
if (mach->accel.dp_config & 0x1000) {
|
|
|
|
|
mix = mix_dat >> 0x1f;
|
|
|
|
|
mix_dat <<= 1;
|
|
|
|
|
} else {
|
|
|
|
|
if (mach->accel.dp_config & 0x200) {
|
|
|
|
|
mix = mix_dat & 1;
|
|
|
|
|
mix_dat >>= 1;
|
|
|
|
|
} else {
|
|
|
|
|
mix = mix_dat & 0x80;
|
|
|
|
|
mix_dat <<= 1;
|
|
|
|
|
mix_dat |= 1;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 3:
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (dev->bpp) {
|
|
|
|
|
READ((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), mix);
|
2023-07-14 23:38:04 +02:00
|
|
|
} else {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
READ((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), mix);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
mix = (mix & rd_mask) == rd_mask;
|
|
|
|
|
break;
|
2023-06-09 23:46:54 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if ((dev->accel.dx >= clip_l) &&
|
|
|
|
|
(dev->accel.dx <= clip_r) &&
|
|
|
|
|
(dev->accel.dy >= clip_t) &&
|
|
|
|
|
(dev->accel.dy <= clip_b)) {
|
2024-01-05 21:22:01 +01:00
|
|
|
switch (mix ? frgd_sel : bkgd_sel) {
|
|
|
|
|
case 0:
|
|
|
|
|
src_dat = dev->accel.bkgd_color;
|
|
|
|
|
break;
|
|
|
|
|
case 1:
|
|
|
|
|
src_dat = dev->accel.frgd_color;
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
src_dat = cpu_dat;
|
|
|
|
|
break;
|
|
|
|
|
case 3:
|
|
|
|
|
if (mach_pixel_read(mach))
|
|
|
|
|
src_dat = cpu_dat;
|
|
|
|
|
else {
|
|
|
|
|
if (dev->bpp) {
|
|
|
|
|
READ((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), src_dat);
|
|
|
|
|
} else {
|
|
|
|
|
READ((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), src_dat);
|
|
|
|
|
}
|
|
|
|
|
if (mono_src == 3) {
|
|
|
|
|
src_dat = (src_dat & rd_mask) == rd_mask;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 5:
|
2024-10-26 21:32:47 +02:00
|
|
|
src_dat = mach->accel.color_pattern[mach->accel.color_pattern_idx];
|
|
|
|
|
if (dev->bpp)
|
|
|
|
|
src_dat |= (mach->accel.color_pattern[mach->accel.color_pattern_idx + 1] << 8);
|
2024-01-05 21:22:01 +01:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
if (mach->accel.linedraw_opt & 0x02) {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (dev->bpp) {
|
|
|
|
|
READ((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), poly_src);
|
2023-07-14 23:38:04 +02:00
|
|
|
} else {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
READ((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), poly_src);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
poly_src = ((poly_src & rd_mask) == rd_mask);
|
|
|
|
|
if (poly_src)
|
|
|
|
|
mach->accel.poly_fill = !mach->accel.poly_fill;
|
|
|
|
|
}
|
|
|
|
|
|
2024-01-05 21:22:01 +01:00
|
|
|
if (mach->accel.poly_fill || !(mach->accel.linedraw_opt & 0x02)) {
|
|
|
|
|
if (dev->bpp) {
|
|
|
|
|
READ((mach->accel.ge_offset << 1) + ((dev->accel.dy) * (dev->pitch)) + (dev->accel.dx), dest_dat);
|
|
|
|
|
} else {
|
|
|
|
|
READ((mach->accel.ge_offset << 2) + ((dev->accel.dy) * (dev->pitch)) + (dev->accel.dx), dest_dat);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
switch (compare_mode) {
|
2023-07-14 23:38:04 +02:00
|
|
|
case 1:
|
2024-01-05 21:22:01 +01:00
|
|
|
compare = 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 2:
|
2024-01-05 21:22:01 +01:00
|
|
|
compare = (dest_dat >= dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 3:
|
2024-01-05 21:22:01 +01:00
|
|
|
compare = (dest_dat < dest_cmp_clr) ? 0 : 1;
|
|
|
|
|
break;
|
|
|
|
|
case 4:
|
|
|
|
|
compare = (dest_dat != dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 5:
|
2024-01-05 21:22:01 +01:00
|
|
|
compare = (dest_dat == dest_cmp_clr) ? 0 : 1;
|
|
|
|
|
break;
|
|
|
|
|
case 6:
|
|
|
|
|
compare = (dest_dat <= dest_cmp_clr) ? 0 : 1;
|
|
|
|
|
break;
|
|
|
|
|
case 7:
|
|
|
|
|
compare = (dest_dat > dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
2023-06-09 23:46:54 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
2024-01-05 21:22:01 +01:00
|
|
|
if (!compare) {
|
|
|
|
|
if (mach_pixel_write(mach)) {
|
|
|
|
|
old_dest_dat = dest_dat;
|
|
|
|
|
MIX(mix, dest_dat, src_dat);
|
|
|
|
|
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
|
|
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
2024-01-05 21:22:01 +01:00
|
|
|
if (mach->accel.dp_config & 0x10) {
|
|
|
|
|
if (mach->accel.linedraw_opt & 0x04) {
|
|
|
|
|
if (((mono_src != 1) && (dev->accel.sx < mach->accel.width)) || ((mono_src == 1) && count)) {
|
|
|
|
|
if (dev->bpp) {
|
|
|
|
|
WRITE((mach->accel.ge_offset << 1) + ((dev->accel.dy) * (dev->pitch)) + (dev->accel.dx), dest_dat);
|
|
|
|
|
} else {
|
|
|
|
|
WRITE((mach->accel.ge_offset << 2) + ((dev->accel.dy) * (dev->pitch)) + (dev->accel.dx), dest_dat);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
} else {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (dev->bpp) {
|
|
|
|
|
WRITE((mach->accel.ge_offset << 1) + ((dev->accel.dy) * (dev->pitch)) + (dev->accel.dx), dest_dat);
|
2023-07-14 23:38:04 +02:00
|
|
|
} else {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
WRITE((mach->accel.ge_offset << 2) + ((dev->accel.dy) * (dev->pitch)) + (dev->accel.dx), dest_dat);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2024-11-02 20:50:06 +01:00
|
|
|
if ((mono_src == 1) && !count) {
|
|
|
|
|
dev->accel.cmd_back = 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
2024-11-02 20:50:06 +01:00
|
|
|
} else if ((mono_src != 1) && (dev->accel.sx >= mach->accel.width)) {
|
|
|
|
|
dev->accel.cmd_back = 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
2024-11-02 20:50:06 +01:00
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (dev->bpp)
|
2023-07-14 23:38:04 +02:00
|
|
|
cpu_dat >>= 16;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
else
|
|
|
|
|
cpu_dat >>= 8;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if (dev->bpp)
|
|
|
|
|
mach->accel.color_pattern_idx += 2;
|
|
|
|
|
else
|
|
|
|
|
mach->accel.color_pattern_idx++;
|
|
|
|
|
|
|
|
|
|
if (mach->accel.color_pattern_idx > mach->accel.patt_len)
|
|
|
|
|
mach->accel.color_pattern_idx = 0;
|
|
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
if (mach->accel.linedraw_opt & 0x40) {
|
|
|
|
|
dev->accel.dy += mach->accel.stepy;
|
|
|
|
|
if ((frgd_sel == 3) || (bkgd_sel == 3))
|
|
|
|
|
dev->accel.cy += mach->accel.stepy;
|
|
|
|
|
|
|
|
|
|
if (dev->accel.err_term >= 0) {
|
|
|
|
|
dev->accel.err_term += dev->accel.destx_distp;
|
|
|
|
|
dev->accel.dx += mach->accel.stepx;
|
|
|
|
|
if ((frgd_sel == 3) || (bkgd_sel == 3))
|
|
|
|
|
dev->accel.cx += mach->accel.stepx;
|
|
|
|
|
} else {
|
|
|
|
|
dev->accel.err_term += dev->accel.desty_axstp;
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
dev->accel.dx += mach->accel.stepx;
|
|
|
|
|
if ((frgd_sel == 3) || (bkgd_sel == 3))
|
|
|
|
|
dev->accel.cx += mach->accel.stepx;
|
|
|
|
|
|
|
|
|
|
if (dev->accel.err_term >= 0) {
|
|
|
|
|
dev->accel.err_term += dev->accel.destx_distp;
|
|
|
|
|
dev->accel.dy += mach->accel.stepy;
|
|
|
|
|
if ((frgd_sel == 3) || (bkgd_sel == 3))
|
|
|
|
|
dev->accel.cy += mach->accel.stepy;
|
|
|
|
|
} else {
|
|
|
|
|
dev->accel.err_term += dev->accel.desty_axstp;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dev->accel.sx++;
|
|
|
|
|
}
|
|
|
|
|
}
|
2024-01-05 21:22:01 +01:00
|
|
|
mach->accel.poly_fill = 0;
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->accel.cur_x = dev->accel.dx;
|
|
|
|
|
dev->accel.cur_y = dev->accel.dy;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 2: /*Non-conforming BitBLT from dest_y_end register (0xaeee)*/
|
|
|
|
|
if (!cpu_input) {
|
|
|
|
|
mach->accel.stepx = 0;
|
|
|
|
|
mach->accel.stepy = 0;
|
|
|
|
|
|
|
|
|
|
dev->accel.dx = dev->accel.cur_x;
|
|
|
|
|
if (dev->accel.cur_x >= 0x600)
|
|
|
|
|
dev->accel.dx |= ~0x5ff;
|
|
|
|
|
|
|
|
|
|
dev->accel.dy = dev->accel.cur_y;
|
|
|
|
|
if (dev->accel.cur_y >= 0x600)
|
|
|
|
|
dev->accel.dy |= ~0x5ff;
|
|
|
|
|
|
|
|
|
|
/*Destination Width*/
|
|
|
|
|
mach->accel.dx_start = mach->accel.dest_x_start;
|
|
|
|
|
if (mach->accel.dest_x_start >= 0x600)
|
|
|
|
|
mach->accel.dx_start |= ~0x5ff;
|
|
|
|
|
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_log("DXStart=%d, CURX=%d.\n", mach->accel.dx_start, dev->accel.dx);
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.dx_end = mach->accel.dest_x_end;
|
|
|
|
|
if (mach->accel.dest_x_end >= 0x600)
|
|
|
|
|
mach->accel.dx_end |= ~0x5ff;
|
|
|
|
|
|
|
|
|
|
if (mach->accel.dx_end > mach->accel.dx_start) {
|
|
|
|
|
mach->accel.width = (mach->accel.dx_end - mach->accel.dx_start);
|
|
|
|
|
mach->accel.stepx = 1;
|
|
|
|
|
} else if (mach->accel.dx_end < mach->accel.dx_start) {
|
|
|
|
|
mach->accel.width = (mach->accel.dx_start - mach->accel.dx_end);
|
|
|
|
|
mach->accel.stepx = -1;
|
|
|
|
|
if (dev->accel.dx > 0)
|
|
|
|
|
dev->accel.dx--;
|
2025-02-01 03:29:03 -05:00
|
|
|
mach_log("BitBLT: Dst Negative X, dxstart = %d, end = %d, width = %d, dx = %d, dpconfig = %04x.\n",
|
|
|
|
|
mach->accel.dest_x_start, mach->accel.dest_x_end, mach->accel.width, dev->accel.dx,
|
|
|
|
|
mach->accel.dp_config);
|
2023-07-14 23:38:04 +02:00
|
|
|
} else {
|
|
|
|
|
mach->accel.stepx = 1;
|
|
|
|
|
mach->accel.width = 0;
|
2025-02-01 03:29:03 -05:00
|
|
|
mach_log("BitBLT: Dst Indeterminate X, dpconfig = %04x, destxend = %d, destxstart = %d.\n",
|
|
|
|
|
mach->accel.dp_config, mach->accel.dest_x_end, mach->accel.dest_x_start);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
dev->accel.sx = 0;
|
|
|
|
|
mach->accel.poly_fill = 0;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
|
|
|
|
/*Height*/
|
|
|
|
|
mach->accel.dy_start = dev->accel.cur_y;
|
|
|
|
|
if (dev->accel.cur_y >= 0x600)
|
|
|
|
|
mach->accel.dy_start |= ~0x5ff;
|
2024-10-27 23:36:11 +01:00
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.dy_end = mach->accel.dest_y_end;
|
|
|
|
|
if (mach->accel.dest_y_end >= 0x600)
|
|
|
|
|
mach->accel.dy_end |= ~0x5ff;
|
|
|
|
|
|
|
|
|
|
if (mach->accel.dy_end > mach->accel.dy_start) {
|
|
|
|
|
mach->accel.height = (mach->accel.dy_end - mach->accel.dy_start);
|
2023-07-30 18:33:29 -04:00
|
|
|
mach->accel.stepy = 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
} else if (mach->accel.dy_end < mach->accel.dy_start) {
|
|
|
|
|
mach->accel.height = (mach->accel.dy_start - mach->accel.dy_end);
|
2023-07-30 18:33:29 -04:00
|
|
|
mach->accel.stepy = -1;
|
2023-07-14 23:38:04 +02:00
|
|
|
} else {
|
|
|
|
|
mach->accel.height = 0;
|
2023-07-30 18:33:29 -04:00
|
|
|
mach->accel.stepy = 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dev->accel.sy = 0;
|
2024-10-26 21:32:47 +02:00
|
|
|
if (mach->accel.dp_config & 0x02)
|
|
|
|
|
dev->accel.dest = (dev->accel.dy * dev->pitch);
|
|
|
|
|
else {
|
|
|
|
|
if (dev->bpp)
|
|
|
|
|
dev->accel.dest = (mach->accel.ge_offset << 1) + (dev->accel.dy * dev->pitch);
|
|
|
|
|
else
|
|
|
|
|
dev->accel.dest = (mach->accel.ge_offset << 2) + (dev->accel.dy * dev->pitch);
|
|
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
|
|
|
|
|
mach->accel.src_stepx = 0;
|
|
|
|
|
/*Source Width*/
|
|
|
|
|
dev->accel.cx = mach->accel.src_x;
|
|
|
|
|
if (mach->accel.src_x >= 0x600)
|
|
|
|
|
dev->accel.cx |= ~0x5ff;
|
|
|
|
|
|
|
|
|
|
dev->accel.cy = mach->accel.src_y;
|
|
|
|
|
if (mach->accel.src_y >= 0x600)
|
|
|
|
|
dev->accel.cy |= ~0x5ff;
|
|
|
|
|
|
|
|
|
|
mach->accel.sx_start = mach->accel.src_x_start;
|
|
|
|
|
if (mach->accel.src_x_start >= 0x600)
|
|
|
|
|
mach->accel.sx_start |= ~0x5ff;
|
|
|
|
|
|
|
|
|
|
mach->accel.sx_end = mach->accel.src_x_end;
|
|
|
|
|
if (mach->accel.src_x_end >= 0x600)
|
|
|
|
|
mach->accel.sx_end |= ~0x5ff;
|
|
|
|
|
|
|
|
|
|
if (mach->accel.sx_end > mach->accel.sx_start) {
|
|
|
|
|
mach->accel.src_width = (mach->accel.sx_end - mach->accel.sx_start);
|
|
|
|
|
mach->accel.src_stepx = 1;
|
2025-02-01 03:29:03 -05:00
|
|
|
mach_log("BitBLT: Src Positive X: wh(%d,%d), srcwidth = %d, coordinates: %d,%d px, start: %d, end: %d px, stepx = %d, dpconfig = %04x, oddwidth = %d.\n",
|
|
|
|
|
mach->accel.width, mach->accel.height, mach->accel.src_width, dev->accel.cx, dev->accel.cy, mach->accel.src_x_start, mach->accel.src_x_end,
|
|
|
|
|
mach->accel.src_stepx, mach->accel.dp_config, mach->accel.src_width & 1);
|
2023-07-14 23:38:04 +02:00
|
|
|
} else if (mach->accel.sx_end < mach->accel.sx_start) {
|
|
|
|
|
mach->accel.src_width = (mach->accel.sx_start - mach->accel.sx_end);
|
|
|
|
|
mach->accel.src_stepx = -1;
|
|
|
|
|
if (dev->accel.cx > 0)
|
|
|
|
|
dev->accel.cx--;
|
2025-02-01 03:29:03 -05:00
|
|
|
mach_log("BitBLT: Src Negative X: width = %d, coordinates: %d,%d px, end: %d px, stepx = %d, dpconfig = %04x, oddwidth = %d.\n",
|
|
|
|
|
mach->accel.src_width, dev->accel.cx, dev->accel.cy, mach->accel.src_x_end, mach->accel.src_stepx, mach->accel.dp_config
|
|
|
|
|
mach->accel.src_width & 1);
|
2023-07-14 23:38:04 +02:00
|
|
|
} else {
|
|
|
|
|
mach->accel.src_stepx = 1;
|
|
|
|
|
mach->accel.src_width = 0;
|
2025-02-01 03:29:03 -05:00
|
|
|
mach_log("BitBLT: Src Indeterminate X: width = %d, coordinates: %d,%d px, end: %d px, stepx = %d, dpconfig = %04x, oddwidth = %d.\n",
|
|
|
|
|
mach->accel.src_width, dev->accel.cx, dev->accel.cy, mach->accel.src_x_end, mach->accel.src_stepx,
|
|
|
|
|
mach->accel.dp_config, mach->accel.src_width & 1);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
mach->accel.sx = 0;
|
2024-10-26 21:32:47 +02:00
|
|
|
if (mach->accel.patt_data_idx < 16)
|
|
|
|
|
mach->accel.color_pattern_idx = mach->accel.patt_idx;
|
2023-07-14 23:38:04 +02:00
|
|
|
else
|
2024-10-26 21:32:47 +02:00
|
|
|
mach->accel.color_pattern_idx = 0;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if (dev->bpp)
|
|
|
|
|
dev->accel.src = (mach->accel.ge_offset << 1) + (dev->accel.cy * dev->pitch);
|
|
|
|
|
else
|
|
|
|
|
dev->accel.src = (mach->accel.ge_offset << 2) + (dev->accel.cy * dev->pitch);
|
2023-07-14 23:38:04 +02:00
|
|
|
|
|
|
|
|
if (mono_src == 1) {
|
2024-10-26 21:32:47 +02:00
|
|
|
if (mach->accel.mono_pattern_enable || mach->accel.block_write_mono_pattern_enable) {
|
|
|
|
|
mono_dat0 = mach->accel.mono_pattern_normal[0];
|
|
|
|
|
mono_dat0 |= (mach->accel.mono_pattern_normal[1] << 8);
|
|
|
|
|
mono_dat0 |= (mach->accel.mono_pattern_normal[2] << 16);
|
|
|
|
|
mono_dat0 |= (mach->accel.mono_pattern_normal[3] << 24);
|
|
|
|
|
mono_dat1 = mach->accel.mono_pattern_normal[4];
|
|
|
|
|
mono_dat1 |= (mach->accel.mono_pattern_normal[5] << 8);
|
|
|
|
|
mono_dat1 |= (mach->accel.mono_pattern_normal[6] << 16);
|
|
|
|
|
mono_dat1 |= (mach->accel.mono_pattern_normal[7] << 24);
|
|
|
|
|
|
|
|
|
|
mach_log("MonoData0=%x, MonoData1=%x.\n", mono_dat0, mono_dat1);
|
2023-07-14 23:38:04 +02:00
|
|
|
for (uint8_t y = 0; y < 8; y++) {
|
|
|
|
|
for (uint8_t x = 0; x < 8; x++) {
|
2023-07-30 18:33:29 -04:00
|
|
|
uint32_t temp = (y & 4) ? mono_dat1 : mono_dat0;
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.mono_pattern[y][7 - x] = (temp >> (x + ((y & 3) << 3))) & 1;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if ((mono_src == 2) || (bkgd_sel == 2) || (frgd_sel == 2) || mach_pixel_read(mach)) {
|
|
|
|
|
if (mach_pixel_write(mach)) {
|
2023-07-30 18:33:29 -04:00
|
|
|
dev->data_available = 0;
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->data_available2 = 0;
|
|
|
|
|
return;
|
|
|
|
|
} else if (mach_pixel_read(mach)) {
|
2023-07-30 18:33:29 -04:00
|
|
|
dev->data_available = 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->data_available2 = 1;
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mono_src == 1) {
|
2024-10-26 21:32:47 +02:00
|
|
|
if (!mach->accel.mono_pattern_enable && !mach->accel.block_write_mono_pattern_enable) {
|
|
|
|
|
if (((dev->accel_bpp == 24) && (frgd_sel != 5)) || (dev->accel_bpp != 24)) {
|
|
|
|
|
mix_dat = mach->accel.mono_pattern_normal[0] ^ ((mach->accel.patt_idx & 0x01) ? 0xff : 0);
|
|
|
|
|
dev->accel.temp_cnt = 8;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2023-06-09 23:46:54 -04:00
|
|
|
if (mach->accel.dy_end == mach->accel.dy_start) {
|
2023-07-14 23:38:04 +02:00
|
|
|
mach_log("No DEST.\n");
|
2024-11-02 20:50:06 +01:00
|
|
|
dev->accel.cmd_back = 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if ((mono_src == 3) || (bkgd_sel == 3) || (frgd_sel == 3)) {
|
|
|
|
|
if (mach->accel.sx_end == mach->accel.sx_start) {
|
|
|
|
|
mach_log("No SRC.\n");
|
2024-11-02 20:50:06 +01:00
|
|
|
dev->accel.cmd_back = 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (cpu_input) {
|
|
|
|
|
if (mach->accel.dp_config == 0x3251) {
|
2025-02-01 03:29:03 -05:00
|
|
|
mach_log("DPCONFIG 3251: monosrc=%d, frgdsel=%d, bkgdsel=%d, pitch=%d.\n",
|
|
|
|
|
mono_src, frgd_sel, bkgd_sel, dev->pitch);
|
2024-10-27 23:36:11 +01:00
|
|
|
if (dev->accel.sy == mach->accel.height) {
|
|
|
|
|
mach_log("No Blit on DPCONFIG=3251.\n");
|
2024-11-02 20:50:06 +01:00
|
|
|
dev->accel.cmd_back = 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
return;
|
2024-10-27 23:36:11 +01:00
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
while (count--) {
|
|
|
|
|
switch (mono_src) {
|
|
|
|
|
case 0:
|
2024-10-26 21:32:47 +02:00
|
|
|
mix = 0x01;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 1:
|
2024-10-26 21:32:47 +02:00
|
|
|
if (mach->accel.mono_pattern_enable || mach->accel.block_write_mono_pattern_enable)
|
2023-07-14 23:38:04 +02:00
|
|
|
mix = mach->accel.mono_pattern[dev->accel.dy & 7][dev->accel.dx & 7];
|
2024-10-26 21:32:47 +02:00
|
|
|
else if ((dev->accel_bpp == 24) && (frgd_sel == 5))
|
|
|
|
|
mix = 0x01;
|
2023-11-08 23:47:16 +01:00
|
|
|
else {
|
2024-10-26 21:32:47 +02:00
|
|
|
if (!dev->accel.temp_cnt) {
|
|
|
|
|
dev->accel.temp_cnt = 8;
|
|
|
|
|
mix_dat >>= 8;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
2024-10-26 21:32:47 +02:00
|
|
|
mix = !!(mix_dat & 0x80);
|
|
|
|
|
dev->accel.temp_cnt--;
|
|
|
|
|
mix_dat <<= 1;
|
|
|
|
|
mix_dat |= 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
2025-02-20 15:35:56 +01:00
|
|
|
if ((mach->accel.dp_config & 0x1000) || (mach->accel.dp_config & 0x04)) {
|
2023-07-14 23:38:04 +02:00
|
|
|
mix = mix_dat >> 0x1f;
|
|
|
|
|
mix_dat <<= 1;
|
|
|
|
|
} else {
|
|
|
|
|
if (mach->accel.dp_config & 0x200) {
|
2024-10-26 21:32:47 +02:00
|
|
|
mix = mix_dat & 0x01;
|
2023-07-14 23:38:04 +02:00
|
|
|
mix_dat >>= 1;
|
|
|
|
|
} else {
|
2024-10-26 21:32:47 +02:00
|
|
|
mix = !!(mix_dat & 0x80);
|
2023-07-14 23:38:04 +02:00
|
|
|
mix_dat <<= 1;
|
|
|
|
|
mix_dat |= 1;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 3:
|
2023-12-06 15:00:31 +01:00
|
|
|
READ(dev->accel.src + dev->accel.cx, mix);
|
2023-07-14 23:38:04 +02:00
|
|
|
mix = (mix & rd_mask) == rd_mask;
|
|
|
|
|
break;
|
2023-06-09 23:46:54 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if ((dev->accel.dx >= clip_l) &&
|
|
|
|
|
(dev->accel.dx <= clip_r) &&
|
|
|
|
|
(dev->accel.dy >= clip_t) &&
|
|
|
|
|
(dev->accel.dy <= clip_b)) {
|
|
|
|
|
if (mach->accel.dp_config & 0x02) {
|
2024-01-05 21:22:01 +01:00
|
|
|
READ(dev->accel.src + dev->accel.cx, poly_src);
|
2023-07-14 23:38:04 +02:00
|
|
|
poly_src = ((poly_src & rd_mask) == rd_mask);
|
|
|
|
|
if (poly_src)
|
2024-01-05 21:22:01 +01:00
|
|
|
mach->accel.poly_fill ^= 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if (mach->accel.poly_fill || !(mach->accel.dp_config & 0x02)) {
|
2023-07-14 23:38:04 +02:00
|
|
|
switch (mix ? frgd_sel : bkgd_sel) {
|
|
|
|
|
case 0:
|
|
|
|
|
src_dat = dev->accel.bkgd_color;
|
|
|
|
|
break;
|
|
|
|
|
case 1:
|
|
|
|
|
src_dat = dev->accel.frgd_color;
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
src_dat = cpu_dat;
|
|
|
|
|
break;
|
|
|
|
|
case 3:
|
|
|
|
|
if (mach_pixel_read(mach))
|
|
|
|
|
src_dat = cpu_dat;
|
|
|
|
|
else {
|
2024-01-05 21:22:01 +01:00
|
|
|
READ(dev->accel.src + dev->accel.cx, src_dat);
|
2023-11-08 23:47:16 +01:00
|
|
|
if (mono_src == 3)
|
2023-07-14 23:38:04 +02:00
|
|
|
src_dat = (src_dat & rd_mask) == rd_mask;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 5:
|
2024-10-26 21:32:47 +02:00
|
|
|
src_dat = mach->accel.color_pattern[mach->accel.color_pattern_idx];
|
|
|
|
|
if (dev->bpp)
|
|
|
|
|
src_dat |= (mach->accel.color_pattern[mach->accel.color_pattern_idx + 1] << 8);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
2023-06-09 23:46:54 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if ((dev->accel_bpp == 24) && (mono_src == 1) && (frgd_sel == 5) && !mach->accel.mono_pattern_enable) {
|
2024-01-05 21:22:01 +01:00
|
|
|
if (dev->accel.sy & 1) {
|
2024-10-26 21:32:47 +02:00
|
|
|
READ(dev->accel.dest + dev->accel.dx - dev->pitch, dest_dat);
|
2024-01-05 21:22:01 +01:00
|
|
|
} else {
|
|
|
|
|
READ(dev->accel.dest + dev->accel.dx, dest_dat);
|
|
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
} else {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
READ(dev->accel.dest + dev->accel.dx, dest_dat);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
2024-01-05 21:22:01 +01:00
|
|
|
switch (compare_mode) {
|
|
|
|
|
case 1:
|
|
|
|
|
compare = 1;
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
compare = (dest_dat >= dest_cmp_clr) ? 0 : 1;
|
|
|
|
|
break;
|
|
|
|
|
case 3:
|
|
|
|
|
compare = (dest_dat < dest_cmp_clr) ? 0 : 1;
|
|
|
|
|
break;
|
|
|
|
|
case 4:
|
|
|
|
|
compare = (dest_dat != dest_cmp_clr) ? 0 : 1;
|
|
|
|
|
break;
|
|
|
|
|
case 5:
|
|
|
|
|
compare = (dest_dat == dest_cmp_clr) ? 0 : 1;
|
|
|
|
|
break;
|
|
|
|
|
case 6:
|
|
|
|
|
compare = (dest_dat <= dest_cmp_clr) ? 0 : 1;
|
|
|
|
|
break;
|
|
|
|
|
case 7:
|
|
|
|
|
compare = (dest_dat > dest_cmp_clr) ? 0 : 1;
|
|
|
|
|
break;
|
2023-06-09 23:46:54 -04:00
|
|
|
|
2024-01-05 21:22:01 +01:00
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
|
2024-01-05 21:22:01 +01:00
|
|
|
if (!compare) {
|
|
|
|
|
if (mach_pixel_write(mach)) {
|
|
|
|
|
old_dest_dat = dest_dat;
|
|
|
|
|
MIX(mix, dest_dat, src_dat);
|
|
|
|
|
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
|
|
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
2024-01-05 21:22:01 +01:00
|
|
|
if (mach->accel.dp_config & 0x10) {
|
2024-11-02 20:50:06 +01:00
|
|
|
if ((dev->accel_bpp == 24) && (mono_src == 1) && (frgd_sel == 5) && !mach->accel.mono_pattern_enable) {
|
|
|
|
|
if (dev->accel.sy & 1) {
|
|
|
|
|
WRITE(dev->accel.dest + dev->accel.dx - dev->pitch, dest_dat);
|
2024-10-26 21:32:47 +02:00
|
|
|
} else {
|
|
|
|
|
WRITE(dev->accel.dest + dev->accel.dx, dest_dat);
|
|
|
|
|
}
|
2024-11-02 20:50:06 +01:00
|
|
|
} else {
|
|
|
|
|
WRITE(dev->accel.dest + dev->accel.dx, dest_dat);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (dev->bpp)
|
2023-07-14 23:38:04 +02:00
|
|
|
cpu_dat >>= 16;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
else
|
|
|
|
|
cpu_dat >>= 8;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if (mach->accel.dp_config == 0x2071 || (mach->accel.dp_config == 0x2011))
|
2025-02-01 03:29:03 -05:00
|
|
|
mach_log("FontBlit: SX=%d, C(%d,%d), SRCWidth=%d, frgdmix=%d, bkgdmix=%d, rdmask=%04x, D(%d,%d), geoffset=%x, addr=%08x,.\n",
|
|
|
|
|
mach->accel.sx, dev->accel.cx, dev->accel.cy, mach->accel.src_width, dev->accel.frgd_mix & 0x1f,
|
|
|
|
|
dev->accel.bkgd_mix & 0x1f, rd_mask, dev->accel.dx, dev->accel.dy, dev->accel.ge_offset,
|
|
|
|
|
(dev->accel.src + dev->accel.cx) & dev->vram_mask);
|
2024-10-26 21:32:47 +02:00
|
|
|
|
2024-01-05 21:22:01 +01:00
|
|
|
if ((mono_src == 3) || (frgd_sel == 3) || (bkgd_sel == 3) || (mach->accel.dp_config & 0x02)) {
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->accel.cx += mach->accel.src_stepx;
|
|
|
|
|
mach->accel.sx++;
|
|
|
|
|
if (mach->accel.sx >= mach->accel.src_width) {
|
|
|
|
|
mach->accel.sx = 0;
|
2024-10-26 21:32:47 +02:00
|
|
|
if (mach->accel.src_stepx < 0)
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->accel.cx += mach->accel.src_width;
|
|
|
|
|
else
|
|
|
|
|
dev->accel.cx -= mach->accel.src_width;
|
2023-12-06 15:00:31 +01:00
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->accel.cy += (mach->accel.src_y_dir ? 1 : -1);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (dev->bpp)
|
2024-10-26 21:32:47 +02:00
|
|
|
dev->accel.src = (mach->accel.ge_offset << 1) + (dev->accel.cy * dev->pitch);
|
2023-07-14 23:38:04 +02:00
|
|
|
else
|
2024-10-26 21:32:47 +02:00
|
|
|
dev->accel.src = (mach->accel.ge_offset << 2) + (dev->accel.cy * dev->pitch);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if (dev->bpp)
|
|
|
|
|
mach->accel.color_pattern_idx += 2;
|
|
|
|
|
else
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.color_pattern_idx++;
|
|
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if ((mono_src == 1) && !mach->accel.mono_pattern_enable && !mach->accel.block_write_mono_pattern_enable && (frgd_sel == 5) && (dev->accel_bpp == 24)) {
|
|
|
|
|
if (mach->accel.color_pattern_idx > 2)
|
|
|
|
|
mach->accel.color_pattern_idx = 0;
|
|
|
|
|
} else {
|
|
|
|
|
if (mach->accel.color_pattern_idx > mach->accel.patt_len)
|
|
|
|
|
mach->accel.color_pattern_idx = 0;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
dev->accel.dx += mach->accel.stepx;
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->accel.sx++;
|
2024-01-15 21:43:33 +01:00
|
|
|
if ((dev->accel.sx >= mach->accel.width) || (dev->accel.dx >= 0x600)) {
|
2023-07-30 18:33:29 -04:00
|
|
|
dev->accel.sx = 0;
|
2024-10-26 21:32:47 +02:00
|
|
|
if (mach->accel.stepx < 0)
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->accel.dx += mach->accel.width;
|
|
|
|
|
else
|
|
|
|
|
dev->accel.dx -= mach->accel.width;
|
|
|
|
|
|
|
|
|
|
dev->accel.dy += mach->accel.stepy;
|
|
|
|
|
dev->accel.sy++;
|
|
|
|
|
|
2024-01-05 21:22:01 +01:00
|
|
|
mach->accel.poly_fill = 0;
|
2024-10-26 21:32:47 +02:00
|
|
|
if (mach->accel.dp_config & 0x02)
|
|
|
|
|
dev->accel.dest = (dev->accel.dy * dev->pitch);
|
|
|
|
|
else {
|
|
|
|
|
if (dev->bpp)
|
|
|
|
|
dev->accel.dest = (mach->accel.ge_offset << 1) + (dev->accel.dy * dev->pitch);
|
|
|
|
|
else
|
|
|
|
|
dev->accel.dest = (mach->accel.ge_offset << 2) + (dev->accel.dy * dev->pitch);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
2024-10-26 21:32:47 +02:00
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
if (dev->accel.sy >= mach->accel.height) {
|
2024-11-02 20:50:06 +01:00
|
|
|
dev->accel.cmd_back = 1;
|
2024-10-26 21:32:47 +02:00
|
|
|
if ((mono_src == 2) || (mono_src == 3) || (frgd_sel == 3) || (bkgd_sel == 3) || (mach->accel.dp_config & 0x02))
|
2023-07-14 23:38:04 +02:00
|
|
|
return;
|
2024-11-02 20:50:06 +01:00
|
|
|
if ((mono_src == 1) && (frgd_sel == 5) && (dev->accel_bpp == 24))
|
2023-07-14 23:38:04 +02:00
|
|
|
return;
|
|
|
|
|
dev->accel.cur_x = dev->accel.dx;
|
|
|
|
|
dev->accel.cur_y = dev->accel.dy;
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 3: /*Direct Linedraw (Polyline) from linedraw indexes (0xfeee)*/
|
|
|
|
|
case 4:
|
|
|
|
|
if (!cpu_input) {
|
|
|
|
|
dev->accel.cx = dev->accel.cur_x;
|
|
|
|
|
dev->accel.cy = dev->accel.cur_y;
|
|
|
|
|
|
|
|
|
|
if (dev->accel.cur_x >= 0x600) {
|
|
|
|
|
mach_log("Linedraw XOver = %d.\n", dev->accel.cur_x);
|
|
|
|
|
dev->accel.cx |= ~0x5ff;
|
|
|
|
|
}
|
|
|
|
|
if (dev->accel.cur_y >= 0x600) {
|
|
|
|
|
mach_log("Linedraw YOver = %d.\n", dev->accel.cur_y);
|
|
|
|
|
dev->accel.cy |= ~0x5ff;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dev->accel.dx = ABS(mach->accel.cx_end_line - dev->accel.cx) << 1;
|
|
|
|
|
dev->accel.dy = ABS(mach->accel.cy_end_line - dev->accel.cy) << 1;
|
|
|
|
|
|
|
|
|
|
mach->accel.stepx = (mach->accel.cx_end_line < dev->accel.cx) ? -1 : 1;
|
|
|
|
|
mach->accel.stepy = (mach->accel.cy_end_line < dev->accel.cy) ? -1 : 1;
|
|
|
|
|
|
|
|
|
|
dev->accel.sx = 0;
|
|
|
|
|
|
2025-02-01 03:29:03 -05:00
|
|
|
mach_log("Linedraw: c(%d,%d), d(%d,%d), cend(%d,%d), bounds: l=%d, r=%d, t=%d, b=%d.\n",
|
|
|
|
|
dev->accel.cur_x, dev->accel.cur_y, dev->accel.dx, dev->accel.dy, mach->accel.cx_end_line,
|
|
|
|
|
mach->accel.cy_end_line, mach->accel.bleft, mach->accel.bright, mach->accel.btop, mach->accel.bbottom);
|
2023-07-14 23:38:04 +02:00
|
|
|
|
|
|
|
|
if ((mono_src == 2) || (bkgd_sel == 2) || (frgd_sel == 2) || mach_pixel_read(mach)) {
|
|
|
|
|
if (mach_pixel_write(mach)) {
|
2024-11-13 22:55:16 +01:00
|
|
|
mach_log("Write PIXTRANS.\n");
|
2023-07-30 18:33:29 -04:00
|
|
|
dev->data_available = 0;
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->data_available2 = 0;
|
|
|
|
|
return;
|
|
|
|
|
} else if (mach_pixel_read(mach)) {
|
2024-11-13 22:55:16 +01:00
|
|
|
mach_log("Read PIXTRANS.\n");
|
2023-07-30 18:33:29 -04:00
|
|
|
dev->data_available = 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->data_available2 = 1;
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mono_src == 1) {
|
2024-10-26 21:32:47 +02:00
|
|
|
mix_dat = mach->accel.mono_pattern_normal[0];
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->accel.temp_cnt = 8;
|
|
|
|
|
}
|
|
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
count = (dev->accel.dx > dev->accel.dy) ? (dev->accel.dx >> 1) : (dev->accel.dy >> 1);
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.width = count;
|
|
|
|
|
|
|
|
|
|
if (dev->accel.dx > dev->accel.dy) {
|
|
|
|
|
mach->accel.err = (dev->accel.dy - dev->accel.dx) >> 1;
|
|
|
|
|
if (mono_src == 1) {
|
|
|
|
|
while (count--) {
|
|
|
|
|
if (!dev->accel.temp_cnt) {
|
|
|
|
|
dev->accel.temp_cnt = 8;
|
|
|
|
|
mix_dat >>= 8;
|
|
|
|
|
}
|
|
|
|
|
mix = (mix_dat & 0x80);
|
|
|
|
|
dev->accel.temp_cnt--;
|
|
|
|
|
mix_dat <<= 1;
|
|
|
|
|
mix_dat |= 1;
|
|
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if ((dev->accel.cx >= clip_l) &&
|
|
|
|
|
(dev->accel.cx <= clip_r) &&
|
|
|
|
|
(dev->accel.cy >= clip_t) &&
|
|
|
|
|
(dev->accel.cy <= clip_b)) {
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.clip_overrun = 0;
|
|
|
|
|
switch (mix ? frgd_sel : bkgd_sel) {
|
|
|
|
|
case 0:
|
|
|
|
|
src_dat = dev->accel.bkgd_color;
|
|
|
|
|
break;
|
|
|
|
|
case 1:
|
|
|
|
|
src_dat = dev->accel.frgd_color;
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
src_dat = cpu_dat;
|
|
|
|
|
break;
|
|
|
|
|
case 3:
|
|
|
|
|
if (mach_pixel_read(mach))
|
|
|
|
|
src_dat = cpu_dat;
|
2024-01-05 21:22:01 +01:00
|
|
|
else
|
2023-07-14 23:38:04 +02:00
|
|
|
src_dat = 0;
|
|
|
|
|
break;
|
|
|
|
|
case 5:
|
2024-10-26 21:32:47 +02:00
|
|
|
src_dat = mach->accel.color_pattern[mach->accel.color_pattern_idx];
|
|
|
|
|
if (dev->bpp)
|
|
|
|
|
src_dat |= (mach->accel.color_pattern[mach->accel.color_pattern_idx + 1] << 8);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
2023-06-09 23:46:54 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (dev->bpp) {
|
|
|
|
|
READ((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
|
2023-07-14 23:38:04 +02:00
|
|
|
} else {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
READ((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
switch (compare_mode) {
|
|
|
|
|
case 1:
|
|
|
|
|
compare = 1;
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat >= dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 3:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat < dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 4:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat != dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 5:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat == dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 6:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat <= dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 7:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat > dest_cmp_clr) ? 0 : 1;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (!compare) {
|
|
|
|
|
if (mach_pixel_write(mach)) {
|
|
|
|
|
old_dest_dat = dest_dat;
|
|
|
|
|
MIX(mix, dest_dat, src_dat);
|
|
|
|
|
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
|
|
|
|
|
}
|
|
|
|
|
}
|
2024-05-29 20:47:22 +02:00
|
|
|
if ((mach->accel.dp_config & 0x10) && (cmd_type == 3)) {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (dev->bpp) {
|
|
|
|
|
WRITE((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
|
2023-07-14 23:38:04 +02:00
|
|
|
} else {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
WRITE((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
} else
|
|
|
|
|
mach->accel.clip_overrun = ((mach->accel.clip_overrun + 1) & 0x0f);
|
|
|
|
|
|
2024-11-02 20:50:06 +01:00
|
|
|
if (!count) {
|
|
|
|
|
dev->accel.cmd_back = 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
2024-11-02 20:50:06 +01:00
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (dev->bpp)
|
2023-07-14 23:38:04 +02:00
|
|
|
cpu_dat >>= 16;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
else
|
|
|
|
|
cpu_dat >>= 8;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if (dev->bpp)
|
|
|
|
|
mach->accel.color_pattern_idx += 2;
|
|
|
|
|
else
|
|
|
|
|
mach->accel.color_pattern_idx++;
|
|
|
|
|
|
|
|
|
|
if (mach->accel.color_pattern_idx > mach->accel.patt_len)
|
|
|
|
|
mach->accel.color_pattern_idx = 0;
|
|
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
if (mach->accel.err >= 0) {
|
|
|
|
|
dev->accel.cy += mach->accel.stepy;
|
|
|
|
|
mach->accel.err -= dev->accel.dx;
|
|
|
|
|
}
|
|
|
|
|
dev->accel.cx += mach->accel.stepx;
|
|
|
|
|
mach->accel.err += dev->accel.dy;
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
while (count--) {
|
|
|
|
|
switch (mono_src) {
|
|
|
|
|
case 0:
|
|
|
|
|
case 3:
|
|
|
|
|
mix = 1;
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
if (mach->accel.dp_config & 0x1000) {
|
|
|
|
|
mix = mix_dat >> 0x1f;
|
|
|
|
|
mix_dat <<= 1;
|
|
|
|
|
} else {
|
|
|
|
|
if (mach->accel.dp_config & 0x200) {
|
|
|
|
|
mix = mix_dat & 1;
|
|
|
|
|
mix_dat >>= 1;
|
|
|
|
|
} else {
|
|
|
|
|
mix = mix_dat & 0x80;
|
|
|
|
|
mix_dat <<= 1;
|
|
|
|
|
mix_dat |= 1;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
2023-06-09 23:46:54 -04:00
|
|
|
|
|
|
|
|
default:
|
2023-07-30 18:33:29 -04:00
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if ((dev->accel.cx >= clip_l) &&
|
|
|
|
|
(dev->accel.cx <= clip_r) &&
|
|
|
|
|
(dev->accel.cy >= clip_t) &&
|
|
|
|
|
(dev->accel.cy <= clip_b)) {
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.clip_overrun = 0;
|
2024-01-05 21:22:01 +01:00
|
|
|
if (mach->accel.linedraw_opt & 0x02) {
|
2024-10-26 21:32:47 +02:00
|
|
|
if (dev->bpp) {
|
|
|
|
|
READ((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), poly_src);
|
|
|
|
|
} else {
|
|
|
|
|
READ((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), poly_src);
|
|
|
|
|
}
|
2024-01-05 21:22:01 +01:00
|
|
|
if (poly_src)
|
2024-10-26 21:32:47 +02:00
|
|
|
mach->accel.poly_fill ^= 1;
|
2024-01-05 21:22:01 +01:00
|
|
|
}
|
|
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
switch (mix ? frgd_sel : bkgd_sel) {
|
|
|
|
|
case 0:
|
|
|
|
|
src_dat = dev->accel.bkgd_color;
|
|
|
|
|
break;
|
|
|
|
|
case 1:
|
|
|
|
|
src_dat = dev->accel.frgd_color;
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
src_dat = cpu_dat;
|
|
|
|
|
break;
|
|
|
|
|
case 3:
|
|
|
|
|
if (mach_pixel_read(mach))
|
|
|
|
|
src_dat = cpu_dat;
|
|
|
|
|
else {
|
|
|
|
|
src_dat = 0;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 5:
|
2024-10-26 21:32:47 +02:00
|
|
|
src_dat = mach->accel.color_pattern[mach->accel.color_pattern_idx];
|
|
|
|
|
if (dev->bpp)
|
|
|
|
|
src_dat |= (mach->accel.color_pattern[mach->accel.color_pattern_idx + 1] << 8);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
2023-06-09 23:46:54 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if (mach->accel.linedraw_opt & 0x02) {
|
|
|
|
|
if (dev->bpp) {
|
|
|
|
|
READ((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
|
|
|
|
|
} else {
|
|
|
|
|
READ((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
|
|
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
} else {
|
2024-10-26 21:32:47 +02:00
|
|
|
READ(((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
switch (compare_mode) {
|
|
|
|
|
case 1:
|
|
|
|
|
compare = 1;
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat >= dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 3:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat < dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 4:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat != dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 5:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat == dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 6:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat <= dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 7:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat > dest_cmp_clr) ? 0 : 1;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (!compare) {
|
|
|
|
|
if (mach_pixel_write(mach)) {
|
|
|
|
|
old_dest_dat = dest_dat;
|
2024-01-05 21:22:01 +01:00
|
|
|
if (mach->accel.poly_fill || !(mach->accel.linedraw_opt & 0x02)) {
|
|
|
|
|
MIX(mix, dest_dat, src_dat);
|
|
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if ((mach->accel.dp_config & 0x10) && (cmd_type == 3)) {
|
|
|
|
|
if (mach->accel.linedraw_opt & 0x04) {
|
|
|
|
|
if (dev->accel.sx < mach->accel.width) {
|
2024-10-26 21:32:47 +02:00
|
|
|
if (mach->accel.linedraw_opt & 0x02) {
|
|
|
|
|
if (dev->bpp) {
|
|
|
|
|
WRITE((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
|
|
|
|
|
} else {
|
|
|
|
|
WRITE((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
WRITE(((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
if (mach->accel.linedraw_opt & 0x02) {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (dev->bpp) {
|
|
|
|
|
WRITE((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
|
2023-07-14 23:38:04 +02:00
|
|
|
} else {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
WRITE((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
} else {
|
2024-10-26 21:32:47 +02:00
|
|
|
WRITE(((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
} else
|
|
|
|
|
mach->accel.clip_overrun = ((mach->accel.clip_overrun + 1) & 0x0f);
|
|
|
|
|
|
2024-11-02 20:50:06 +01:00
|
|
|
if (dev->accel.sx >= mach->accel.width) {
|
|
|
|
|
dev->accel.cmd_back = 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
2024-11-02 20:50:06 +01:00
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (dev->bpp)
|
2023-07-14 23:38:04 +02:00
|
|
|
cpu_dat >>= 16;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
else
|
|
|
|
|
cpu_dat >>= 8;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if (dev->bpp)
|
|
|
|
|
mach->accel.color_pattern_idx += 2;
|
|
|
|
|
else
|
|
|
|
|
mach->accel.color_pattern_idx++;
|
|
|
|
|
|
|
|
|
|
if (mach->accel.color_pattern_idx > mach->accel.patt_len)
|
|
|
|
|
mach->accel.color_pattern_idx = 0;
|
|
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
if (mach->accel.err >= 0) {
|
|
|
|
|
dev->accel.cy += mach->accel.stepy;
|
|
|
|
|
mach->accel.err -= dev->accel.dx;
|
|
|
|
|
}
|
|
|
|
|
dev->accel.cx += mach->accel.stepx;
|
|
|
|
|
mach->accel.err += dev->accel.dy;
|
|
|
|
|
|
|
|
|
|
dev->accel.sx++;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
mach->accel.err = (dev->accel.dx - dev->accel.dy) >> 1;
|
|
|
|
|
if (mono_src == 1) {
|
|
|
|
|
while (count--) {
|
|
|
|
|
if (dev->accel.temp_cnt == 0) {
|
|
|
|
|
dev->accel.temp_cnt = 8;
|
|
|
|
|
mix_dat >>= 8;
|
|
|
|
|
}
|
|
|
|
|
mix = (mix_dat & 0x80);
|
|
|
|
|
dev->accel.temp_cnt--;
|
|
|
|
|
mix_dat <<= 1;
|
|
|
|
|
mix_dat |= 1;
|
|
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if ((dev->accel.cx >= clip_l) &&
|
|
|
|
|
(dev->accel.cx <= clip_r) &&
|
|
|
|
|
(dev->accel.cy >= clip_t) &&
|
|
|
|
|
(dev->accel.cy <= clip_b)) {
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.clip_overrun = 0;
|
|
|
|
|
switch (mix ? frgd_sel : bkgd_sel) {
|
|
|
|
|
case 0:
|
|
|
|
|
src_dat = dev->accel.bkgd_color;
|
|
|
|
|
break;
|
|
|
|
|
case 1:
|
|
|
|
|
src_dat = dev->accel.frgd_color;
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
src_dat = cpu_dat;
|
|
|
|
|
break;
|
|
|
|
|
case 3:
|
|
|
|
|
if (mach_pixel_read(mach))
|
|
|
|
|
src_dat = cpu_dat;
|
|
|
|
|
else {
|
|
|
|
|
src_dat = 0;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 5:
|
2024-10-26 21:32:47 +02:00
|
|
|
src_dat = mach->accel.color_pattern[mach->accel.color_pattern_idx];
|
|
|
|
|
if (dev->bpp)
|
|
|
|
|
src_dat |= (mach->accel.color_pattern[mach->accel.color_pattern_idx + 1] << 8);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
2023-06-09 23:46:54 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (dev->bpp) {
|
|
|
|
|
READ((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
|
2023-07-14 23:38:04 +02:00
|
|
|
} else {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
READ((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
switch (compare_mode) {
|
|
|
|
|
case 1:
|
|
|
|
|
compare = 1;
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat >= dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 3:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat < dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 4:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat != dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 5:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat == dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 6:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat <= dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 7:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat > dest_cmp_clr) ? 0 : 1;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (!compare) {
|
|
|
|
|
if (mach_pixel_write(mach)) {
|
|
|
|
|
old_dest_dat = dest_dat;
|
|
|
|
|
MIX(mix, dest_dat, src_dat);
|
|
|
|
|
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if ((mach->accel.dp_config & 0x10) && (cmd_type == 3)) {
|
2024-05-29 20:47:22 +02:00
|
|
|
if (dev->bpp) {
|
|
|
|
|
WRITE((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
|
2023-07-14 23:38:04 +02:00
|
|
|
} else {
|
2024-05-29 20:47:22 +02:00
|
|
|
WRITE((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
} else
|
|
|
|
|
mach->accel.clip_overrun = ((mach->accel.clip_overrun + 1) & 0x0f);
|
|
|
|
|
|
2024-11-02 20:50:06 +01:00
|
|
|
if (!count) {
|
|
|
|
|
dev->accel.cmd_back = 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
2024-11-02 20:50:06 +01:00
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (dev->bpp)
|
2023-07-14 23:38:04 +02:00
|
|
|
cpu_dat >>= 16;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
else
|
|
|
|
|
cpu_dat >>= 8;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if (dev->bpp)
|
|
|
|
|
mach->accel.color_pattern_idx += 2;
|
|
|
|
|
else
|
|
|
|
|
mach->accel.color_pattern_idx++;
|
|
|
|
|
|
|
|
|
|
if (mach->accel.color_pattern_idx > mach->accel.patt_len)
|
|
|
|
|
mach->accel.color_pattern_idx = 0;
|
|
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
if (mach->accel.err >= 0) {
|
|
|
|
|
dev->accel.cx += mach->accel.stepx;
|
|
|
|
|
mach->accel.err -= dev->accel.dy;
|
|
|
|
|
}
|
|
|
|
|
dev->accel.cy += mach->accel.stepy;
|
|
|
|
|
mach->accel.err += dev->accel.dx;
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
while (count--) {
|
|
|
|
|
switch (mono_src) {
|
|
|
|
|
case 0:
|
|
|
|
|
case 3:
|
|
|
|
|
mix = 1;
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
if (mach->accel.dp_config & 0x1000) {
|
|
|
|
|
mix = mix_dat >> 0x1f;
|
|
|
|
|
mix_dat <<= 1;
|
|
|
|
|
} else {
|
|
|
|
|
if (mach->accel.dp_config & 0x200) {
|
|
|
|
|
mix = mix_dat & 1;
|
|
|
|
|
mix_dat >>= 1;
|
|
|
|
|
} else {
|
|
|
|
|
mix = mix_dat & 0x80;
|
|
|
|
|
mix_dat <<= 1;
|
|
|
|
|
mix_dat |= 1;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
2023-06-09 23:46:54 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if ((dev->accel.cx >= clip_l) &&
|
|
|
|
|
(dev->accel.cx <= clip_r) &&
|
|
|
|
|
(dev->accel.cy >= clip_t) &&
|
|
|
|
|
(dev->accel.cy <= clip_b)) {
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.clip_overrun = 0;
|
|
|
|
|
switch (mix ? frgd_sel : bkgd_sel) {
|
|
|
|
|
case 0:
|
|
|
|
|
src_dat = dev->accel.bkgd_color;
|
|
|
|
|
break;
|
|
|
|
|
case 1:
|
|
|
|
|
src_dat = dev->accel.frgd_color;
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
src_dat = cpu_dat;
|
|
|
|
|
break;
|
|
|
|
|
case 3:
|
|
|
|
|
if (mach_pixel_read(mach))
|
|
|
|
|
src_dat = cpu_dat;
|
|
|
|
|
else {
|
|
|
|
|
src_dat = 0;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 5:
|
2024-10-26 21:32:47 +02:00
|
|
|
src_dat = mach->accel.color_pattern[mach->accel.color_pattern_idx];
|
|
|
|
|
if (dev->bpp)
|
|
|
|
|
src_dat |= (mach->accel.color_pattern[mach->accel.color_pattern_idx + 1] << 8);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
2023-06-09 23:46:54 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if (mach->accel.linedraw_opt & 0x02) {
|
|
|
|
|
if (dev->bpp) {
|
|
|
|
|
READ((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
|
|
|
|
|
} else {
|
|
|
|
|
READ((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
|
|
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
} else {
|
2024-10-26 21:32:47 +02:00
|
|
|
READ(((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
switch (compare_mode) {
|
|
|
|
|
case 1:
|
|
|
|
|
compare = 1;
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat >= dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 3:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat < dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 4:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat != dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 5:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat == dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 6:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat <= dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 7:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat > dest_cmp_clr) ? 0 : 1;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (!compare) {
|
|
|
|
|
if (mach_pixel_write(mach)) {
|
|
|
|
|
old_dest_dat = dest_dat;
|
|
|
|
|
MIX(mix, dest_dat, src_dat);
|
|
|
|
|
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if ((mach->accel.dp_config & 0x10) && (cmd_type == 3)) {
|
|
|
|
|
if (mach->accel.linedraw_opt & 0x04) {
|
|
|
|
|
if (dev->accel.sx < mach->accel.width) {
|
2024-10-26 21:32:47 +02:00
|
|
|
if (mach->accel.linedraw_opt & 0x02) {
|
|
|
|
|
if (dev->bpp) {
|
|
|
|
|
WRITE((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
|
|
|
|
|
} else {
|
|
|
|
|
WRITE((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
WRITE((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
if (mach->accel.linedraw_opt & 0x02) {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (dev->bpp) {
|
|
|
|
|
WRITE((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
|
2023-07-14 23:38:04 +02:00
|
|
|
} else {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
WRITE((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
} else {
|
2024-10-26 21:32:47 +02:00
|
|
|
WRITE(((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
} else
|
|
|
|
|
mach->accel.clip_overrun = ((mach->accel.clip_overrun + 1) & 0x0f);
|
|
|
|
|
|
2024-11-02 20:50:06 +01:00
|
|
|
if (dev->accel.sx >= mach->accel.width) {
|
|
|
|
|
dev->accel.cmd_back = 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
2024-11-02 20:50:06 +01:00
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (dev->bpp)
|
2023-07-14 23:38:04 +02:00
|
|
|
cpu_dat >>= 16;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
else
|
|
|
|
|
cpu_dat >>= 8;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if (dev->bpp)
|
|
|
|
|
mach->accel.color_pattern_idx += 2;
|
|
|
|
|
else
|
|
|
|
|
mach->accel.color_pattern_idx++;
|
|
|
|
|
|
|
|
|
|
if (mach->accel.color_pattern_idx > mach->accel.patt_len)
|
|
|
|
|
mach->accel.color_pattern_idx = 0;
|
|
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
if (mach->accel.err >= 0) {
|
|
|
|
|
dev->accel.cx += mach->accel.stepx;
|
|
|
|
|
mach->accel.err -= dev->accel.dy;
|
|
|
|
|
}
|
|
|
|
|
dev->accel.cy += mach->accel.stepy;
|
|
|
|
|
mach->accel.err += dev->accel.dx;
|
|
|
|
|
|
|
|
|
|
dev->accel.sx++;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
2024-01-05 21:22:01 +01:00
|
|
|
mach->accel.poly_fill = 0;
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.line_array[(cmd_type == 4) ? 4 : 0] = dev->accel.cx;
|
|
|
|
|
mach->accel.line_array[(cmd_type == 4) ? 5 : 1] = dev->accel.cy;
|
2023-07-30 18:33:29 -04:00
|
|
|
dev->accel.cur_x = mach->accel.line_array[(cmd_type == 4) ? 4 : 0];
|
|
|
|
|
dev->accel.cur_y = mach->accel.line_array[(cmd_type == 4) ? 5 : 1];
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 5: /*Horizontal Raster Draw from scan_to_x register (0xcaee)*/
|
|
|
|
|
if (!cpu_input) {
|
|
|
|
|
mach->accel.stepx = 0;
|
|
|
|
|
mach->accel.stepy = 0;
|
|
|
|
|
|
|
|
|
|
dev->accel.dx = dev->accel.cur_x;
|
|
|
|
|
if (dev->accel.cur_x >= 0x600)
|
|
|
|
|
dev->accel.dx |= ~0x5ff;
|
|
|
|
|
dev->accel.dy = dev->accel.cur_y;
|
|
|
|
|
if (dev->accel.cur_y >= 0x600)
|
|
|
|
|
dev->accel.dy |= ~0x5ff;
|
|
|
|
|
|
|
|
|
|
/*Destination Width*/
|
|
|
|
|
mach->accel.dx_start = dev->accel.cur_x;
|
|
|
|
|
if (dev->accel.cur_x >= 0x600)
|
|
|
|
|
mach->accel.dx_start |= ~0x5ff;
|
|
|
|
|
mach->accel.dx_end = mach->accel.scan_to_x;
|
|
|
|
|
if (mach->accel.scan_to_x >= 0x600)
|
|
|
|
|
mach->accel.dx_end |= ~0x5ff;
|
|
|
|
|
|
|
|
|
|
if (mach->accel.dx_end > mach->accel.dx_start) {
|
|
|
|
|
mach->accel.width = (mach->accel.dx_end - mach->accel.dx_start);
|
|
|
|
|
mach->accel.stepx = 1;
|
|
|
|
|
} else if (mach->accel.dx_end < mach->accel.dx_start) {
|
|
|
|
|
mach->accel.width = (mach->accel.dx_start - mach->accel.dx_end);
|
|
|
|
|
mach->accel.stepx = -1;
|
|
|
|
|
if (dev->accel.dx > 0)
|
|
|
|
|
dev->accel.dx--;
|
|
|
|
|
} else {
|
|
|
|
|
mach->accel.stepx = 1;
|
|
|
|
|
mach->accel.width = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dev->accel.sx = 0;
|
|
|
|
|
|
|
|
|
|
/*Step Y*/
|
|
|
|
|
mach->accel.dy_start = dev->accel.cur_y;
|
|
|
|
|
if (dev->accel.cur_y >= 0x600)
|
|
|
|
|
mach->accel.dy_start |= ~0x5ff;
|
|
|
|
|
mach->accel.dy_end = mach->accel.dest_y_end;
|
|
|
|
|
if (mach->accel.dest_y_end >= 0x600)
|
|
|
|
|
mach->accel.dy_end |= ~0x5ff;
|
|
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if (mach->accel.dy_end > mach->accel.dy_start)
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.stepy = 1;
|
2024-10-26 21:32:47 +02:00
|
|
|
else if (mach->accel.dy_end < mach->accel.dy_start)
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.stepy = -1;
|
2024-10-26 21:32:47 +02:00
|
|
|
else
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.stepy = 0;
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (dev->bpp)
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->accel.dest = (mach->accel.ge_offset << 1) + (dev->accel.dy * (dev->pitch));
|
|
|
|
|
else
|
|
|
|
|
dev->accel.dest = (mach->accel.ge_offset << 2) + (dev->accel.dy * (dev->pitch));
|
|
|
|
|
|
|
|
|
|
mach->accel.src_stepx = 0;
|
|
|
|
|
|
|
|
|
|
/*Source Width*/
|
|
|
|
|
dev->accel.cx = mach->accel.src_x;
|
|
|
|
|
if (mach->accel.src_x >= 0x600)
|
|
|
|
|
dev->accel.cx |= ~0x5ff;
|
|
|
|
|
dev->accel.cy = mach->accel.src_y;
|
|
|
|
|
if (mach->accel.src_y >= 0x600)
|
|
|
|
|
dev->accel.cy |= ~0x5ff;
|
|
|
|
|
|
|
|
|
|
mach->accel.sx_start = mach->accel.src_x_start;
|
|
|
|
|
if (mach->accel.src_x_start >= 0x600)
|
|
|
|
|
mach->accel.sx_start |= ~0x5ff;
|
|
|
|
|
|
|
|
|
|
mach->accel.sx_end = mach->accel.src_x_end;
|
|
|
|
|
if (mach->accel.src_x_end >= 0x600)
|
|
|
|
|
mach->accel.sx_end |= ~0x5ff;
|
|
|
|
|
|
|
|
|
|
if (mach->accel.sx_end > mach->accel.sx_start) {
|
|
|
|
|
mach->accel.src_width = (mach->accel.sx_end - mach->accel.sx_start);
|
|
|
|
|
mach->accel.src_stepx = 1;
|
|
|
|
|
} else if (mach->accel.sx_end < mach->accel.sx_start) {
|
|
|
|
|
mach->accel.src_width = (mach->accel.sx_start - mach->accel.sx_end);
|
|
|
|
|
mach->accel.src_stepx = -1;
|
|
|
|
|
if (dev->accel.cx > 0)
|
|
|
|
|
dev->accel.cx--;
|
|
|
|
|
} else {
|
|
|
|
|
mach->accel.src_stepx = 1;
|
|
|
|
|
mach->accel.src_width = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
mach->accel.sx = 0;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (dev->bpp)
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->accel.src = (mach->accel.ge_offset << 1) + (dev->accel.cy * (dev->pitch));
|
|
|
|
|
else
|
|
|
|
|
dev->accel.src = (mach->accel.ge_offset << 2) + (dev->accel.cy * (dev->pitch));
|
|
|
|
|
|
2025-02-01 03:29:03 -05:00
|
|
|
mach_log("ScanToX=%04x, MonoSRC=%d, FrgdSel=%d, BkgdSel=%d, Pitch=%d, C(%d,%d), SRCWidth=%d, WH(%d,%d), colorpattidx=%d, pattlen=%d.\n",
|
|
|
|
|
mach->accel.dp_config, mono_src, frgd_sel, bkgd_sel, dev->ext_pitch, dev->accel.cx, dev->accel.cy, mach->accel.src_width,
|
|
|
|
|
mach->accel.width, mach->accel.height, mach->accel.color_pattern_idx, mach->accel.patt_len);
|
2023-07-14 23:38:04 +02:00
|
|
|
|
|
|
|
|
if ((mono_src == 2) || (bkgd_sel == 2) || (frgd_sel == 2) || mach_pixel_read(mach)) {
|
|
|
|
|
if (mach_pixel_write(mach)) {
|
2023-07-30 18:33:29 -04:00
|
|
|
dev->data_available = 0;
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->data_available2 = 0;
|
|
|
|
|
return;
|
|
|
|
|
} else if (mach_pixel_read(mach)) {
|
2023-07-30 18:33:29 -04:00
|
|
|
dev->data_available = 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->data_available2 = 1;
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mono_src == 1) {
|
2023-07-30 18:33:29 -04:00
|
|
|
count = mach->accel.width;
|
2024-10-26 21:32:47 +02:00
|
|
|
mix_dat = mach->accel.mono_pattern_normal[0];
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->accel.temp_cnt = 8;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
while (count--) {
|
|
|
|
|
switch (mono_src) {
|
|
|
|
|
case 0:
|
|
|
|
|
mix = 1;
|
|
|
|
|
break;
|
|
|
|
|
case 1:
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (!dev->accel.temp_cnt) {
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->accel.temp_cnt = 8;
|
|
|
|
|
mix_dat >>= 8;
|
|
|
|
|
}
|
|
|
|
|
mix = (mix_dat & 0x80);
|
|
|
|
|
dev->accel.temp_cnt--;
|
|
|
|
|
mix_dat <<= 1;
|
|
|
|
|
mix_dat |= 1;
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
if (mach->accel.dp_config & 0x1000) {
|
|
|
|
|
mix = mix_dat >> 0x1f;
|
|
|
|
|
mix_dat <<= 1;
|
|
|
|
|
} else {
|
|
|
|
|
if (mach->accel.dp_config & 0x200) {
|
|
|
|
|
mix = mix_dat & 1;
|
|
|
|
|
mix_dat >>= 1;
|
|
|
|
|
} else {
|
|
|
|
|
mix = mix_dat & 0x80;
|
|
|
|
|
mix_dat <<= 1;
|
|
|
|
|
mix_dat |= 1;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 3:
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
READ(dev->accel.src + (dev->accel.cx), mix);
|
2023-07-14 23:38:04 +02:00
|
|
|
mix = (mix & rd_mask) == rd_mask;
|
|
|
|
|
break;
|
2023-06-09 23:46:54 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if ((dev->accel.dx >= clip_l) &&
|
|
|
|
|
(dev->accel.dx <= clip_r) &&
|
|
|
|
|
(dev->accel.dy >= clip_t) &&
|
|
|
|
|
(dev->accel.dy <= clip_b)) {
|
2023-07-14 23:38:04 +02:00
|
|
|
switch (mix ? frgd_sel : bkgd_sel) {
|
|
|
|
|
case 0:
|
|
|
|
|
src_dat = dev->accel.bkgd_color;
|
|
|
|
|
break;
|
|
|
|
|
case 1:
|
|
|
|
|
src_dat = dev->accel.frgd_color;
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
src_dat = cpu_dat;
|
|
|
|
|
break;
|
|
|
|
|
case 3:
|
|
|
|
|
if (mach_pixel_read(mach))
|
|
|
|
|
src_dat = cpu_dat;
|
|
|
|
|
else {
|
2024-01-15 21:43:33 +01:00
|
|
|
READ(dev->accel.src + dev->accel.cx, src_dat);
|
|
|
|
|
if (mono_src == 3)
|
2023-07-14 23:38:04 +02:00
|
|
|
src_dat = (src_dat & rd_mask) == rd_mask;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 5:
|
2024-10-26 21:32:47 +02:00
|
|
|
src_dat = mach->accel.color_pattern[mach->accel.color_pattern_idx];
|
|
|
|
|
if (dev->bpp)
|
|
|
|
|
src_dat |= (mach->accel.color_pattern[mach->accel.color_pattern_idx + 1] << 8);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
2023-06-09 23:46:54 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
2024-01-15 21:43:33 +01:00
|
|
|
READ(dev->accel.dest + dev->accel.dx, dest_dat);
|
2023-07-14 23:38:04 +02:00
|
|
|
|
|
|
|
|
switch (compare_mode) {
|
|
|
|
|
case 1:
|
|
|
|
|
compare = 1;
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat >= dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 3:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat < dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 4:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat != dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 5:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat == dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 6:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat <= dest_cmp_clr) ? 0 : 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 7:
|
2023-06-09 23:46:54 -04:00
|
|
|
compare = (dest_dat > dest_cmp_clr) ? 0 : 1;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (!compare) {
|
|
|
|
|
if (mach_pixel_write(mach)) {
|
|
|
|
|
old_dest_dat = dest_dat;
|
|
|
|
|
MIX(mix, dest_dat, src_dat);
|
|
|
|
|
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mach->accel.dp_config & 0x10) {
|
2024-10-26 21:32:47 +02:00
|
|
|
WRITE(dev->accel.dest + dev->accel.dx, dest_dat);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (dev->bpp)
|
2023-07-14 23:38:04 +02:00
|
|
|
cpu_dat >>= 16;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
else
|
|
|
|
|
cpu_dat >>= 8;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
|
|
|
|
dev->accel.cx += mach->accel.src_stepx;
|
|
|
|
|
mach->accel.sx++;
|
|
|
|
|
if (mach->accel.sx >= mach->accel.src_width) {
|
|
|
|
|
mach->accel.sx = 0;
|
|
|
|
|
if (mach->accel.src_stepx == -1) {
|
|
|
|
|
dev->accel.cx += mach->accel.src_width;
|
|
|
|
|
} else
|
|
|
|
|
dev->accel.cx -= mach->accel.src_width;
|
|
|
|
|
dev->accel.cy += (mach->accel.src_y_dir ? 1 : -1);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (dev->bpp)
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->accel.src = (mach->accel.ge_offset << 1) + (dev->accel.cy * (dev->pitch));
|
|
|
|
|
else
|
|
|
|
|
dev->accel.src = (mach->accel.ge_offset << 2) + (dev->accel.cy * (dev->pitch));
|
|
|
|
|
}
|
|
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if (dev->bpp)
|
|
|
|
|
mach->accel.color_pattern_idx += 2;
|
|
|
|
|
else
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.color_pattern_idx++;
|
|
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if (mach->accel.color_pattern_idx > mach->accel.patt_len)
|
|
|
|
|
mach->accel.color_pattern_idx = 0;
|
|
|
|
|
|
|
|
|
|
dev->accel.dx += mach->accel.stepx;
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->accel.sx++;
|
|
|
|
|
if (dev->accel.sx >= mach->accel.width) {
|
|
|
|
|
dev->accel.sx = 0;
|
|
|
|
|
dev->accel.dy += mach->accel.stepy;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (dev->bpp)
|
2024-11-02 20:50:06 +01:00
|
|
|
dev->accel.dest = (mach->accel.ge_offset << 1) + (dev->accel.dy * dev->pitch);
|
2023-07-14 23:38:04 +02:00
|
|
|
else
|
2024-11-02 20:50:06 +01:00
|
|
|
dev->accel.dest = (mach->accel.ge_offset << 2) + (dev->accel.dy * dev->pitch);
|
2023-07-14 23:38:04 +02:00
|
|
|
if (mach->accel.line_idx == 2) {
|
|
|
|
|
mach->accel.line_array[0] = dev->accel.dx;
|
|
|
|
|
mach->accel.line_array[4] = dev->accel.dx;
|
|
|
|
|
}
|
2024-11-02 20:50:06 +01:00
|
|
|
dev->accel.cmd_back = 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
2023-06-09 23:46:54 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_accel_out_pixtrans(svga_t *svga, mach_t *mach, ibm8514_t *dev, uint16_t val)
|
2023-07-14 23:38:04 +02:00
|
|
|
{
|
2023-06-09 23:46:54 -04:00
|
|
|
int frgd_sel;
|
|
|
|
|
int bkgd_sel;
|
|
|
|
|
int mono_src;
|
2024-10-26 21:32:47 +02:00
|
|
|
int swap = 0;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
|
|
|
|
frgd_sel = (mach->accel.dp_config >> 13) & 7;
|
|
|
|
|
bkgd_sel = (mach->accel.dp_config >> 7) & 3;
|
|
|
|
|
mono_src = (mach->accel.dp_config >> 5) & 3;
|
|
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if ((mach->accel.dp_config & 0x04) && (mach->accel.cmd_type != 5)) {
|
|
|
|
|
mach_log("Read Host Monochrome Data.\n");
|
2023-07-14 23:38:04 +02:00
|
|
|
val = (val >> 8) | (val << 8);
|
2024-10-26 21:32:47 +02:00
|
|
|
swap = 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
switch (mach->accel.dp_config & 0x200) {
|
|
|
|
|
case 0x000: /*8-bit size*/
|
2023-06-09 23:46:54 -04:00
|
|
|
if (mono_src == 2) {
|
2023-07-14 23:38:04 +02:00
|
|
|
if ((frgd_sel != 2) && (bkgd_sel != 2)) {
|
2024-10-26 21:32:47 +02:00
|
|
|
if ((mach->accel.dp_config & 0x1000) && !swap) {
|
|
|
|
|
mach_log("8-bit bus size swap.\n");
|
2023-07-14 23:38:04 +02:00
|
|
|
val = (val >> 8) | (val << 8);
|
2024-10-26 21:32:47 +02:00
|
|
|
}
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_accel_start(mach->accel.cmd_type, 1, 8, val | (val << 16), 0, svga, mach, dev);
|
2023-07-14 23:38:04 +02:00
|
|
|
} else
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_accel_start(mach->accel.cmd_type, 1, 1, -1, val | (val << 16), svga, mach, dev);
|
2023-07-14 23:38:04 +02:00
|
|
|
} else
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_accel_start(mach->accel.cmd_type, 1, 1, -1, val | (val << 16), svga, mach, dev);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 0x200: /*16-bit size*/
|
2023-06-09 23:46:54 -04:00
|
|
|
if (mono_src == 2) {
|
2023-07-14 23:38:04 +02:00
|
|
|
if ((frgd_sel != 2) && (bkgd_sel != 2)) {
|
2025-02-20 15:35:56 +01:00
|
|
|
if (((mach->accel.dp_config & 0x1000) && !swap) || swap) {
|
2024-10-26 21:32:47 +02:00
|
|
|
mach_log("16-bit bus size swap.\n");
|
2023-07-14 23:38:04 +02:00
|
|
|
val = (val >> 8) | (val << 8);
|
2024-10-26 21:32:47 +02:00
|
|
|
}
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_accel_start(mach->accel.cmd_type, 1, 16, val | (val << 16), 0, svga, mach, dev);
|
2024-01-15 21:43:33 +01:00
|
|
|
} else
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_accel_start(mach->accel.cmd_type, 1, 2, -1, val | (val << 16), svga, mach, dev);
|
2024-01-15 21:43:33 +01:00
|
|
|
} else
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_accel_start(mach->accel.cmd_type, 1, 2, -1, val | (val << 16), svga, mach, dev);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
2023-06-09 23:46:54 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2023-06-09 23:46:54 -04:00
|
|
|
mach_out(uint16_t addr, uint8_t val, void *priv)
|
2023-07-14 23:38:04 +02:00
|
|
|
{
|
2023-07-30 18:33:29 -04:00
|
|
|
mach_t *mach = (mach_t *) priv;
|
|
|
|
|
svga_t *svga = &mach->svga;
|
2024-11-02 20:50:06 +01:00
|
|
|
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
2023-07-30 18:33:29 -04:00
|
|
|
uint8_t old;
|
|
|
|
|
uint8_t rs2;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
uint8_t rs3;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
|
|
|
|
if (((addr & 0xFFF0) == 0x3D0 || (addr & 0xFFF0) == 0x3B0) && !(svga->miscout & 1))
|
|
|
|
|
addr ^= 0x60;
|
|
|
|
|
|
2024-11-02 20:50:06 +01:00
|
|
|
if (((dev->disp_cntl & 0x60) == 0x20) && ((dev->local & 0xff) >= 0x02)) {
|
2024-11-03 04:46:32 +01:00
|
|
|
if ((addr >= 0x3c6) && (addr <= 0x3c9)) {
|
2025-02-01 03:29:03 -05:00
|
|
|
mach_log("VGA DAC write regs=%03x, on=%d, display control=%02x, on1=%x, clocksel=%02x.\n",
|
|
|
|
|
addr, dev->on, dev->disp_cntl & 0x60, dev->accel.advfunc_cntl & 0x01, mach->accel.clock_sel & 0x01);
|
2024-11-03 04:46:32 +01:00
|
|
|
} else if ((addr >= 0x2ea) && (addr <= 0x2ed))
|
2025-02-01 03:29:03 -05:00
|
|
|
mach_log("8514/A DAC write regs=%03x, on=%d, display control=%02x, on1=%x, clocksel=%02x.\n",
|
|
|
|
|
addr, dev->on, dev->disp_cntl & 0x60, dev->accel.advfunc_cntl & 0x01, mach->accel.clock_sel & 0x01);
|
2024-11-02 20:50:06 +01:00
|
|
|
}
|
|
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
switch (addr) {
|
|
|
|
|
case 0x1ce:
|
|
|
|
|
mach->index = val;
|
|
|
|
|
break;
|
|
|
|
|
case 0x1cf:
|
2023-07-30 18:33:29 -04:00
|
|
|
old = mach->regs[mach->index];
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->regs[mach->index] = val;
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_log("ATI VGA write reg=%02x, val=%02x.\n", mach->index, val);
|
2023-07-14 23:38:04 +02:00
|
|
|
switch (mach->index) {
|
|
|
|
|
case 0xa3:
|
2024-11-02 20:50:06 +01:00
|
|
|
if ((old ^ val) & 0x10) {
|
|
|
|
|
mach_log("ATI A3 bit 7.\n");
|
2023-07-14 23:38:04 +02:00
|
|
|
svga_recalctimings(svga);
|
2024-11-02 20:50:06 +01:00
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 0xa7:
|
2024-11-02 20:50:06 +01:00
|
|
|
if ((old ^ val) & 0x80) {
|
|
|
|
|
mach_log("ATI A7 bit 7.\n");
|
2023-07-14 23:38:04 +02:00
|
|
|
svga_recalctimings(svga);
|
2024-11-02 20:50:06 +01:00
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 0xad:
|
2023-12-06 15:00:31 +01:00
|
|
|
if ((dev->local & 0xff) >= 0x02) {
|
2024-11-02 20:50:06 +01:00
|
|
|
if ((old ^ val) & 0x0c) {
|
|
|
|
|
mach_log("ATI AD bits 2-3.\n");
|
2023-07-14 23:38:04 +02:00
|
|
|
svga_recalctimings(svga);
|
2024-11-02 20:50:06 +01:00
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0xb0:
|
2024-11-02 20:50:06 +01:00
|
|
|
if ((old ^ val) & 0x60) {
|
|
|
|
|
mach_log("ATI B0 bits 5-6: old=%02x, val=%02x.\n", old & 0x60, val & 0x60);
|
2023-07-14 23:38:04 +02:00
|
|
|
svga_recalctimings(svga);
|
2024-11-02 20:50:06 +01:00
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 0xae:
|
|
|
|
|
case 0xb2:
|
|
|
|
|
case 0xbe:
|
|
|
|
|
mach_log("ATI VGA write reg=0x%02X, val=0x%02X\n", mach->index, val);
|
|
|
|
|
if (mach->regs[0xbe] & 0x08) { /* Read/write bank mode */
|
|
|
|
|
mach->bank_r = (((mach->regs[0xb2] & 1) << 3) | ((mach->regs[0xb2] & 0xe0) >> 5));
|
|
|
|
|
mach->bank_w = ((mach->regs[0xb2] & 0x1e) >> 1);
|
2023-12-06 15:00:31 +01:00
|
|
|
if ((dev->local & 0xff) >= 0x02) {
|
2023-06-09 23:46:54 -04:00
|
|
|
mach->bank_r |= ((mach->regs[0xae] & 0x0c) << 2);
|
|
|
|
|
mach->bank_w |= ((mach->regs[0xae] & 3) << 4);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
2024-10-26 21:32:47 +02:00
|
|
|
if (dev->on)
|
2023-07-14 23:38:04 +02:00
|
|
|
mach_log("Separate B2Bank = %02x, AEbank = %02x.\n", mach->regs[0xb2], mach->regs[0xae]);
|
|
|
|
|
} else { /* Single bank mode */
|
|
|
|
|
mach->bank_w = ((mach->regs[0xb2] & 0x1e) >> 1);
|
2024-10-26 21:32:47 +02:00
|
|
|
if ((dev->local & 0xff) >= 0x02)
|
2023-06-09 23:46:54 -04:00
|
|
|
mach->bank_w |= ((mach->regs[0xae] & 3) << 4);
|
2024-10-26 21:32:47 +02:00
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->bank_r = mach->bank_w;
|
2024-10-26 21:32:47 +02:00
|
|
|
if (dev->on)
|
2023-07-14 23:38:04 +02:00
|
|
|
mach_log("Single B2Bank = %02x, AEbank = %02x.\n", mach->regs[0xb2], mach->regs[0xae]);
|
|
|
|
|
}
|
2023-07-30 18:33:29 -04:00
|
|
|
svga->read_bank = mach->bank_r << 16;
|
2023-07-14 23:38:04 +02:00
|
|
|
svga->write_bank = mach->bank_w << 16;
|
|
|
|
|
|
|
|
|
|
if (mach->index == 0xbe) {
|
2024-11-02 20:50:06 +01:00
|
|
|
if ((old ^ val) & 0x10) {
|
|
|
|
|
mach_log("ATI BE bit 4.\n");
|
2023-07-14 23:38:04 +02:00
|
|
|
svga_recalctimings(svga);
|
2024-11-02 20:50:06 +01:00
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0xbd:
|
2024-11-02 20:50:06 +01:00
|
|
|
if ((old ^ val) & 0x04)
|
2024-01-15 21:43:33 +01:00
|
|
|
mach32_updatemapping(mach, svga);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 0xb3:
|
2024-11-02 20:50:06 +01:00
|
|
|
ati_eeprom_write(&mach->eeprom, val & 0x08, val & 0x02, val & 0x01);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 0xb6:
|
2024-11-02 20:50:06 +01:00
|
|
|
if ((old ^ val) & 0x10) {
|
|
|
|
|
mach_log("ATI B6 bit 4.\n");
|
2023-07-14 23:38:04 +02:00
|
|
|
svga_recalctimings(svga);
|
2024-11-02 20:50:06 +01:00
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 0xb8:
|
2023-12-06 15:00:31 +01:00
|
|
|
if ((dev->local & 0xff) >= 0x02) {
|
2024-11-02 20:50:06 +01:00
|
|
|
if ((old ^ val) & 0x40) {
|
|
|
|
|
mach_log("ATI B8 bit 6.\n");
|
2023-07-14 23:38:04 +02:00
|
|
|
svga_recalctimings(svga);
|
2024-11-02 20:50:06 +01:00
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
} else {
|
|
|
|
|
if ((old ^ val) & 0xc0)
|
|
|
|
|
svga_recalctimings(svga);
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0xb9:
|
2024-11-02 20:50:06 +01:00
|
|
|
if ((old ^ val) & 0x02) {
|
|
|
|
|
mach_log("ATI B9 bit 1.\n");
|
2023-07-14 23:38:04 +02:00
|
|
|
svga_recalctimings(svga);
|
2024-11-02 20:50:06 +01:00
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
2023-06-09 23:46:54 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x2ea:
|
|
|
|
|
case 0x2eb:
|
|
|
|
|
case 0x2ec:
|
|
|
|
|
case 0x2ed:
|
|
|
|
|
rs2 = !!(mach->accel.ext_ge_config & 0x1000);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
rs3 = !!(mach->accel.ext_ge_config & 0x2000);
|
2023-12-06 15:00:31 +01:00
|
|
|
if ((dev->local & 0xff) >= 0x02) {
|
2024-11-03 23:21:18 +01:00
|
|
|
if (mach->regs[0xb0] & 0x20) { /*ATI extended 8514/A mode.*/
|
2024-11-05 01:08:13 +01:00
|
|
|
mach_log("Extended 8514/A mode.\n");
|
2024-11-03 23:21:18 +01:00
|
|
|
dev->vendor_mode = 1;
|
2024-11-03 04:46:32 +01:00
|
|
|
dev->on |= 0x01;
|
|
|
|
|
svga_recalctimings(svga);
|
|
|
|
|
mach32_updatemapping(mach, svga);
|
2024-11-02 20:50:06 +01:00
|
|
|
}
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (mach->pci_bus && !mach->ramdac_type)
|
2024-11-02 20:50:06 +01:00
|
|
|
ati68860_ramdac_out((addr & 0x03) | (rs2 << 2) | (rs3 << 3), val, svga->ramdac, svga);
|
2023-07-14 23:38:04 +02:00
|
|
|
else
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
ati68875_ramdac_out(addr, rs2, rs3, val, svga->ramdac, svga);
|
2023-07-14 23:38:04 +02:00
|
|
|
} else
|
|
|
|
|
svga_out(addr, val, svga);
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
case 0x3C6:
|
|
|
|
|
case 0x3C7:
|
|
|
|
|
case 0x3C8:
|
|
|
|
|
case 0x3C9:
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
rs2 = !!(mach->regs[0xa0] & 0x20);
|
|
|
|
|
rs3 = !!(mach->regs[0xa0] & 0x40);
|
2023-12-06 15:00:31 +01:00
|
|
|
if ((dev->local & 0xff) >= 0x02) {
|
2024-11-05 01:08:13 +01:00
|
|
|
if (svga->attrregs[0x10] & 0x40) {
|
|
|
|
|
mach_log("VGA mode.\n");
|
2024-11-03 23:21:18 +01:00
|
|
|
dev->vendor_mode = 0;
|
2024-11-03 04:46:32 +01:00
|
|
|
dev->on &= ~0x01;
|
|
|
|
|
svga_recalctimings(svga);
|
|
|
|
|
mach32_updatemapping(mach, svga);
|
2024-11-02 20:50:06 +01:00
|
|
|
}
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (mach->pci_bus && !mach->ramdac_type)
|
2024-11-02 20:50:06 +01:00
|
|
|
ati68860_ramdac_out((addr & 0x03) | (rs2 << 2) | (rs3 << 3), val, svga->ramdac, svga);
|
2023-07-14 23:38:04 +02:00
|
|
|
else
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
ati68875_ramdac_out(addr, rs2, rs3, val, svga->ramdac, svga);
|
2023-07-14 23:38:04 +02:00
|
|
|
} else
|
|
|
|
|
svga_out(addr, val, svga);
|
|
|
|
|
return;
|
|
|
|
|
|
2024-11-03 04:46:32 +01:00
|
|
|
case 0x3CF:
|
|
|
|
|
if (svga->gdcaddr == 6) {
|
|
|
|
|
uint8_t old_val = svga->gdcreg[6];
|
|
|
|
|
svga->gdcreg[6] = val;
|
|
|
|
|
if ((svga->gdcreg[6] & 0xc) != (old_val & 0xc)) {
|
|
|
|
|
mach_log("GDCREG6=%02x.\n", svga->gdcreg[6] & 0xc);
|
|
|
|
|
mach32_updatemapping(mach, svga);
|
|
|
|
|
}
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
case 0x3D4:
|
|
|
|
|
svga->crtcreg = val & 0x3f;
|
|
|
|
|
return;
|
|
|
|
|
case 0x3D5:
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (svga->crtcreg & 0x20)
|
2023-07-14 23:38:04 +02:00
|
|
|
return;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80) && !(mach->regs[0xb4] & 0x80))
|
|
|
|
|
return;
|
|
|
|
|
if ((svga->crtcreg == 7) && (svga->crtc[0x11] & 0x80) && !(mach->regs[0xb4] & 0x80))
|
2023-07-14 23:38:04 +02:00
|
|
|
val = (svga->crtc[7] & ~0x10) | (val & 0x10);
|
|
|
|
|
|
|
|
|
|
old = svga->crtc[svga->crtcreg];
|
|
|
|
|
svga->crtc[svga->crtcreg] = val;
|
|
|
|
|
if (old != val) {
|
|
|
|
|
if (svga->crtcreg < 0xe || svga->crtcreg > 0x10) {
|
|
|
|
|
if ((svga->crtcreg == 0xc) || (svga->crtcreg == 0xd)) {
|
|
|
|
|
svga->fullchange = 3;
|
|
|
|
|
svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]) + ((svga->crtc[8] & 0x60) >> 5);
|
|
|
|
|
} else {
|
|
|
|
|
svga->fullchange = changeframecount;
|
|
|
|
|
svga_recalctimings(svga);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
2023-06-09 23:46:54 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
svga_out(addr, val, svga);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static uint8_t
|
2023-06-09 23:46:54 -04:00
|
|
|
mach_in(uint16_t addr, void *priv)
|
2023-07-14 23:38:04 +02:00
|
|
|
{
|
2023-07-30 18:33:29 -04:00
|
|
|
mach_t *mach = (mach_t *) priv;
|
|
|
|
|
svga_t *svga = &mach->svga;
|
2024-11-02 20:50:06 +01:00
|
|
|
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
uint8_t temp = 0xff;
|
2023-07-30 18:33:29 -04:00
|
|
|
uint8_t rs2;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
uint8_t rs3;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
|
|
|
|
if (((addr & 0xFFF0) == 0x3D0 || (addr & 0xFFF0) == 0x3B0) && !(svga->miscout & 1))
|
|
|
|
|
addr ^= 0x60;
|
|
|
|
|
|
2024-11-03 04:46:32 +01:00
|
|
|
if ((addr >= 0x3c6) && (addr <= 0x3c9) && dev->on) {
|
2024-05-29 20:47:22 +02:00
|
|
|
addr -= 0xdc;
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_log("VGA DAC read regs=%03x.\n", addr);
|
|
|
|
|
} else if ((addr >= 0x2ea) && (addr <= 0x2ed))
|
|
|
|
|
mach_log("8514/A DAC read regs=%03x.\n", addr);
|
2024-05-29 20:47:22 +02:00
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
switch (addr) {
|
|
|
|
|
case 0x1ce:
|
|
|
|
|
temp = mach->index;
|
|
|
|
|
break;
|
|
|
|
|
case 0x1cf:
|
|
|
|
|
switch (mach->index) {
|
2024-01-15 21:43:33 +01:00
|
|
|
case 0xa0:
|
|
|
|
|
temp = mach->regs[0xa0] | 0x10;
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
case 0xa8:
|
|
|
|
|
temp = (svga->vc >> 8) & 3;
|
|
|
|
|
break;
|
|
|
|
|
case 0xa9:
|
|
|
|
|
temp = svga->vc & 0xff;
|
|
|
|
|
break;
|
|
|
|
|
case 0xb0:
|
|
|
|
|
temp = mach->regs[0xb0] | 0x80;
|
2024-01-15 21:43:33 +01:00
|
|
|
temp &= ~0x18;
|
2023-12-06 15:00:31 +01:00
|
|
|
if ((dev->local & 0xff) >= 0x02) { /*Mach32 VGA 1MB memory*/
|
2023-07-14 23:38:04 +02:00
|
|
|
temp |= 0x08;
|
|
|
|
|
} else { /*ATI 28800 VGA 512kB memory*/
|
|
|
|
|
temp |= 0x10;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0xb7:
|
2024-05-29 20:47:22 +02:00
|
|
|
temp = mach->regs[0xb7] & ~0x08;
|
2023-07-14 23:38:04 +02:00
|
|
|
if (ati_eeprom_read(&mach->eeprom))
|
2024-05-29 20:47:22 +02:00
|
|
|
temp |= 0x08;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
2023-08-15 22:12:30 +02:00
|
|
|
case 0xbd:
|
|
|
|
|
temp = mach->regs[0xbd] | 0x10;
|
|
|
|
|
break;
|
|
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
default:
|
|
|
|
|
temp = mach->regs[mach->index];
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x2ea:
|
|
|
|
|
case 0x2eb:
|
|
|
|
|
case 0x2ec:
|
|
|
|
|
case 0x2ed:
|
|
|
|
|
rs2 = !!(mach->accel.ext_ge_config & 0x1000);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
rs3 = !!(mach->accel.ext_ge_config & 0x2000);
|
2023-12-06 15:00:31 +01:00
|
|
|
if ((dev->local & 0xff) >= 0x02) {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (mach->pci_bus && !mach->ramdac_type)
|
|
|
|
|
temp = ati68860_ramdac_in((addr & 3) | (rs2 << 2) | (rs3 << 3), svga->ramdac, svga);
|
2023-07-14 23:38:04 +02:00
|
|
|
else
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
temp = ati68875_ramdac_in(addr, rs2, rs3, svga->ramdac, svga);
|
|
|
|
|
} else
|
|
|
|
|
temp = svga_in(addr, svga);
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
|
|
|
|
case 0x3D4:
|
|
|
|
|
temp = svga->crtcreg;
|
|
|
|
|
break;
|
|
|
|
|
case 0x3D5:
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (svga->crtcreg & 0x20)
|
|
|
|
|
temp = 0xff;
|
2023-07-14 23:38:04 +02:00
|
|
|
else
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
temp = svga->crtc[svga->crtcreg];
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
temp = svga_in(addr, svga);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
return temp;
|
|
|
|
|
}
|
|
|
|
|
|
2024-11-02 20:50:06 +01:00
|
|
|
void
|
2024-01-15 21:43:33 +01:00
|
|
|
ati8514_out(uint16_t addr, uint8_t val, void *priv)
|
|
|
|
|
{
|
2024-05-29 20:47:22 +02:00
|
|
|
mach_log("[%04X:%08X]: ADDON OUT addr=%03x, val=%02x.\n", CS, cpu_state.pc, addr, val);
|
2024-11-02 20:50:06 +01:00
|
|
|
|
2024-11-03 23:21:18 +01:00
|
|
|
svga_out(addr, val, priv);
|
2024-01-15 21:43:33 +01:00
|
|
|
}
|
|
|
|
|
|
2024-11-02 20:50:06 +01:00
|
|
|
uint8_t
|
2024-01-15 21:43:33 +01:00
|
|
|
ati8514_in(uint16_t addr, void *priv)
|
|
|
|
|
{
|
|
|
|
|
uint8_t temp = 0xff;
|
|
|
|
|
|
2024-11-03 23:21:18 +01:00
|
|
|
temp = svga_in(addr, priv);
|
2024-01-15 21:43:33 +01:00
|
|
|
|
2024-05-29 20:47:22 +02:00
|
|
|
mach_log("[%04X:%08X]: ADDON IN addr=%03x, temp=%02x.\n", CS, cpu_state.pc, addr, temp);
|
2024-01-15 21:43:33 +01:00
|
|
|
return temp;
|
|
|
|
|
}
|
|
|
|
|
|
2025-01-26 14:25:35 +01:00
|
|
|
static void
|
|
|
|
|
ati_render_24bpp(svga_t *svga)
|
|
|
|
|
{
|
|
|
|
|
mach_t *mach = (mach_t *) svga->priv;
|
|
|
|
|
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
|
|
|
|
uint32_t *p;
|
|
|
|
|
uint32_t dat;
|
|
|
|
|
|
|
|
|
|
if ((dev->displine + svga->y_add) < 0)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
if (dev->changedvram[dev->ma >> 12] || dev->changedvram[(dev->ma >> 12) + 1] || svga->fullchange) {
|
|
|
|
|
p = &buffer32->line[dev->displine + svga->y_add][svga->x_add];
|
|
|
|
|
|
|
|
|
|
if (dev->firstline_draw == 2000)
|
|
|
|
|
dev->firstline_draw = dev->displine;
|
|
|
|
|
dev->lastline_draw = dev->displine;
|
|
|
|
|
|
|
|
|
|
if (mach->accel.ext_ge_config & 0x400) { /*BGR, Blue-(23:16), Green-(15:8), Red-(7:0)*/
|
|
|
|
|
for (int x = 0; x <= dev->h_disp; x += 4) {
|
|
|
|
|
dat = *(uint32_t *) (&dev->vram[dev->ma & dev->vram_mask]);
|
|
|
|
|
p[x] = ((dat & 0xff0000) >> 16) | (dat & 0x00ff00) | ((dat & 0x0000ff) << 16);
|
|
|
|
|
|
|
|
|
|
dat = *(uint32_t *) (&dev->vram[(dev->ma + 3) & dev->vram_mask]);
|
|
|
|
|
p[x + 1] = ((dat & 0xff0000) >> 16) | (dat & 0x00ff00) | ((dat & 0x0000ff) << 16);
|
|
|
|
|
|
|
|
|
|
dat = *(uint32_t *) (&dev->vram[(dev->ma + 6) & dev->vram_mask]);
|
|
|
|
|
p[x + 2] = ((dat & 0xff0000) >> 16) | (dat & 0x00ff00) | ((dat & 0x0000ff) << 16);
|
|
|
|
|
|
|
|
|
|
dat = *(uint32_t *) (&dev->vram[(dev->ma + 9) & dev->vram_mask]);
|
|
|
|
|
p[x + 3] = ((dat & 0xff0000) >> 16) | (dat & 0x00ff00) | ((dat & 0x0000ff) << 16);
|
|
|
|
|
|
|
|
|
|
dev->ma += 12;
|
|
|
|
|
}
|
|
|
|
|
} else { /*RGB, Red-(23:16), Green-(15:8), Blue-(7:0)*/
|
|
|
|
|
for (int x = 0; x <= dev->h_disp; x += 4) {
|
|
|
|
|
dat = *(uint32_t *) (&dev->vram[dev->ma & dev->vram_mask]);
|
|
|
|
|
p[x] = dat & 0xffffff;
|
|
|
|
|
|
|
|
|
|
dat = *(uint32_t *) (&dev->vram[(dev->ma + 3) & dev->vram_mask]);
|
|
|
|
|
p[x + 1] = dat & 0xffffff;
|
|
|
|
|
|
|
|
|
|
dat = *(uint32_t *) (&dev->vram[(dev->ma + 6) & dev->vram_mask]);
|
|
|
|
|
p[x + 2] = dat & 0xffffff;
|
|
|
|
|
|
|
|
|
|
dat = *(uint32_t *) (&dev->vram[(dev->ma + 9) & dev->vram_mask]);
|
|
|
|
|
p[x + 3] = dat & 0xffffff;
|
|
|
|
|
|
|
|
|
|
dev->ma += 12;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
dev->ma &= dev->vram_mask;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
ati_render_32bpp(svga_t *svga)
|
|
|
|
|
{
|
|
|
|
|
mach_t *mach = (mach_t *) svga->priv;
|
|
|
|
|
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
|
|
|
|
int x;
|
|
|
|
|
uint32_t *p;
|
|
|
|
|
uint32_t dat;
|
|
|
|
|
|
|
|
|
|
if ((dev->displine + svga->y_add) < 0)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
if (dev->changedvram[dev->ma >> 12] || dev->changedvram[(dev->ma >> 12) + 1] || dev->changedvram[(dev->ma >> 12) + 2] || svga->fullchange) {
|
|
|
|
|
p = &buffer32->line[dev->displine + svga->y_add][svga->x_add];
|
|
|
|
|
|
|
|
|
|
if (dev->firstline_draw == 2000)
|
|
|
|
|
dev->firstline_draw = dev->displine;
|
|
|
|
|
dev->lastline_draw = dev->displine;
|
|
|
|
|
|
|
|
|
|
if (mach->accel.ext_ge_config & 0x400) { /*BGR, Blue-(23:16), Green-(15:8), Red-(7:0)*/
|
|
|
|
|
for (x = 0; x <= dev->h_disp; x++) {
|
|
|
|
|
dat = *(uint32_t *) (&dev->vram[(dev->ma + (x << 2)) & dev->vram_mask]);
|
|
|
|
|
*p++ = ((dat & 0x00ff0000) >> 16) | (dat & 0x0000ff00) | ((dat & 0x000000ff) << 16);
|
|
|
|
|
}
|
|
|
|
|
} else { /*RGB, Red-(31:24), Green-(23:16), Blue-(15:8)*/
|
|
|
|
|
for (x = 0; x <= dev->h_disp; x++) {
|
|
|
|
|
dat = *(uint32_t *) (&dev->vram[(dev->ma + (x << 2)) & dev->vram_mask]);
|
|
|
|
|
*p++ = ((dat & 0xffffff00) >> 8);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
dev->ma += (x * 4);
|
|
|
|
|
dev->ma &= dev->vram_mask;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2024-01-15 21:43:33 +01:00
|
|
|
void
|
|
|
|
|
ati8514_recalctimings(svga_t *svga)
|
|
|
|
|
{
|
2024-05-29 20:47:22 +02:00
|
|
|
mach_t *mach = (mach_t *) svga->ext8514;
|
2024-01-15 21:43:33 +01:00
|
|
|
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
|
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
mach_log("ON=%d, vgahdisp=%d.\n", dev->on, svga->hdisp);
|
|
|
|
|
if (dev->on) {
|
2024-05-29 20:47:22 +02:00
|
|
|
mach_log("8514/A ON.\n");
|
2024-11-02 20:50:06 +01:00
|
|
|
dev->pitch = dev->ext_pitch;
|
|
|
|
|
dev->rowoffset = dev->ext_crt_pitch;
|
2024-01-15 21:43:33 +01:00
|
|
|
dev->h_total = dev->htotal + 1;
|
|
|
|
|
dev->rowcount = !!(dev->disp_cntl & 0x08);
|
2024-05-29 20:47:22 +02:00
|
|
|
dev->accel.ge_offset = (mach->accel.ge_offset_lo | (mach->accel.ge_offset_hi << 16));
|
|
|
|
|
mach->accel.ge_offset = dev->accel.ge_offset;
|
2024-01-15 21:43:33 +01:00
|
|
|
|
2025-02-01 03:29:03 -05:00
|
|
|
mach_log("HDISP=%d, VDISP=%d, shadowset=%x, 8514/A mode=%x, clocksel=%02x.\n",
|
|
|
|
|
dev->hdisp, dev->vdisp, mach->shadow_set & 0x03, dev->accel.advfunc_cntl & 0x05, mach->accel.clock_sel & 0x01);
|
2024-10-26 21:32:47 +02:00
|
|
|
|
2024-11-02 20:50:06 +01:00
|
|
|
if (mach->accel.clock_sel & 0x01) {
|
2024-10-26 21:32:47 +02:00
|
|
|
dev->h_disp = dev->hdisp;
|
|
|
|
|
dev->dispend = dev->vdisp;
|
|
|
|
|
} else {
|
2024-05-29 20:47:22 +02:00
|
|
|
if (dev->accel.advfunc_cntl & 0x04) {
|
2024-11-13 22:55:16 +01:00
|
|
|
if (dev->hdisp == 640) {
|
|
|
|
|
dev->h_disp = 1024;
|
|
|
|
|
dev->dispend = 768;
|
|
|
|
|
} else {
|
|
|
|
|
dev->h_disp = dev->hdisp;
|
|
|
|
|
dev->dispend = dev->vdisp;
|
|
|
|
|
}
|
2024-05-29 20:47:22 +02:00
|
|
|
} else {
|
|
|
|
|
dev->h_disp = 640;
|
|
|
|
|
dev->dispend = 480;
|
2024-01-15 21:43:33 +01:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2024-10-03 14:56:23 +02:00
|
|
|
if (dev->accel.advfunc_cntl & 0x04)
|
2024-05-29 20:47:22 +02:00
|
|
|
svga->clock8514 = (cpuclock * (double) (1ULL << 32)) / 44900000.0;
|
2024-10-03 14:56:23 +02:00
|
|
|
else
|
2024-05-29 20:47:22 +02:00
|
|
|
svga->clock8514 = (cpuclock * (double) (1ULL << 32)) / 25175000.0;
|
2024-10-03 14:56:23 +02:00
|
|
|
|
|
|
|
|
if (dev->interlace)
|
|
|
|
|
dev->dispend >>= 1;
|
2024-01-15 21:43:33 +01:00
|
|
|
|
2025-02-01 03:29:03 -05:00
|
|
|
mach_log("cntl=%d, hv(%d,%d), pitch=%d, rowoffset=%d, gextconfig=%03x, shadow=%x interlace=%d.\n",
|
|
|
|
|
dev->accel.advfunc_cntl & 0x04, dev->h_disp, dev->dispend, dev->pitch, dev->rowoffset,
|
|
|
|
|
mach->accel.ext_ge_config & 0xcec0, mach->shadow_set & 3, dev->interlace);
|
2024-10-26 21:32:47 +02:00
|
|
|
if (dev->vram_512k_8514) {
|
|
|
|
|
if (dev->h_disp == 640) {
|
|
|
|
|
dev->ext_pitch = 640;
|
|
|
|
|
dev->pitch = dev->ext_pitch;
|
|
|
|
|
} else {
|
|
|
|
|
dev->ext_pitch = 1024;
|
|
|
|
|
dev->pitch = dev->ext_pitch;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
dev->accel_bpp = 8;
|
2024-01-15 21:43:33 +01:00
|
|
|
svga->render8514 = ibm8514_render_8bpp;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
static void
|
|
|
|
|
mach_recalctimings(svga_t *svga)
|
|
|
|
|
{
|
2024-01-15 21:43:33 +01:00
|
|
|
mach_t *mach = (mach_t *) svga->priv;
|
2023-10-09 20:14:03 +02:00
|
|
|
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
2023-08-14 18:59:02 -04:00
|
|
|
int clock_sel;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
2024-01-13 03:54:56 +01:00
|
|
|
if (mach->regs[0xad] & 0x08)
|
2024-02-18 17:54:14 +01:00
|
|
|
svga->hblankstart = ((mach->regs[0x0d] >> 2) << 8) + svga->crtc[2];
|
2024-01-15 21:43:33 +01:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
clock_sel = ((svga->miscout >> 2) & 3) | ((mach->regs[0xbe] & 0x10) >> 1) | ((mach->regs[0xb9] & 2) << 1);
|
2023-07-14 23:38:04 +02:00
|
|
|
|
2023-12-06 15:00:31 +01:00
|
|
|
if ((dev->local & 0xff) >= 0x02) {
|
2023-07-14 23:38:04 +02:00
|
|
|
if (mach->regs[0xad] & 0x04)
|
|
|
|
|
svga->ma_latch |= 0x40000;
|
|
|
|
|
|
|
|
|
|
if (mach->regs[0xad] & 0x08)
|
|
|
|
|
svga->ma_latch |= 0x80000;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (mach->regs[0xa3] & 0x10)
|
|
|
|
|
svga->ma_latch |= 0x10000;
|
2023-06-09 23:46:54 -04:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (mach->regs[0xb0] & 0x40)
|
|
|
|
|
svga->ma_latch |= 0x20000;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
2023-12-27 16:07:03 +01:00
|
|
|
if ((mach->regs[0xb6] & 0x18) >= 0x10) {
|
2023-07-14 23:38:04 +02:00
|
|
|
svga->hdisp <<= 1;
|
|
|
|
|
svga->htotal <<= 1;
|
2024-02-07 00:11:02 +01:00
|
|
|
svga->dots_per_clock <<= 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
svga->rowoffset <<= 1;
|
|
|
|
|
}
|
|
|
|
|
|
2023-12-27 16:07:03 +01:00
|
|
|
if (mach->regs[0xb0] & 0x20) {
|
|
|
|
|
if ((mach->regs[0xb6] & 0x18) >= 0x10)
|
|
|
|
|
svga->packed_4bpp = 1;
|
|
|
|
|
else
|
|
|
|
|
svga->packed_4bpp = 0;
|
|
|
|
|
} else
|
|
|
|
|
svga->packed_4bpp = 0;
|
|
|
|
|
|
|
|
|
|
if ((dev->local & 0xff) < 0x02) {
|
2024-11-02 20:50:06 +01:00
|
|
|
if ((mach->regs[0xb6] & 0x18) == 0x08) {
|
2023-12-27 16:07:03 +01:00
|
|
|
svga->hdisp <<= 1;
|
|
|
|
|
svga->htotal <<= 1;
|
2024-02-07 00:11:02 +01:00
|
|
|
svga->dots_per_clock <<= 1;
|
2023-12-27 16:07:03 +01:00
|
|
|
svga->ati_4color = 1;
|
|
|
|
|
} else
|
|
|
|
|
svga->ati_4color = 0;
|
|
|
|
|
}
|
2024-02-07 01:53:16 +01:00
|
|
|
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_log("ON?=%d, override=%d.\n", dev->on, svga->override);
|
2024-10-26 21:32:47 +02:00
|
|
|
if (dev->on) {
|
|
|
|
|
mach_log("8514/A ON, extpitch=%d, devma=%x, vgamalatch=%x.\n", dev->ext_pitch, dev->ma, svga->ma_latch);
|
|
|
|
|
dev->pitch = dev->ext_pitch;
|
|
|
|
|
dev->rowoffset = dev->ext_crt_pitch;
|
2024-01-15 21:43:33 +01:00
|
|
|
dev->h_total = dev->htotal + 1;
|
|
|
|
|
dev->rowcount = !!(dev->disp_cntl & 0x08);
|
2024-05-29 20:47:22 +02:00
|
|
|
dev->accel.ge_offset = (mach->accel.ge_offset_lo | (mach->accel.ge_offset_hi << 16));
|
|
|
|
|
mach->accel.ge_offset = dev->accel.ge_offset;
|
|
|
|
|
|
2025-02-01 03:29:03 -05:00
|
|
|
mach_log("HDISP=%d, VDISP=%d, shadowset=%x, 8514/A mode=%x, clocksel=%02x, interlace=%x.\n",
|
|
|
|
|
dev->hdisp, dev->vdisp, mach->shadow_set & 0x03, dev->accel.advfunc_cntl & 0x04,
|
|
|
|
|
mach->accel.clock_sel & 0xfe, dev->interlace);
|
2024-10-26 21:32:47 +02:00
|
|
|
if ((dev->local & 0xff) >= 0x02) {
|
2024-11-02 20:50:06 +01:00
|
|
|
if (dev->bpp || ((mach->accel.ext_ge_config & 0x30) == 0x30) || (mach->accel.clock_sel & 0x01)) {
|
2024-10-26 21:32:47 +02:00
|
|
|
dev->h_disp = dev->hdisp;
|
|
|
|
|
dev->dispend = dev->vdisp;
|
|
|
|
|
} else {
|
|
|
|
|
if (dev->interlace) { /*Interlaced displays are only for 800x600 and up.*/
|
|
|
|
|
if (dev->accel.advfunc_cntl & 0x04) {
|
|
|
|
|
dev->h_disp = dev->hdisp;
|
|
|
|
|
dev->dispend = dev->vdisp;
|
|
|
|
|
} else {
|
|
|
|
|
dev->h_disp = 640;
|
|
|
|
|
dev->dispend = 480;
|
|
|
|
|
}
|
|
|
|
|
} else {
|
2024-10-27 23:36:11 +01:00
|
|
|
if (((mach->shadow_set & 0x03) == 0x00) && ((dev->hdisp2 == 640) || (dev->hdisp2 == 1280)) && (dev->hdisp != 800)) {
|
|
|
|
|
dev->h_disp = dev->hdisp2;
|
|
|
|
|
dev->dispend = dev->vdisp2;
|
|
|
|
|
} else {
|
|
|
|
|
dev->h_disp = dev->hdisp;
|
|
|
|
|
dev->dispend = dev->vdisp;
|
|
|
|
|
}
|
2024-05-29 20:47:22 +02:00
|
|
|
}
|
2024-10-26 21:32:47 +02:00
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
if (mach->accel.clock_sel & 0x01) {
|
2024-05-29 20:47:22 +02:00
|
|
|
dev->h_disp = dev->hdisp;
|
|
|
|
|
dev->dispend = dev->vdisp;
|
2024-10-26 21:32:47 +02:00
|
|
|
} else {
|
|
|
|
|
if (dev->accel.advfunc_cntl & 0x04) {
|
|
|
|
|
dev->h_disp = dev->hdisp;
|
|
|
|
|
dev->dispend = dev->vdisp;
|
|
|
|
|
} else {
|
|
|
|
|
dev->h_disp = 640;
|
|
|
|
|
dev->dispend = 480;
|
|
|
|
|
}
|
2024-04-20 23:43:27 +02:00
|
|
|
}
|
|
|
|
|
}
|
2024-03-01 19:50:23 +01:00
|
|
|
|
2024-05-29 20:47:22 +02:00
|
|
|
svga->clock8514 = (cpuclock * (double) (1ULL << 32)) / svga->getclock((mach->accel.clock_sel >> 2) & 0x0f, svga->clock_gen);
|
2024-09-22 21:05:10 +02:00
|
|
|
if (mach->accel.clock_sel & 0x40)
|
|
|
|
|
svga->clock8514 *= 2;
|
2024-05-29 20:47:22 +02:00
|
|
|
|
|
|
|
|
if (dev->interlace)
|
|
|
|
|
dev->dispend >>= 1;
|
|
|
|
|
|
2023-12-06 15:00:31 +01:00
|
|
|
if ((dev->local & 0xff) >= 0x02) {
|
2024-10-26 21:32:47 +02:00
|
|
|
mach_log("HDISP=%d, mask=%02x.\n", dev->h_disp, dev->dac_mask);
|
2023-08-14 18:59:02 -04:00
|
|
|
if ((mach->accel.ext_ge_config & 0x800) || (!(mach->accel.ext_ge_config & 0x8000) && !(mach->accel.ext_ge_config & 0x800))) {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if ((mach->accel.ext_ge_config & 0x30) == 0x20) {
|
|
|
|
|
if ((mach->accel.ext_ge_config & 0xc0) == 0x40)
|
2023-08-15 00:11:56 +02:00
|
|
|
dev->accel_bpp = 16;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
else
|
2023-08-15 00:11:56 +02:00
|
|
|
dev->accel_bpp = 15;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
} else if ((mach->accel.ext_ge_config & 0x30) == 0x30) {
|
|
|
|
|
if (mach->accel.ext_ge_config & 0x200)
|
2023-08-15 00:11:56 +02:00
|
|
|
dev->accel_bpp = 32;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
else
|
2023-08-15 00:11:56 +02:00
|
|
|
dev->accel_bpp = 24;
|
2024-10-26 21:32:47 +02:00
|
|
|
} else if ((mach->accel.ext_ge_config & 0x30) == 0x10)
|
2023-08-15 00:11:56 +02:00
|
|
|
dev->accel_bpp = 8;
|
2024-10-26 21:32:47 +02:00
|
|
|
else {
|
|
|
|
|
if (dev->vram_512k_8514) {
|
|
|
|
|
if (dev->h_disp == 640) {
|
|
|
|
|
dev->ext_pitch = 640;
|
|
|
|
|
dev->pitch = dev->ext_pitch;
|
|
|
|
|
} else {
|
|
|
|
|
dev->ext_pitch = 1024;
|
|
|
|
|
dev->pitch = dev->ext_pitch;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
dev->accel_bpp = 8;
|
|
|
|
|
}
|
2024-11-02 20:50:06 +01:00
|
|
|
|
|
|
|
|
svga->render8514 = ibm8514_render_blank;
|
2025-02-01 03:29:03 -05:00
|
|
|
mach_log("hv(%d,%d), pitch=%d, rowoffset=%d, gextconfig=%03x, bpp=%d, shadow=%x, vgahdisp=%d.\n",
|
|
|
|
|
dev->h_disp, dev->dispend, dev->pitch, dev->ext_crt_pitch, mach->accel.ext_ge_config & 0xcec0,
|
|
|
|
|
dev->accel_bpp, mach->shadow_set & 3, svga->hdisp);
|
2023-08-15 00:11:56 +02:00
|
|
|
switch (dev->accel_bpp) {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 8:
|
2023-08-15 00:11:56 +02:00
|
|
|
svga->render8514 = ibm8514_render_8bpp;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
break;
|
|
|
|
|
case 15:
|
2023-08-15 00:11:56 +02:00
|
|
|
svga->render8514 = ibm8514_render_15bpp;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
break;
|
|
|
|
|
case 16:
|
2023-08-15 00:11:56 +02:00
|
|
|
svga->render8514 = ibm8514_render_16bpp;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
break;
|
|
|
|
|
case 24:
|
2023-12-14 21:47:10 +01:00
|
|
|
mach_log("GEConfig24bpp: %03x.\n", mach->accel.ext_ge_config & 0x600);
|
2025-01-26 14:25:35 +01:00
|
|
|
svga->render8514 = ati_render_24bpp;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
break;
|
|
|
|
|
case 32:
|
2023-12-14 21:47:10 +01:00
|
|
|
mach_log("GEConfig32bpp: %03x.\n", mach->accel.ext_ge_config & 0x600);
|
2025-01-26 14:25:35 +01:00
|
|
|
svga->render8514 = ati_render_32bpp;
|
2023-08-11 20:32:56 -04:00
|
|
|
break;
|
2023-08-14 18:59:02 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
2023-08-15 00:11:56 +02:00
|
|
|
} else {
|
2024-11-02 20:50:06 +01:00
|
|
|
svga->render8514 = ibm8514_render_blank;
|
2025-02-01 03:29:03 -05:00
|
|
|
mach_log("cntl=%d, hv(%d,%d), pitch=%d, rowoffset=%d, gextconfig=%03x, shadow=%x interlace=%d.\n",
|
|
|
|
|
dev->accel.advfunc_cntl & 0x04, dev->h_disp, dev->dispend, dev->pitch, dev->rowoffset,
|
|
|
|
|
mach->accel.ext_ge_config & 0xcec0, mach->shadow_set & 3, dev->interlace);
|
2024-10-26 21:32:47 +02:00
|
|
|
if (dev->vram_512k_8514) {
|
|
|
|
|
if (dev->h_disp == 640) {
|
|
|
|
|
dev->ext_pitch = 640;
|
|
|
|
|
dev->pitch = dev->ext_pitch;
|
|
|
|
|
} else {
|
|
|
|
|
dev->ext_pitch = 1024;
|
|
|
|
|
dev->pitch = dev->ext_pitch;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
dev->accel_bpp = 8;
|
2023-08-15 00:11:56 +02:00
|
|
|
svga->render8514 = ibm8514_render_8bpp;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
}
|
2024-11-02 20:50:06 +01:00
|
|
|
} else {
|
|
|
|
|
if (!svga->scrblank && (svga->crtc[0x17] & 0x80) && svga->attr_palette_enable) {
|
2025-02-01 03:29:03 -05:00
|
|
|
mach_log("GDCREG5=%02x, ATTR10=%02x, ATI B0 bit 5=%02x, ON=%d.\n",
|
|
|
|
|
svga->gdcreg[5] & 0x60, svga->attrregs[0x10] & 0x40, mach->regs[0xb0] & 0x20, dev->on);
|
2024-11-02 20:50:06 +01:00
|
|
|
if ((svga->gdcreg[6] & 0x01) || (svga->attrregs[0x10] & 0x01)) {
|
|
|
|
|
if ((svga->gdcreg[5] & 0x40) || (svga->attrregs[0x10] & 0x40) || (mach->regs[0xb0] & 0x20)) {
|
|
|
|
|
svga->clock = (cpuclock * (double) (1ULL << 32)) / svga->getclock(clock_sel, svga->clock_gen);
|
|
|
|
|
mach_log("VGA clock=%02x.\n", mach->regs[0xa7] & 0x80);
|
|
|
|
|
if ((dev->local & 0xff) >= 0x02) {
|
|
|
|
|
if (mach->regs[0xb8] & 0x40)
|
|
|
|
|
svga->clock *= 2;
|
|
|
|
|
} else {
|
|
|
|
|
switch (mach->regs[0xb8] & 0xc0) {
|
|
|
|
|
case 0x40:
|
|
|
|
|
svga->clock *= 2;
|
|
|
|
|
break;
|
|
|
|
|
case 0x80:
|
|
|
|
|
svga->clock *= 3;
|
|
|
|
|
break;
|
|
|
|
|
case 0xc0:
|
|
|
|
|
svga->clock *= 4;
|
|
|
|
|
break;
|
2024-05-29 20:47:22 +02:00
|
|
|
|
2024-11-02 20:50:06 +01:00
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
}
|
2023-12-14 21:47:10 +01:00
|
|
|
}
|
2024-11-02 20:50:06 +01:00
|
|
|
svga->map8 = svga->pallook;
|
|
|
|
|
mach_log("Lowres=%x, seqreg[1]bit3=%x.\n", svga->lowres, svga->seqregs[1] & 8);
|
|
|
|
|
if (svga->lowres)
|
|
|
|
|
svga->render = svga_render_8bpp_lowres;
|
|
|
|
|
else {
|
|
|
|
|
svga->render = svga_render_8bpp_highres;
|
|
|
|
|
if (!svga->packed_4bpp) {
|
|
|
|
|
svga->ma_latch <<= 1;
|
|
|
|
|
svga->rowoffset <<= 1;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
2023-08-15 00:11:56 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
mach_accel_out_fifo(mach_t *mach, svga_t *svga, ibm8514_t *dev, uint16_t port, uint16_t val, int len)
|
2023-07-14 23:38:04 +02:00
|
|
|
{
|
2023-06-09 23:46:54 -04:00
|
|
|
int frgd_sel;
|
|
|
|
|
int bkgd_sel;
|
|
|
|
|
int mono_src;
|
|
|
|
|
|
2023-12-28 02:01:45 +01:00
|
|
|
mach_log("[%04X:%08X]: Port FIFO OUT=%04x, val=%04x, len=%d.\n", CS, cpu_state.pc, port, val, len);
|
|
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
switch (port) {
|
|
|
|
|
case 0x82e8:
|
|
|
|
|
case 0x86e8:
|
2024-05-29 20:47:22 +02:00
|
|
|
case 0xc2e8:
|
|
|
|
|
case 0xc6e8:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2024-05-29 20:47:22 +02:00
|
|
|
ibm8514_accel_out_fifo(svga, port, val, len);
|
|
|
|
|
break;
|
|
|
|
|
case 0xf6ee:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
|
|
|
|
if (len == 2)
|
|
|
|
|
dev->accel.cur_y = val & 0x7ff;
|
2024-05-29 20:47:22 +02:00
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
|
|
|
|
case 0x8ae8:
|
|
|
|
|
case 0xcae8:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2024-05-29 20:47:22 +02:00
|
|
|
ibm8514_accel_out_fifo(svga, port, val, len);
|
2024-10-26 21:32:47 +02:00
|
|
|
if (len == 2) {
|
|
|
|
|
mach_log("SRCY=%d.\n", val & 0x07ff);
|
|
|
|
|
mach->accel.src_y = val & 0x07ff;
|
|
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x8ee8:
|
|
|
|
|
case 0xcee8:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2024-05-29 20:47:22 +02:00
|
|
|
ibm8514_accel_out_fifo(svga, port, val, len);
|
2024-10-26 21:32:47 +02:00
|
|
|
if (len == 2) {
|
|
|
|
|
mach_log("SRCX=%d.\n", val & 0x07ff);
|
|
|
|
|
mach->accel.src_x = val & 0x07ff;
|
|
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x92e8:
|
2024-05-29 20:47:22 +02:00
|
|
|
case 0xd2e8:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2024-05-29 20:47:22 +02:00
|
|
|
ibm8514_accel_out_fifo(svga, port, val, len);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x96e8:
|
|
|
|
|
case 0xd6e8:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2024-05-29 20:47:22 +02:00
|
|
|
ibm8514_accel_out_fifo(svga, port, val, len);
|
2024-10-26 21:32:47 +02:00
|
|
|
if (len == 2)
|
2024-05-29 20:47:22 +02:00
|
|
|
mach->accel.test = val & 0x1fff;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x9ae8:
|
|
|
|
|
case 0xdae8:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2024-10-26 21:32:47 +02:00
|
|
|
mach->accel.cmd_type = -1;
|
|
|
|
|
ibm8514_accel_out_fifo(svga, port, val, len);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x9ee8:
|
|
|
|
|
case 0xdee8:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2024-10-26 21:32:47 +02:00
|
|
|
ibm8514_accel_out_fifo(svga, port, val, len);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xa2e8:
|
|
|
|
|
case 0xe2e8:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
|
|
|
|
dev->fifo_idx++;
|
2023-07-14 23:38:04 +02:00
|
|
|
if (port == 0xe2e8) {
|
2024-10-26 21:32:47 +02:00
|
|
|
if (len == 2) {
|
|
|
|
|
if (dev->accel.cmd_back) {
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->accel.bkgd_color = val;
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_log("CMDBack BKGDCOLOR, sy=%d, height=%d, val=%04x.\n", dev->accel.sy, mach->accel.height, val);
|
2023-07-14 23:38:04 +02:00
|
|
|
} else {
|
|
|
|
|
if (mach->accel.cmd_type >= 0) {
|
|
|
|
|
if (mach_pixel_read(mach))
|
|
|
|
|
break;
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_accel_out_pixtrans(svga, mach, dev, val);
|
2023-07-14 23:38:04 +02:00
|
|
|
} else {
|
|
|
|
|
if (ibm8514_cpu_dest(svga))
|
|
|
|
|
break;
|
|
|
|
|
ibm8514_accel_out_pixtrans(svga, port, val, len);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
} else {
|
2024-10-26 21:32:47 +02:00
|
|
|
if (mach->accel.cmd_type >= 0) {
|
|
|
|
|
if (mach_pixel_read(mach))
|
|
|
|
|
break;
|
|
|
|
|
mach->accel.pix_trans[1] = val;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
} else {
|
2024-10-26 21:32:47 +02:00
|
|
|
if (len == 2)
|
|
|
|
|
dev->accel.bkgd_color = val;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xa6e8:
|
|
|
|
|
case 0xe6e8:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
|
|
|
|
dev->fifo_idx++;
|
2023-07-14 23:38:04 +02:00
|
|
|
if (port == 0xe6e8) {
|
2024-10-26 21:32:47 +02:00
|
|
|
if (len == 2) {
|
2024-11-02 20:50:06 +01:00
|
|
|
if (dev->accel.cmd_back)
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->accel.frgd_color = val;
|
2024-11-02 20:50:06 +01:00
|
|
|
else {
|
2023-07-14 23:38:04 +02:00
|
|
|
if (mach->accel.cmd_type >= 0) {
|
|
|
|
|
if (mach_pixel_read(mach))
|
|
|
|
|
break;
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_accel_out_pixtrans(svga, mach, dev, val);
|
2023-07-14 23:38:04 +02:00
|
|
|
} else {
|
|
|
|
|
if (ibm8514_cpu_dest(svga))
|
|
|
|
|
break;
|
|
|
|
|
ibm8514_accel_out_pixtrans(svga, port, val, len);
|
|
|
|
|
}
|
|
|
|
|
}
|
2024-10-26 21:32:47 +02:00
|
|
|
} else {
|
|
|
|
|
if (mach->accel.cmd_type >= 0) {
|
|
|
|
|
if (mach_pixel_read(mach))
|
|
|
|
|
break;
|
|
|
|
|
mach->accel.pix_trans[1] = val;
|
|
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
} else {
|
2024-10-26 21:32:47 +02:00
|
|
|
if (len == 2)
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->accel.frgd_color = val;
|
|
|
|
|
}
|
|
|
|
|
break;
|
2024-10-26 21:32:47 +02:00
|
|
|
|
|
|
|
|
case 0xe2e9:
|
2023-07-14 23:38:04 +02:00
|
|
|
case 0xe6e9:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
|
|
|
|
dev->fifo_idx++;
|
2024-10-26 21:32:47 +02:00
|
|
|
mach_log("Write PORT=%04x, 8514/A=%x, val=%04x, len=%d.\n", port, dev->accel.cmd_back, val, len);
|
|
|
|
|
if (len == 1) {
|
|
|
|
|
if (mach->accel.cmd_type >= 0) {
|
|
|
|
|
if (mach_pixel_read(mach))
|
|
|
|
|
break;
|
|
|
|
|
mach->accel.pix_trans[0] = val;
|
|
|
|
|
frgd_sel = (mach->accel.dp_config >> 13) & 7;
|
|
|
|
|
bkgd_sel = (mach->accel.dp_config >> 7) & 3;
|
|
|
|
|
mono_src = (mach->accel.dp_config >> 5) & 3;
|
2023-06-09 23:46:54 -04:00
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
switch (mach->accel.dp_config & 0x200) {
|
|
|
|
|
case 0x000: /*8-bit size*/
|
|
|
|
|
if (mono_src == 2) {
|
|
|
|
|
if ((frgd_sel != 2) && (bkgd_sel != 2)) {
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_accel_start(mach->accel.cmd_type, 1, 8, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), 0, svga, mach, dev);
|
2024-10-26 21:32:47 +02:00
|
|
|
} else
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_accel_start(mach->accel.cmd_type, 1, 1, -1, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), svga, mach, dev);
|
2024-10-26 21:32:47 +02:00
|
|
|
} else
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_accel_start(mach->accel.cmd_type, 1, 1, -1, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), svga, mach, dev);
|
2024-10-26 21:32:47 +02:00
|
|
|
break;
|
|
|
|
|
case 0x200: /*16-bit size*/
|
|
|
|
|
if (mono_src == 2) {
|
|
|
|
|
if ((frgd_sel != 2) && (bkgd_sel != 2)) {
|
|
|
|
|
if (mach->accel.dp_config & 0x1000)
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_accel_start(mach->accel.cmd_type, 1, 16, mach->accel.pix_trans[1] | (mach->accel.pix_trans[0] << 8), 0, svga, mach, dev);
|
2024-10-26 21:32:47 +02:00
|
|
|
else
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_accel_start(mach->accel.cmd_type, 1, 16, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), 0, svga, mach, dev);
|
2024-10-26 21:32:47 +02:00
|
|
|
} else
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_accel_start(mach->accel.cmd_type, 1, 2, -1, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), svga, mach, dev);
|
2024-10-26 21:32:47 +02:00
|
|
|
} else
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_accel_start(mach->accel.cmd_type, 1, 2, -1, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), svga, mach, dev);
|
2024-10-26 21:32:47 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_log("Write Port=%04x, Busy=%02x.\n", port, dev->force_busy2);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xaae8:
|
|
|
|
|
case 0xaee8:
|
|
|
|
|
case 0xb2e8:
|
|
|
|
|
case 0xb6e8:
|
|
|
|
|
case 0xbae8:
|
2024-05-29 20:47:22 +02:00
|
|
|
case 0xeae8:
|
|
|
|
|
case 0xeee8:
|
|
|
|
|
case 0xf2e8:
|
|
|
|
|
case 0xf6e8:
|
2023-07-14 23:38:04 +02:00
|
|
|
case 0xfae8:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2024-05-29 20:47:22 +02:00
|
|
|
ibm8514_accel_out_fifo(svga, port, val, len);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xbee8:
|
|
|
|
|
case 0xfee8:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2024-10-26 21:32:47 +02:00
|
|
|
ibm8514_accel_out_fifo(svga, port, val, len);
|
|
|
|
|
if (len == 2) {
|
2023-07-14 23:38:04 +02:00
|
|
|
if ((dev->accel.multifunc_cntl >> 12) == 5) {
|
2024-01-15 21:43:33 +01:00
|
|
|
if ((dev->local & 0xff) < 0x02)
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->ext_crt_pitch = 128;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
2023-07-30 18:33:29 -04:00
|
|
|
/*ATI Mach8/32 specific registers*/
|
2023-07-14 23:38:04 +02:00
|
|
|
case 0x82ee:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2024-10-26 21:32:47 +02:00
|
|
|
mach->accel.patt_data_idx_reg = val & 0x1f;
|
|
|
|
|
mach->accel.patt_data_idx = mach->accel.patt_data_idx_reg;
|
|
|
|
|
|
|
|
|
|
if (mach->accel.patt_data_idx_reg < 0x10)
|
|
|
|
|
mach->accel.color_pattern_idx = mach->accel.patt_idx;
|
|
|
|
|
else
|
|
|
|
|
mach->accel.color_pattern_idx = 0;
|
|
|
|
|
|
|
|
|
|
mach_log("Write Port 82ee: Pattern Data Index=%d.\n", val & 0x1f);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x8eee:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2024-10-26 21:32:47 +02:00
|
|
|
if (len == 2) {
|
|
|
|
|
if (mach->accel.patt_data_idx_reg < 0x10) {
|
|
|
|
|
mach->accel.color_pattern[mach->accel.patt_data_idx] = val & 0xff;
|
|
|
|
|
mach->accel.color_pattern[mach->accel.patt_data_idx + 1] = (val >> 8) & 0xff;
|
|
|
|
|
mach_log("Write Port 8eee: Color Pattern Word Data[%d]=%04x.\n", mach->accel.patt_data_idx, val);
|
|
|
|
|
} else {
|
|
|
|
|
mach->accel.mono_pattern_normal[mach->accel.patt_data_idx - 0x10] = val & 0xff;
|
|
|
|
|
mach->accel.mono_pattern_normal[(mach->accel.patt_data_idx + 1) - 0x10] = (val >> 8) & 0xff;
|
|
|
|
|
mach_log("Write Port 8eee: Mono Pattern Word Data[%d]=%04x.\n", mach->accel.patt_data_idx - 0x10, val);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
2024-10-26 21:32:47 +02:00
|
|
|
mach->accel.patt_data_idx += 2;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x96ee:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2024-10-26 21:32:47 +02:00
|
|
|
if (len == 2) {
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.bres_count = val & 0x7ff;
|
2024-10-26 21:32:47 +02:00
|
|
|
mach_log("BresenhamDraw=%04x.\n", mach->accel.dp_config);
|
2024-11-02 20:50:06 +01:00
|
|
|
dev->data_available = 0;
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->data_available2 = 0;
|
|
|
|
|
mach->accel.cmd_type = 1;
|
2024-11-02 20:50:06 +01:00
|
|
|
frgd_sel = (mach->accel.dp_config >> 13) & 7;
|
|
|
|
|
bkgd_sel = (mach->accel.dp_config >> 7) & 3;
|
|
|
|
|
mono_src = (mach->accel.dp_config >> 5) & 3;
|
|
|
|
|
|
|
|
|
|
dev->accel.cmd_back = 1;
|
|
|
|
|
if ((mono_src == 2) || (bkgd_sel == 2) || (frgd_sel == 2) || mach_pixel_read(mach))
|
|
|
|
|
dev->accel.cmd_back = 0;
|
|
|
|
|
|
|
|
|
|
mach_accel_start(mach->accel.cmd_type, 0, -1, -1, 0, svga, mach, dev);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x9aee:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.line_idx = val & 0x07;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xa2ee:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2024-10-26 21:32:47 +02:00
|
|
|
mach_log("Line OPT=%04x.\n", val);
|
|
|
|
|
if (len == 2) {
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.linedraw_opt = val;
|
2024-11-02 20:50:06 +01:00
|
|
|
mach->accel.bbottom = dev->accel.clip_bottom;
|
|
|
|
|
mach->accel.btop = dev->accel.clip_top;
|
|
|
|
|
mach->accel.bleft = dev->accel.clip_left;
|
|
|
|
|
mach->accel.bright = dev->accel.clip_right;
|
2024-01-05 21:22:01 +01:00
|
|
|
if (mach->accel.linedraw_opt & 0x100) {
|
|
|
|
|
mach->accel.bbottom = 2047;
|
|
|
|
|
mach->accel.btop = 0;
|
|
|
|
|
mach->accel.bleft = 0;
|
|
|
|
|
mach->accel.bright = 2047;
|
|
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xa6ee:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2024-10-26 21:32:47 +02:00
|
|
|
if (len == 2)
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.dest_x_start = val & 0x7ff;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xaaee:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2024-10-26 21:32:47 +02:00
|
|
|
if (len == 2)
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.dest_x_end = val & 0x7ff;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xaeee:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2024-10-26 21:32:47 +02:00
|
|
|
if (len == 2) {
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.dest_y_end = val & 0x7ff;
|
|
|
|
|
if ((val + 1) == 0x10000) {
|
2024-10-26 21:32:47 +02:00
|
|
|
mach_log("Dest_Y_end overflow val=%04x, DPCONFIG=%04x\n", val, mach->accel.dp_config);
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.dest_y_end = 0;
|
|
|
|
|
}
|
|
|
|
|
dev->data_available = 0;
|
|
|
|
|
dev->data_available2 = 0;
|
2024-10-26 21:32:47 +02:00
|
|
|
mach_log("BitBLT=%04x.\n", mach->accel.dp_config);
|
|
|
|
|
mach_log(".\n");
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.cmd_type = 2; /*Non-conforming BitBLT from dest_y_end register (0xaeee)*/
|
2024-11-02 20:50:06 +01:00
|
|
|
|
|
|
|
|
frgd_sel = (mach->accel.dp_config >> 13) & 7;
|
|
|
|
|
bkgd_sel = (mach->accel.dp_config >> 7) & 3;
|
|
|
|
|
mono_src = (mach->accel.dp_config >> 5) & 3;
|
|
|
|
|
|
|
|
|
|
dev->accel.cmd_back = 1;
|
|
|
|
|
if ((mono_src == 2) || (bkgd_sel == 2) || (frgd_sel == 2) || mach_pixel_read(mach))
|
|
|
|
|
dev->accel.cmd_back = 0;
|
|
|
|
|
|
|
|
|
|
mach_accel_start(mach->accel.cmd_type, 0, -1, -1, 0, svga, mach, dev);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xb2ee:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2024-10-26 21:32:47 +02:00
|
|
|
if (len == 2)
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.src_x_start = val & 0x7ff;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xb6ee:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
|
|
|
|
dev->accel.bkgd_mix = val & 0xff;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xbaee:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
|
|
|
|
dev->accel.frgd_mix = val & 0xff;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xbeee:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2024-10-26 21:32:47 +02:00
|
|
|
if (len == 2)
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.src_x_end = val & 0x7ff;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xc2ee:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.src_y_dir = val & 1;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xc6ee:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2024-11-02 20:50:06 +01:00
|
|
|
if (len == 2) {
|
|
|
|
|
mach->accel.cmd_type = 0;
|
|
|
|
|
mach_log("TODO: Short Stroke.\n");
|
|
|
|
|
frgd_sel = (mach->accel.dp_config >> 13) & 7;
|
|
|
|
|
bkgd_sel = (mach->accel.dp_config >> 7) & 3;
|
|
|
|
|
mono_src = (mach->accel.dp_config >> 5) & 3;
|
|
|
|
|
|
|
|
|
|
dev->accel.cmd_back = 1;
|
|
|
|
|
if ((mono_src == 2) || (bkgd_sel == 2) || (frgd_sel == 2) || mach_pixel_read(mach))
|
|
|
|
|
dev->accel.cmd_back = 0;
|
|
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xcaee:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2024-10-26 21:32:47 +02:00
|
|
|
if (len == 2) {
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.scan_to_x = (val & 0x7ff);
|
|
|
|
|
if ((val + 1) == 0x10000) {
|
|
|
|
|
mach_log("Scan_to_X overflow val = %04x\n", val);
|
|
|
|
|
mach->accel.scan_to_x = 0;
|
|
|
|
|
}
|
|
|
|
|
dev->data_available = 0;
|
|
|
|
|
dev->data_available2 = 0;
|
|
|
|
|
mach->accel.cmd_type = 5; /*Horizontal Raster Draw from scan_to_x register (0xcaee)*/
|
2024-10-26 21:32:47 +02:00
|
|
|
mach_log("ScanToX=%04x.\n", mach->accel.dp_config);
|
|
|
|
|
mach_log(".\n");
|
2024-11-02 20:50:06 +01:00
|
|
|
|
|
|
|
|
frgd_sel = (mach->accel.dp_config >> 13) & 7;
|
|
|
|
|
bkgd_sel = (mach->accel.dp_config >> 7) & 3;
|
|
|
|
|
mono_src = (mach->accel.dp_config >> 5) & 3;
|
|
|
|
|
|
|
|
|
|
dev->accel.cmd_back = 1;
|
|
|
|
|
if ((mono_src == 2) || (bkgd_sel == 2) || (frgd_sel == 2) || mach_pixel_read(mach))
|
|
|
|
|
dev->accel.cmd_back = 0;
|
|
|
|
|
|
|
|
|
|
mach_accel_start(mach->accel.cmd_type, 0, -1, -1, 0, svga, mach, dev);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xceee:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2023-07-14 23:38:04 +02:00
|
|
|
mach_log("CEEE write val = %04x.\n", val);
|
2024-10-26 21:32:47 +02:00
|
|
|
if (len == 2) {
|
2023-12-28 02:01:45 +01:00
|
|
|
dev->data_available = 0;
|
|
|
|
|
dev->data_available2 = 0;
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.dp_config = val;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xd2ee:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.patt_len = val & 0x1f;
|
2024-10-26 21:32:47 +02:00
|
|
|
mach_log("Write Port d2ee: Pattern Length=%d, val=%04x.\n", val & 0x1f, val);
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.mono_pattern_enable = !!(val & 0x80);
|
2024-10-26 21:32:47 +02:00
|
|
|
if (len == 2) {
|
|
|
|
|
mach->accel.block_write_mono_pattern_enable = !!(val & 0x8000);
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.patt_len_reg = val;
|
2024-10-26 21:32:47 +02:00
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xd6ee:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.patt_idx = val & 0x1f;
|
2024-10-26 21:32:47 +02:00
|
|
|
mach_log("Write Port d6ee: Pattern Index=%d.\n", val & 0x1f);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xdaee:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2024-10-27 23:36:11 +01:00
|
|
|
if (len == 2) {
|
2024-10-26 21:32:47 +02:00
|
|
|
dev->accel.multifunc[2] = val & 0x7ff;
|
2024-10-27 23:36:11 +01:00
|
|
|
dev->accel.clip_left = dev->accel.multifunc[2];
|
|
|
|
|
if (val & 0x800)
|
|
|
|
|
dev->accel.clip_left |= ~0x7ff;
|
|
|
|
|
}
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_log("DAEE (extclipl) write val=%d, left=%d.\n", val, dev->accel.clip_left);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xdeee:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2024-10-27 23:36:11 +01:00
|
|
|
if (len == 2) {
|
2024-10-26 21:32:47 +02:00
|
|
|
dev->accel.multifunc[1] = val & 0x7ff;
|
2024-10-27 23:36:11 +01:00
|
|
|
dev->accel.clip_top = dev->accel.multifunc[1];
|
2024-11-02 20:50:06 +01:00
|
|
|
if (val & 0x800) {
|
2024-10-27 23:36:11 +01:00
|
|
|
dev->accel.clip_top |= ~0x7ff;
|
2024-11-02 20:50:06 +01:00
|
|
|
}
|
2024-10-27 23:36:11 +01:00
|
|
|
}
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_log("DEEE (extclipt) write val = %d\n", val);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xe2ee:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2024-10-27 23:36:11 +01:00
|
|
|
if (len == 2) {
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->accel.multifunc[4] = val & 0x7ff;
|
2024-10-27 23:36:11 +01:00
|
|
|
dev->accel.clip_right = dev->accel.multifunc[4];
|
|
|
|
|
if (val & 0x800)
|
|
|
|
|
dev->accel.clip_right |= ~0x7ff;
|
|
|
|
|
}
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_log("E2EE (extclipr) write val = %d\n", val);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xe6ee:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2024-10-27 23:36:11 +01:00
|
|
|
if (len == 2) {
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->accel.multifunc[3] = val & 0x7ff;
|
2024-10-27 23:36:11 +01:00
|
|
|
dev->accel.clip_bottom = dev->accel.multifunc[3];
|
|
|
|
|
if (val & 0x800)
|
|
|
|
|
dev->accel.clip_bottom |= ~0x7ff;
|
|
|
|
|
}
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_log("E6EE (extclipb) write val = %d\n", val);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xeeee:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2024-10-26 21:32:47 +02:00
|
|
|
if (len == 2)
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.dest_cmp_fn = val;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xf2ee:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2023-07-14 23:38:04 +02:00
|
|
|
mach_log("F2EE.\n");
|
2024-10-26 21:32:47 +02:00
|
|
|
if (len == 2)
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.dst_clr_cmp_mask = val;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xfeee:
|
2024-11-13 22:55:16 +01:00
|
|
|
dev->ext_fifo_idx++;
|
2024-10-26 21:32:47 +02:00
|
|
|
mach_log("LineDraw=%04x.\n", mach->accel.dp_config);
|
|
|
|
|
if (len == 2) {
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.line_array[mach->accel.line_idx] = val;
|
2023-07-30 18:33:29 -04:00
|
|
|
dev->accel.cur_x = mach->accel.line_array[(mach->accel.line_idx == 4) ? 4 : 0];
|
|
|
|
|
dev->accel.cur_y = mach->accel.line_array[(mach->accel.line_idx == 5) ? 5 : 1];
|
|
|
|
|
mach->accel.cx_end_line = mach->accel.line_array[2];
|
|
|
|
|
mach->accel.cy_end_line = mach->accel.line_array[3];
|
2023-07-14 23:38:04 +02:00
|
|
|
if ((mach->accel.line_idx == 3) || (mach->accel.line_idx == 5)) {
|
|
|
|
|
mach->accel.cmd_type = (mach->accel.line_idx == 5) ? 4 : 3;
|
2024-11-02 20:50:06 +01:00
|
|
|
frgd_sel = (mach->accel.dp_config >> 13) & 7;
|
|
|
|
|
bkgd_sel = (mach->accel.dp_config >> 7) & 3;
|
|
|
|
|
mono_src = (mach->accel.dp_config >> 5) & 3;
|
|
|
|
|
|
|
|
|
|
dev->accel.cmd_back = 1;
|
|
|
|
|
if ((mono_src == 2) || (bkgd_sel == 2) || (frgd_sel == 2) || mach_pixel_read(mach))
|
|
|
|
|
dev->accel.cmd_back = 0;
|
|
|
|
|
|
|
|
|
|
mach_accel_start(mach->accel.cmd_type, 0, -1, -1, 0, svga, mach, dev);
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->accel.line_idx = (mach->accel.line_idx == 5) ? 4 : 2;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
mach->accel.line_idx++;
|
|
|
|
|
}
|
|
|
|
|
break;
|
2023-06-09 23:46:54 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2024-01-15 21:43:33 +01:00
|
|
|
mach_accel_out_call(uint16_t port, uint8_t val, mach_t *mach, svga_t *svga, ibm8514_t *dev)
|
2023-07-14 23:38:04 +02:00
|
|
|
{
|
2024-10-26 21:32:47 +02:00
|
|
|
if (port != 0x42e8 && port != 0x42e9)
|
2024-01-15 21:43:33 +01:00
|
|
|
mach_log("[%04X:%08X]: Port CALL OUT=%04x, val=%02x.\n", CS, cpu_state.pc, port, val);
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
switch (port) {
|
|
|
|
|
case 0x2e8:
|
2024-04-26 19:28:03 +02:00
|
|
|
case 0x6e9:
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0xae8:
|
|
|
|
|
case 0xee8:
|
2024-05-29 20:47:22 +02:00
|
|
|
case 0x1ee8:
|
|
|
|
|
case 0x1ee9:
|
|
|
|
|
case 0x42e8:
|
2024-11-13 22:55:16 +01:00
|
|
|
ibm8514_accel_out(port, val, svga, 2);
|
|
|
|
|
break;
|
2024-05-29 20:47:22 +02:00
|
|
|
case 0x42e9:
|
|
|
|
|
ibm8514_accel_out(port, val, svga, 2);
|
2024-11-13 22:55:16 +01:00
|
|
|
if ((val & 0xc0) == 0xc0) {
|
|
|
|
|
dev->ext_fifo_idx = 0;
|
|
|
|
|
mach->force_busy = 0;
|
|
|
|
|
}
|
2024-05-29 20:47:22 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x6e8:
|
2024-04-20 23:43:27 +02:00
|
|
|
/*In preparation to switch from VGA to 8514/A mode*/
|
2024-10-26 21:32:47 +02:00
|
|
|
if (!(mach->shadow_cntl & 0x08)) {
|
|
|
|
|
if ((mach->shadow_set & 0x03) || (mach->accel.clock_sel & 0x01)) {
|
|
|
|
|
dev->hdisped = val;
|
2024-10-27 23:36:11 +01:00
|
|
|
dev->hdisp = (val + 1) << 3;
|
|
|
|
|
} else if (((mach->shadow_set & 0x03) == 0x00) && !(mach->accel.clock_sel & 0x01))
|
|
|
|
|
dev->hdisp2 = (val + 1) << 3;
|
2024-10-26 21:32:47 +02:00
|
|
|
}
|
2025-02-01 03:29:03 -05:00
|
|
|
mach_log("[%04X:%08X]: ATI 8514/A: (0x%04x): hdisp=0x%02x, shadowcntl=%02x, shadowset=%02x.\n",
|
|
|
|
|
CS, cpu_state.pc, port, val, mach->shadow_cntl & 0x08, mach->shadow_set & 0x03);
|
2024-10-26 21:32:47 +02:00
|
|
|
svga_recalctimings(svga);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x12e8:
|
|
|
|
|
case 0x12e9:
|
|
|
|
|
/*In preparation to switch from VGA to 8514/A mode*/
|
|
|
|
|
if (!(mach->shadow_cntl & 0x10)) {
|
2024-10-27 23:36:11 +01:00
|
|
|
if ((mach->shadow_set & 0x03) || (mach->accel.clock_sel & 0x01) ||
|
|
|
|
|
(((mach->shadow_set & 0x03) == 0x00) && !(mach->accel.clock_sel & 0x01))) {
|
2024-10-26 21:32:47 +02:00
|
|
|
WRITE8(port, dev->v_total_reg, val);
|
|
|
|
|
dev->v_total_reg &= 0x1fff;
|
|
|
|
|
dev->v_total = dev->v_total_reg + 1;
|
|
|
|
|
if (dev->interlace)
|
|
|
|
|
dev->v_total >>= 1;
|
|
|
|
|
}
|
2024-01-26 19:03:43 +01:00
|
|
|
}
|
2024-05-29 20:47:22 +02:00
|
|
|
mach_log("[%04X:%08X]: ATI 8514/A: (0x%04x): hdisp=0x%02x.\n", CS, cpu_state.pc, port, val);
|
2024-04-26 19:28:03 +02:00
|
|
|
svga_recalctimings(svga);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x16e8:
|
|
|
|
|
case 0x16e9:
|
2024-04-20 23:43:27 +02:00
|
|
|
/*In preparation to switch from VGA to 8514/A mode*/
|
2024-10-26 21:32:47 +02:00
|
|
|
if (!(mach->shadow_cntl & 0x20)) {
|
|
|
|
|
if ((mach->shadow_set & 0x03) || (mach->accel.clock_sel & 0x01)) {
|
|
|
|
|
WRITE8(port, dev->v_disp, val);
|
|
|
|
|
dev->v_disp &= 0x1fff;
|
|
|
|
|
dev->vdisp = (dev->v_disp + 1) >> 1;
|
2024-10-27 23:36:11 +01:00
|
|
|
if ((dev->vdisp == 478) || (dev->vdisp == 598) || (dev->vdisp == 766) || (dev->vdisp == 1022))
|
|
|
|
|
dev->vdisp += 2;
|
|
|
|
|
} else if (((mach->shadow_set & 0x03) == 0x00) && !(mach->accel.clock_sel & 0x01)) {
|
|
|
|
|
WRITE8(port, dev->v_disp2, val);
|
|
|
|
|
dev->v_disp2 &= 0x1fff;
|
|
|
|
|
dev->vdisp2 = (dev->v_disp2 + 1) >> 1;
|
|
|
|
|
if ((dev->vdisp2 == 478) || (dev->vdisp2 == 598) || (dev->vdisp2 == 766) || (dev->vdisp2 == 1022))
|
|
|
|
|
dev->vdisp2 += 2;
|
2024-10-26 21:32:47 +02:00
|
|
|
}
|
2023-12-22 19:43:51 +01:00
|
|
|
}
|
2024-10-27 23:36:11 +01:00
|
|
|
mach_log("ATI 8514/A: V_DISP write 16E8=%d, vdisp2=%d.\n", dev->v_disp, dev->v_disp2);
|
2024-04-20 23:43:27 +02:00
|
|
|
mach_log("ATI 8514/A: (0x%04x): vdisp=0x%02x.\n", port, val);
|
2024-04-26 19:28:03 +02:00
|
|
|
svga_recalctimings(svga);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
case 0x1ae8:
|
|
|
|
|
case 0x1ae9:
|
|
|
|
|
/*In preparation to switch from VGA to 8514/A mode*/
|
|
|
|
|
if (!(mach->shadow_cntl & 0x10)) {
|
2024-10-27 23:36:11 +01:00
|
|
|
if ((mach->shadow_set & 0x03) || (mach->accel.clock_sel & 0x01) ||
|
|
|
|
|
(((mach->shadow_set & 0x03) == 0x00) && !(mach->accel.clock_sel & 0x01))) {
|
2024-10-26 21:32:47 +02:00
|
|
|
WRITE8(port, dev->v_sync_start, val);
|
|
|
|
|
dev->v_sync_start &= 0x1fff;
|
|
|
|
|
dev->v_syncstart = dev->v_sync_start + 1;
|
|
|
|
|
if (dev->interlace)
|
|
|
|
|
dev->v_syncstart >>= 1;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
mach_log("ATI 8514/A: V_SYNCSTART write 1AE8 = %d\n", dev->v_syncstart);
|
|
|
|
|
mach_log("ATI 8514/A: (0x%04x): vsyncstart=0x%02x.\n", port, val);
|
|
|
|
|
svga_recalctimings(svga);
|
|
|
|
|
break;
|
|
|
|
|
|
2024-10-27 23:36:11 +01:00
|
|
|
case 0x22e8:
|
|
|
|
|
if (!(mach->shadow_cntl & 0x03)) {
|
|
|
|
|
if ((mach->shadow_set & 0x03) || (mach->accel.clock_sel & 0x01) ||
|
|
|
|
|
(((mach->shadow_set & 0x03) == 0x00) && !(mach->accel.clock_sel & 0x01))) {
|
|
|
|
|
dev->disp_cntl = val;
|
|
|
|
|
dev->interlace = !!(dev->disp_cntl & 0x10);
|
|
|
|
|
}
|
|
|
|
|
}
|
2025-02-01 03:29:03 -05:00
|
|
|
mach_log("ATI 8514/A: DISP_CNTL write %04x=%02x, written=%02x, interlace=%d.\n",
|
|
|
|
|
port, val & 0x70, dev->disp_cntl & 0x70, dev->interlace);
|
2024-10-27 23:36:11 +01:00
|
|
|
svga_recalctimings(svga);
|
|
|
|
|
break;
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x4ae8:
|
2024-10-27 23:36:11 +01:00
|
|
|
dev->accel.advfunc_cntl = val;
|
2024-11-03 04:46:32 +01:00
|
|
|
dev->on = dev->accel.advfunc_cntl & 0x01;
|
2024-11-03 23:21:18 +01:00
|
|
|
dev->vendor_mode = 0;
|
2025-02-01 03:29:03 -05:00
|
|
|
mach_log("[%04X:%08X]: ATI 8514/A: (0x%04x): ON=%d, shadow crt=%x, hdisp=%d, vdisp=%d.\n",
|
|
|
|
|
CS, cpu_state.pc, port, val & 0x01, dev->accel.advfunc_cntl & 0x04, dev->hdisp, dev->vdisp);
|
2024-10-26 21:32:47 +02:00
|
|
|
|
2024-11-02 20:50:06 +01:00
|
|
|
if ((dev->local & 0xff) < 0x02) {
|
2023-11-08 23:47:16 +01:00
|
|
|
dev->ext_crt_pitch = 128;
|
2024-11-02 20:50:06 +01:00
|
|
|
svga_recalctimings(svga);
|
|
|
|
|
} else {
|
|
|
|
|
svga_recalctimings(svga);
|
|
|
|
|
mach32_updatemapping(mach, svga);
|
|
|
|
|
}
|
2024-10-26 21:32:47 +02:00
|
|
|
mach_log("Vendor IBM mode set %s resolution.\n", (dev->accel.advfunc_cntl & 0x04) ? "2: 1024x768" : "1: 640x480");
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
/*ATI Mach8/32 specific registers*/
|
|
|
|
|
case 0x2ee:
|
|
|
|
|
mach_log("2EE write val = %02x.\n", val);
|
|
|
|
|
break;
|
|
|
|
|
case 0x2ef:
|
|
|
|
|
mach_log("2EF write val = %02x.\n", val);
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x6ee:
|
|
|
|
|
mach_log("6EE write val = %02x.\n", val);
|
|
|
|
|
break;
|
|
|
|
|
case 0x6ef:
|
|
|
|
|
mach_log("6EF write val = %02x.\n", val);
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0xaee:
|
|
|
|
|
case 0xaef:
|
2023-12-14 21:47:10 +01:00
|
|
|
WRITE8(port, mach->cursor_offset_lo_reg, val);
|
|
|
|
|
mach->cursor_offset_lo = mach->cursor_offset_lo_reg;
|
2024-09-22 21:05:10 +02:00
|
|
|
dev->hwcursor.addr = ((mach->cursor_offset_lo | (mach->cursor_offset_hi << 16)) << 2);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0xeee:
|
|
|
|
|
case 0xeef:
|
|
|
|
|
WRITE8(port, mach->cursor_offset_hi_reg, val);
|
|
|
|
|
mach->cursor_offset_hi = mach->cursor_offset_hi_reg & 0x0f;
|
2024-09-22 21:05:10 +02:00
|
|
|
dev->hwcursor.addr = ((mach->cursor_offset_lo | (mach->cursor_offset_hi << 16)) << 2);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
dev->hwcursor.ena = !!(mach->cursor_offset_hi_reg & 0x8000);
|
2024-10-26 21:32:47 +02:00
|
|
|
mach_log("HWCursorEnabled=%x.\n", dev->hwcursor.ena);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x12ee:
|
|
|
|
|
case 0x12ef:
|
|
|
|
|
WRITE8(port, mach->cursor_x, val);
|
|
|
|
|
dev->hwcursor.x = mach->cursor_x & 0x7ff;
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x16ee:
|
|
|
|
|
case 0x16ef:
|
|
|
|
|
WRITE8(port, mach->cursor_y, val);
|
|
|
|
|
dev->hwcursor.y = mach->cursor_y & 0xfff;
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x1aee:
|
|
|
|
|
case 0x1aef:
|
|
|
|
|
WRITE8(port, mach->cursor_col_b, val);
|
|
|
|
|
mach->cursor_col_0 = mach->cursor_col_b & 0xff;
|
|
|
|
|
mach->cursor_col_1 = (mach->cursor_col_b >> 8) & 0xff;
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x1eee:
|
|
|
|
|
case 0x1eef:
|
|
|
|
|
WRITE8(port, mach->cursor_vh_offset, val);
|
|
|
|
|
dev->hwcursor.xoff = mach->cursor_vh_offset & 0x3f;
|
|
|
|
|
dev->hwcursor.yoff = (mach->cursor_vh_offset >> 8) & 0x3f;
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x22ee:
|
|
|
|
|
if (mach->pci_bus) {
|
|
|
|
|
mach->pci_cntl_reg = val;
|
2024-11-05 01:08:13 +01:00
|
|
|
mach_log("PCI Control Reg=%02x.\n", val);
|
2024-01-15 21:43:33 +01:00
|
|
|
mach32_updatemapping(mach, svga);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
}
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x26ee:
|
2023-08-15 00:11:56 +02:00
|
|
|
case 0x26ef:
|
|
|
|
|
WRITE8(port, mach->accel.crt_pitch, val);
|
|
|
|
|
dev->ext_crt_pitch = mach->accel.crt_pitch & 0xff;
|
|
|
|
|
if (dev->accel_bpp > 8) {
|
|
|
|
|
if (dev->accel_bpp == 24)
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
dev->ext_crt_pitch *= 3;
|
2023-08-15 00:11:56 +02:00
|
|
|
else if (dev->accel_bpp == 32)
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
dev->ext_crt_pitch <<= 2;
|
2023-07-14 23:38:04 +02:00
|
|
|
else
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
dev->ext_crt_pitch <<= 1;
|
|
|
|
|
}
|
2024-11-13 22:55:16 +01:00
|
|
|
if ((dev->local & 0xff) >= 0x02) {
|
|
|
|
|
dev->on |= 0x01;
|
|
|
|
|
dev->vendor_mode = 1;
|
|
|
|
|
}
|
2024-11-03 04:46:32 +01:00
|
|
|
svga_recalctimings(svga);
|
2025-01-16 22:37:52 +01:00
|
|
|
if ((dev->local & 0xff) >= 0x01)
|
|
|
|
|
mach32_updatemapping(mach, svga);
|
|
|
|
|
|
2024-11-13 22:55:16 +01:00
|
|
|
mach_log("ATI 8514/A: (0x%04x) val=0x%02x, extended 8514/A mode=%02x.\n", port, val, mach->regs[0xb0] & 0x20);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x32ee:
|
|
|
|
|
case 0x32ef:
|
|
|
|
|
WRITE8(port, mach->local_cntl, val);
|
2025-01-16 22:37:52 +01:00
|
|
|
if ((dev->local & 0xff) >= 0x01)
|
|
|
|
|
mach32_updatemapping(mach, svga);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x36ee:
|
|
|
|
|
case 0x36ef:
|
Video, Storage and MCA changes/fixes.
1. Cirrus Logic GD54xx, Paradise/WD VGA now reset the interlace once a text mode is issued if not done automatically.
2. Paradise/WD's 15/16bpp modes using the 800x600 resolution now have the correct ma_latch, should fix most operating systems drivers using this combo.
3. More fixes (hopefully) to the accelerated pitch and rowoffset of the Trident TGUI cards (9440AGi and 96x0XGi), should fix issues with delayed displays mode changes under various operating systems (e.g.: Win3.1x).
4. Preliminary implementation of the Area Fill command of XGA, which is issued while using various painting and/or calc utilities on Win3.1x (IBM XGA updated drivers, e.g.: 2.12).
5. Preliminary (and incomplete) 4bpp XGA mode.
6. The XGA memory test for the 0xa5 using writes (used by various operating systems) no longer conflicts with DOS' XGAKIT's memory detection.
7. Small ROP fixes to both XGA and 8514/A.
8. Re-organized the mapping of the Mach32 chipset, especially when to enable the ATI mode or switching back to IBM mode, should fix LFB conflicts with various operating systems.
9. According to The OS/2 Museum, the Adaptec AHA-154xB series of SCSI cards fail the ASPI4DOS.SYS 3.36 signature check, so now make the changes accordingly.
10. Remove useless and crashy bios-less option of the Trantor T128.
11. The Image Manager 1024 card can also be used on a XT (although only if it has a V20/V30).
12. Re-organized the IBM PS/2 model 60 initialization as well as its right POS machine ID (though an update to sc.exe is still required for the POST memory amount to work normally).
2023-09-30 22:08:08 +02:00
|
|
|
mach_log("ATI 8514/A: (0x%04x) val = %04x.\n", port, val);
|
2024-11-13 22:55:16 +01:00
|
|
|
if ((dev->local & 0xff) >= 0x02) {
|
|
|
|
|
WRITE8(port, mach->misc, val);
|
|
|
|
|
mach->misc &= 0xfff0;
|
|
|
|
|
}
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x3aee:
|
|
|
|
|
case 0x3aef:
|
|
|
|
|
WRITE8(port, mach->cursor_col_0_rg, val);
|
|
|
|
|
mach->ext_cur_col_0_g = mach->cursor_col_0_rg & 0xff;
|
|
|
|
|
mach->ext_cur_col_0_r = (mach->cursor_col_0_rg >> 8) & 0xff;
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x3eee:
|
|
|
|
|
case 0x3eef:
|
|
|
|
|
WRITE8(port, mach->cursor_col_1_rg, val);
|
|
|
|
|
mach->ext_cur_col_1_g = mach->cursor_col_1_rg & 0xff;
|
|
|
|
|
mach->ext_cur_col_1_r = (mach->cursor_col_1_rg >> 8) & 0xff;
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x42ee:
|
|
|
|
|
case 0x42ef:
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_log("ATI 8514/A: (0x%04x) val=%04x.\n", port, val);
|
2023-12-28 02:01:45 +01:00
|
|
|
WRITE8(port, mach->accel.test2, val);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x46ee:
|
|
|
|
|
case 0x46ef:
|
2024-01-15 21:43:33 +01:00
|
|
|
WRITE8(port, mach->shadow_cntl, val);
|
2024-05-29 20:47:22 +02:00
|
|
|
mach_log("ATI 8514/A: (0x%04x) val=%02x.\n", port, val);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x4aee:
|
|
|
|
|
case 0x4aef:
|
|
|
|
|
WRITE8(port, mach->accel.clock_sel, val);
|
2024-11-03 04:46:32 +01:00
|
|
|
dev->on = mach->accel.clock_sel & 0x01;
|
2024-11-03 23:21:18 +01:00
|
|
|
dev->vendor_mode = 1;
|
2025-02-01 03:29:03 -05:00
|
|
|
mach_log("ATI 8514/A: (0x%04x): ON=%d, val=%04x, hdisp=%d, vdisp=%d.\n",
|
|
|
|
|
port, mach->accel.clock_sel & 0x01, val, dev->hdisp, dev->vdisp);
|
|
|
|
|
mach_log("Vendor ATI mode set %s resolution.\n",
|
|
|
|
|
(dev->accel.advfunc_cntl & 0x04) ? "2: 1024x768" : "1: 640x480");
|
2024-11-03 04:46:32 +01:00
|
|
|
svga_recalctimings(svga);
|
2025-01-16 22:37:52 +01:00
|
|
|
if ((dev->local & 0xff) >= 0x01)
|
|
|
|
|
mach32_updatemapping(mach, svga);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x52ee:
|
|
|
|
|
case 0x52ef:
|
2024-04-20 23:43:27 +02:00
|
|
|
mach_log("ATI 8514/A: (0x%04x) val=%04x.\n", port, val);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
WRITE8(port, mach->accel.scratch0, val);
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x56ee:
|
|
|
|
|
case 0x56ef:
|
2024-04-20 23:43:27 +02:00
|
|
|
mach_log("ATI 8514/A: (0x%04x) val=%04x.\n", port, val);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
WRITE8(port, mach->accel.scratch1, val);
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x5aee:
|
|
|
|
|
case 0x5aef:
|
2024-04-20 23:43:27 +02:00
|
|
|
WRITE8(port, mach->shadow_set, val);
|
2024-05-29 20:47:22 +02:00
|
|
|
mach_log("ATI 8514/A: (0x%04x) val=0x%02x.\n", port, val);
|
2024-04-20 23:43:27 +02:00
|
|
|
if ((mach->shadow_set & 0x03) == 0x00)
|
|
|
|
|
mach_log("Primary CRT register set.\n");
|
|
|
|
|
else if ((mach->shadow_set & 0x03) == 0x01)
|
2024-05-29 20:47:22 +02:00
|
|
|
mach_log("CRT Shadow Set 1: 640x480.\n");
|
2024-04-20 23:43:27 +02:00
|
|
|
else if ((mach->shadow_set & 0x03) == 0x02)
|
2024-05-29 20:47:22 +02:00
|
|
|
mach_log("CRT Shadow Set 2: 1024x768.\n");
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x5eee:
|
|
|
|
|
case 0x5eef:
|
|
|
|
|
WRITE8(port, mach->memory_aperture, val);
|
|
|
|
|
mach_log("Memory Aperture = %04x.\n", mach->memory_aperture);
|
|
|
|
|
if (!mach->pci_bus)
|
|
|
|
|
mach->linear_base = (mach->memory_aperture & 0xff00) << 12;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
2025-01-16 22:37:52 +01:00
|
|
|
if ((dev->local & 0xff) >= 0x01)
|
|
|
|
|
mach32_updatemapping(mach, svga);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x62ee:
|
|
|
|
|
mach_log("62EE write val = %04x, len = %d.\n", val, len);
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x66ee:
|
|
|
|
|
mach_log("66EE write val = %04x, len = %d.\n", val, len);
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x6aee:
|
|
|
|
|
case 0x6aef:
|
|
|
|
|
WRITE8(port, mach->accel.max_waitstates, val);
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x6eee:
|
|
|
|
|
case 0x6eef:
|
|
|
|
|
WRITE8(port, mach->accel.ge_offset_lo, val);
|
2024-05-29 20:47:22 +02:00
|
|
|
svga_recalctimings(svga);
|
2024-10-26 21:32:47 +02:00
|
|
|
mach_log("ATI 8514/A: (0x%04x) val=0x%02x, geoffset=%04x.\n", port, val, dev->accel.ge_offset);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x72ee:
|
|
|
|
|
case 0x72ef:
|
|
|
|
|
WRITE8(port, mach->accel.ge_offset_hi, val);
|
2024-05-29 20:47:22 +02:00
|
|
|
svga_recalctimings(svga);
|
2024-10-26 21:32:47 +02:00
|
|
|
mach_log("ATI 8514/A: (0x%04x) val=0x%02x, geoffset=%04x.\n", port, val, dev->accel.ge_offset);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
break;
|
2023-06-09 23:46:54 -04:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x76ee:
|
2023-08-15 00:11:56 +02:00
|
|
|
case 0x76ef:
|
|
|
|
|
WRITE8(port, mach->accel.ge_pitch, val);
|
2023-08-15 22:47:29 +02:00
|
|
|
dev->ext_pitch = ((mach->accel.ge_pitch & 0xff) << 3);
|
2024-05-29 20:47:22 +02:00
|
|
|
mach_log("ATI 8514/A: (0x%04x) val=0x%02x, extpitch=%d.\n", port, val, dev->ext_pitch);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
svga_recalctimings(svga);
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x7aee:
|
|
|
|
|
case 0x7aef:
|
|
|
|
|
WRITE8(port, mach->accel.ext_ge_config, val);
|
2023-12-06 15:00:31 +01:00
|
|
|
if ((dev->local & 0xff) >= 0x02) {
|
2023-08-15 00:11:56 +02:00
|
|
|
if (mach->accel.crt_pitch & 0xff)
|
|
|
|
|
dev->ext_crt_pitch = mach->accel.crt_pitch & 0xff;
|
2024-10-26 21:32:47 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
switch (mach->accel.ext_ge_config & 0x30) {
|
2024-10-26 21:32:47 +02:00
|
|
|
case 0x00:
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x10:
|
|
|
|
|
dev->bpp = 0;
|
|
|
|
|
break;
|
|
|
|
|
case 0x20:
|
|
|
|
|
dev->bpp = 1;
|
|
|
|
|
dev->ext_crt_pitch <<= 1;
|
|
|
|
|
break;
|
|
|
|
|
case 0x30:
|
|
|
|
|
dev->bpp = 0;
|
|
|
|
|
if (mach->accel.ext_ge_config & 0x200)
|
|
|
|
|
dev->ext_crt_pitch <<= 2;
|
|
|
|
|
else
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->ext_crt_pitch *= 3;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
break;
|
2023-08-11 20:32:56 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
svga_set_ramdac_type(svga, !!(mach->accel.ext_ge_config & 0x4000));
|
2024-04-20 23:43:27 +02:00
|
|
|
mach_log("ATI 8514/A: (0x%04x) val=%02x.\n", port, val);
|
2024-01-15 21:43:33 +01:00
|
|
|
svga_recalctimings(svga);
|
2024-11-13 22:55:16 +01:00
|
|
|
} else
|
2024-11-02 20:50:06 +01:00
|
|
|
ati_eeprom_write(&mach->eeprom, !!(mach->accel.ext_ge_config & 0x4000), !!(mach->accel.ext_ge_config & 0x2000), !!(mach->accel.ext_ge_config & 0x1000));
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
break;
|
2023-06-09 23:46:54 -04:00
|
|
|
|
2023-08-11 20:32:56 -04:00
|
|
|
default:
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2024-01-15 21:43:33 +01:00
|
|
|
static void
|
|
|
|
|
mach_accel_out(uint16_t port, uint8_t val, mach_t *mach)
|
|
|
|
|
{
|
|
|
|
|
svga_t *svga = &mach->svga;
|
|
|
|
|
|
|
|
|
|
mach_log("[%04X:%08X]: Port NORMAL OUT=%04x, val=%04x.\n", CS, cpu_state.pc, port, val);
|
|
|
|
|
|
|
|
|
|
mach_accel_out_call(port, val, mach, svga, (ibm8514_t *) svga->dev8514);
|
|
|
|
|
}
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
static uint16_t
|
|
|
|
|
mach_accel_in_fifo(mach_t *mach, svga_t *svga, ibm8514_t *dev, uint16_t port, int len)
|
2023-07-14 23:38:04 +02:00
|
|
|
{
|
2023-08-11 20:32:56 -04:00
|
|
|
const uint16_t *vram_w = (uint16_t *) dev->vram;
|
2024-11-13 22:55:16 +01:00
|
|
|
uint16_t temp = 0x0000;
|
2023-08-11 20:32:56 -04:00
|
|
|
int cmd;
|
2023-07-30 18:33:29 -04:00
|
|
|
int frgd_sel;
|
|
|
|
|
int bkgd_sel;
|
|
|
|
|
int mono_src;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
|
|
|
|
switch (port) {
|
|
|
|
|
case 0x82e8:
|
|
|
|
|
case 0x86e8:
|
|
|
|
|
case 0x92e8:
|
|
|
|
|
case 0x96e8:
|
2024-05-29 20:47:22 +02:00
|
|
|
case 0xc2e8:
|
|
|
|
|
case 0xc6e8:
|
|
|
|
|
temp = ibm8514_accel_in_fifo(svga, port, len);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x9ae8:
|
|
|
|
|
case 0xdae8:
|
2024-11-13 22:55:16 +01:00
|
|
|
if ((dev->fifo_idx >= 1) && (dev->fifo_idx <= 8)) {
|
|
|
|
|
temp |= (1 << (dev->fifo_idx - 1));
|
|
|
|
|
dev->fifo_idx = 0;
|
|
|
|
|
}
|
|
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if (len == 2) {
|
2023-07-14 23:38:04 +02:00
|
|
|
if (dev->force_busy)
|
|
|
|
|
temp |= 0x200; /*Hardware busy*/
|
2024-10-26 21:32:47 +02:00
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->force_busy = 0;
|
|
|
|
|
if (dev->data_available) {
|
|
|
|
|
temp |= 0x100; /*Read Data available*/
|
|
|
|
|
if (mach->accel.cmd_type >= 0) {
|
|
|
|
|
switch (mach->accel.cmd_type) {
|
|
|
|
|
case 2:
|
|
|
|
|
if (dev->accel.sy >= mach->accel.height)
|
|
|
|
|
dev->data_available = 0;
|
|
|
|
|
break;
|
|
|
|
|
case 5:
|
|
|
|
|
if (dev->accel.sx >= mach->accel.width)
|
|
|
|
|
dev->data_available = 0;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
if (dev->accel.sy < 0)
|
|
|
|
|
dev->data_available = 0;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
} else {
|
2024-11-13 22:55:16 +01:00
|
|
|
switch (dev->accel.cmd >> 13) {
|
|
|
|
|
case 2:
|
|
|
|
|
case 3:
|
|
|
|
|
case 4:
|
|
|
|
|
case 6:
|
|
|
|
|
if (dev->accel.sy < 0)
|
|
|
|
|
dev->data_available = 0;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
if (!dev->accel.sy)
|
|
|
|
|
dev->data_available = 0;
|
|
|
|
|
break;
|
|
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
mach_log("[%04X:%08X]: 9AE8: Temp = %04x, len = %d\n\n", CS, cpu_state.pc, temp, len);
|
|
|
|
|
break;
|
|
|
|
|
case 0x9ae9:
|
|
|
|
|
case 0xdae9:
|
|
|
|
|
if (len == 1) {
|
|
|
|
|
if (dev->force_busy2)
|
2024-10-26 21:32:47 +02:00
|
|
|
temp |= 0x02; /*Hardware busy*/
|
|
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->force_busy2 = 0;
|
|
|
|
|
if (dev->data_available2) {
|
2024-10-26 21:32:47 +02:00
|
|
|
temp |= 0x01; /*Read Data available*/
|
2023-07-14 23:38:04 +02:00
|
|
|
if (mach->accel.cmd_type >= 0) {
|
|
|
|
|
switch (mach->accel.cmd_type) {
|
|
|
|
|
case 2:
|
|
|
|
|
if (dev->accel.sy >= mach->accel.height)
|
|
|
|
|
dev->data_available2 = 0;
|
|
|
|
|
break;
|
|
|
|
|
case 5:
|
|
|
|
|
if (dev->accel.sx >= mach->accel.width)
|
|
|
|
|
dev->data_available2 = 0;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
if (dev->accel.sy < 0)
|
|
|
|
|
dev->data_available2 = 0;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
if (dev->accel.sy < 0)
|
|
|
|
|
dev->data_available2 = 0;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
mach_log("[%04X:%08X]: 9AE9: Temp = %04x, len = %d\n\n", CS, cpu_state.pc, temp, len);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xe2e8:
|
|
|
|
|
case 0xe6e8:
|
|
|
|
|
if (mach->accel.cmd_type >= 0) {
|
|
|
|
|
if (mach_pixel_read(mach)) {
|
|
|
|
|
cmd = -1;
|
|
|
|
|
if (len == 1) {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
READ_PIXTRANS_BYTE_IO(dev->accel.dx, 1)
|
2023-07-14 23:38:04 +02:00
|
|
|
temp = mach->accel.pix_trans[1];
|
|
|
|
|
} else {
|
|
|
|
|
if (mach->accel.cmd_type == 3) {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
READ_PIXTRANS_WORD(dev->accel.cx, 0)
|
2023-07-14 23:38:04 +02:00
|
|
|
} else {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
READ_PIXTRANS_WORD(dev->accel.dx, 0)
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_accel_out_pixtrans(svga, mach, dev, temp);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
if (ibm8514_cpu_dest(svga)) {
|
|
|
|
|
cmd = (dev->accel.cmd >> 13);
|
2024-10-26 21:32:47 +02:00
|
|
|
if (len == 2) {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
READ_PIXTRANS_WORD(dev->accel.cx, 0)
|
2024-10-26 21:32:47 +02:00
|
|
|
if (dev->subsys_stat & 0x01) {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
dev->force_busy = 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
dev->data_available = 1;
|
|
|
|
|
}
|
2024-10-26 21:32:47 +02:00
|
|
|
if (dev->accel.input) {
|
|
|
|
|
ibm8514_accel_out_pixtrans(svga, port, temp & 0xff, len);
|
|
|
|
|
if (dev->accel.odd_in) { /*WORDs on odd destination scan lengths.*/
|
|
|
|
|
dev->accel.odd_in = 0;
|
|
|
|
|
temp &= ~0xff00;
|
|
|
|
|
READ_HIGH(dev->accel.dest + dev->accel.cx, temp);
|
|
|
|
|
}
|
|
|
|
|
ibm8514_accel_out_pixtrans(svga, port, (temp >> 8) & 0xff, len);
|
|
|
|
|
} else
|
|
|
|
|
ibm8514_accel_out_pixtrans(svga, port, temp, len);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0xe2e9:
|
|
|
|
|
case 0xe6e9:
|
|
|
|
|
if (mach->accel.cmd_type >= 0) {
|
|
|
|
|
mach_log("%04x pixtrans read, len=%d.\n", port, len);
|
|
|
|
|
if (mach_pixel_read(mach)) {
|
|
|
|
|
if (len == 1) {
|
|
|
|
|
cmd = -1;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
READ_PIXTRANS_BYTE_IO(dev->accel.dx, 0)
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
temp = mach->accel.pix_trans[0];
|
2023-07-14 23:38:04 +02:00
|
|
|
frgd_sel = (mach->accel.dp_config >> 13) & 7;
|
|
|
|
|
bkgd_sel = (mach->accel.dp_config >> 7) & 3;
|
|
|
|
|
mono_src = (mach->accel.dp_config >> 5) & 3;
|
|
|
|
|
|
|
|
|
|
switch (mach->accel.dp_config & 0x200) {
|
|
|
|
|
case 0x000: /*8-bit size*/
|
|
|
|
|
if (mono_src == 2) {
|
|
|
|
|
if ((frgd_sel != 2) && (bkgd_sel != 2)) {
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_accel_start(mach->accel.cmd_type, 1, 8, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), 0, svga, mach, dev);
|
2023-07-14 23:38:04 +02:00
|
|
|
} else
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_accel_start(mach->accel.cmd_type, 1, 1, -1, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), svga, mach, dev);
|
2023-07-14 23:38:04 +02:00
|
|
|
} else
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_accel_start(mach->accel.cmd_type, 1, 1, -1, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), svga, mach, dev);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 0x200: /*16-bit size*/
|
|
|
|
|
if (mono_src == 2) {
|
|
|
|
|
if ((frgd_sel != 2) && (bkgd_sel != 2)) {
|
|
|
|
|
if (mach->accel.dp_config & 0x1000)
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_accel_start(mach->accel.cmd_type, 1, 16, mach->accel.pix_trans[1] | (mach->accel.pix_trans[0] << 8), 0, svga, mach, dev);
|
2023-07-14 23:38:04 +02:00
|
|
|
else
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_accel_start(mach->accel.cmd_type, 1, 16, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), 0, svga, mach, dev);
|
2023-07-14 23:38:04 +02:00
|
|
|
} else
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_accel_start(mach->accel.cmd_type, 1, 2, -1, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), svga, mach, dev);
|
2023-07-14 23:38:04 +02:00
|
|
|
} else
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_accel_start(mach->accel.cmd_type, 1, 2, -1, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), svga, mach, dev);
|
2023-06-09 23:46:54 -04:00
|
|
|
break;
|
2023-08-11 20:32:56 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x82ee:
|
2024-10-26 21:32:47 +02:00
|
|
|
if (len == 2)
|
|
|
|
|
temp = mach->accel.patt_data_idx;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
break;
|
|
|
|
|
|
2023-12-28 02:01:45 +01:00
|
|
|
case 0x86ee:
|
|
|
|
|
case 0x86ef:
|
|
|
|
|
temp = 0x0000;
|
|
|
|
|
break;
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x8eee:
|
2023-07-14 23:38:04 +02:00
|
|
|
if (len == 1)
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
temp = mach->accel.ext_ge_config & 0xff;
|
2023-07-14 23:38:04 +02:00
|
|
|
else
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
temp = mach->accel.ext_ge_config;
|
|
|
|
|
|
|
|
|
|
mach_log("ExtGE Read = %04x, len=%d.\n", temp, len);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x8eef:
|
2023-07-14 23:38:04 +02:00
|
|
|
if (len == 1)
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
temp = mach->accel.ext_ge_config >> 8;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x92ee:
|
2023-07-14 23:38:04 +02:00
|
|
|
if (len == 1)
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
temp = mach->accel.eeprom_control & 0xff;
|
2023-07-14 23:38:04 +02:00
|
|
|
else
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
temp = mach->accel.eeprom_control;
|
|
|
|
|
|
|
|
|
|
mach_log("EEPROM cntl read=%04x, len=%d.\n", temp, len);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x92ef:
|
2023-07-14 23:38:04 +02:00
|
|
|
if (len == 1)
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
temp = mach->accel.eeprom_control >> 8;
|
|
|
|
|
|
|
|
|
|
mach_log("EEPROM cntl read+1=%02x, len=%d.\n", temp, len);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x96ee:
|
2024-01-15 21:43:33 +01:00
|
|
|
if (len == 1)
|
2024-05-29 20:47:22 +02:00
|
|
|
temp = mach->accel.test & 0xff;
|
|
|
|
|
else
|
|
|
|
|
temp = mach->accel.test;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x96ef:
|
2023-07-14 23:38:04 +02:00
|
|
|
if (len == 1)
|
2024-05-29 20:47:22 +02:00
|
|
|
temp = mach->accel.test >> 8;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
2024-11-13 22:55:16 +01:00
|
|
|
case 0x9aee:
|
|
|
|
|
if (len == 2) {
|
|
|
|
|
if ((dev->ext_fifo_idx >= 1) && (dev->ext_fifo_idx <= 16)) {
|
|
|
|
|
temp |= (1 << (dev->ext_fifo_idx - 1));
|
|
|
|
|
dev->ext_fifo_idx = 0;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0xa2ee:
|
2023-07-14 23:38:04 +02:00
|
|
|
if (len == 1)
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
temp = mach->accel.linedraw_opt & 0xff;
|
2024-01-15 21:43:33 +01:00
|
|
|
else
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
temp = mach->accel.linedraw_opt;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0xa2ef:
|
2023-07-14 23:38:04 +02:00
|
|
|
if (len == 1)
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
temp = mach->accel.linedraw_opt >> 8;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0xb2ee:
|
|
|
|
|
if (len == 1)
|
2024-01-15 21:43:33 +01:00
|
|
|
temp = dev->hdisped;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
else {
|
2024-01-15 21:43:33 +01:00
|
|
|
temp = dev->hdisped & 0xff;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
temp |= (dev->htotal << 8);
|
|
|
|
|
}
|
2024-04-20 23:43:27 +02:00
|
|
|
mach_log("B2EE read=%02x.\n", temp & 0xff);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0xb2ef:
|
2024-01-15 21:43:33 +01:00
|
|
|
if (len == 1)
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
temp = dev->htotal;
|
2024-01-15 21:43:33 +01:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xb6ee:
|
|
|
|
|
temp = dev->hsync_start;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xbaee:
|
|
|
|
|
temp = dev->hsync_width;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0xc2ee:
|
|
|
|
|
if (len == 1)
|
2024-04-20 23:43:27 +02:00
|
|
|
temp = dev->v_total_reg & 0xff;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
else {
|
2024-04-20 23:43:27 +02:00
|
|
|
temp = dev->v_total_reg;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
mach_log("VTOTAL read=%d.\n", temp);
|
|
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0xc2ef:
|
|
|
|
|
if (len == 1)
|
2024-04-20 23:43:27 +02:00
|
|
|
temp = dev->v_total_reg >> 8;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0xc6ee:
|
2023-07-14 23:38:04 +02:00
|
|
|
if (len == 1)
|
2024-01-15 21:43:33 +01:00
|
|
|
temp = dev->v_disp & 0xff;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
else {
|
2024-01-15 21:43:33 +01:00
|
|
|
temp = dev->v_disp;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
mach_log("VDISP read=%d.\n", temp);
|
|
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0xc6ef:
|
2023-07-14 23:38:04 +02:00
|
|
|
if (len == 1)
|
2024-01-15 21:43:33 +01:00
|
|
|
temp = dev->v_disp >> 8;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0xcaee:
|
2023-07-14 23:38:04 +02:00
|
|
|
if (len == 1)
|
2024-01-26 19:03:43 +01:00
|
|
|
temp = dev->v_sync_start & 0xff;
|
2023-07-14 23:38:04 +02:00
|
|
|
else
|
2024-01-26 19:03:43 +01:00
|
|
|
temp = dev->v_sync_start;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0xcaef:
|
2023-07-14 23:38:04 +02:00
|
|
|
if (len == 1)
|
2024-01-26 19:03:43 +01:00
|
|
|
temp = dev->v_sync_start >> 8;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0xceee:
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_log("CEEE read=%d.\n", len);
|
2023-07-14 23:38:04 +02:00
|
|
|
if (len == 1)
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
temp = dev->vc & 0xff;
|
2023-07-14 23:38:04 +02:00
|
|
|
else
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
temp = dev->vc & 0x7ff;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0xceef:
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_log("CEEF read=%d.\n", len);
|
2023-07-14 23:38:04 +02:00
|
|
|
if (len == 1)
|
2024-11-02 20:50:06 +01:00
|
|
|
temp = (dev->vc >> 8) & 0x07;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0xdaee:
|
2024-10-26 21:32:47 +02:00
|
|
|
if (len == 2) {
|
2023-12-06 15:00:31 +01:00
|
|
|
if ((dev->local & 0xff) >= 0x02)
|
2024-10-26 21:32:47 +02:00
|
|
|
temp = mach->accel.src_x;
|
2024-10-27 23:36:11 +01:00
|
|
|
} else {
|
|
|
|
|
if ((dev->local & 0xff) >= 0x02)
|
|
|
|
|
temp = mach->accel.src_x & 0xff;
|
|
|
|
|
}
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
break;
|
|
|
|
|
case 0xdaef:
|
2024-10-27 23:36:11 +01:00
|
|
|
if (len == 1) {
|
|
|
|
|
if ((dev->local & 0xff) >= 0x02)
|
|
|
|
|
temp = mach->accel.src_x >> 8;
|
|
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
|
|
|
|
|
case 0xdeee:
|
2024-10-26 21:32:47 +02:00
|
|
|
if (len == 2) {
|
2023-12-06 15:00:31 +01:00
|
|
|
if ((dev->local & 0xff) >= 0x02)
|
2024-10-26 21:32:47 +02:00
|
|
|
temp = mach->accel.src_y;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
} else
|
|
|
|
|
temp = mach->accel.src_y & 0xff;
|
|
|
|
|
break;
|
|
|
|
|
case 0xdeef:
|
2024-11-02 20:50:06 +01:00
|
|
|
if (len == 1) {
|
|
|
|
|
if ((dev->local & 0xff) >= 0x02)
|
|
|
|
|
temp = mach->accel.src_y >> 8;
|
|
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0xfaee:
|
2024-10-26 21:32:47 +02:00
|
|
|
if (len == 2) {
|
2024-05-29 20:47:22 +02:00
|
|
|
if ((dev->local & 0xff) >= 0x02) {
|
|
|
|
|
if (mach->pci_bus)
|
|
|
|
|
temp = 0x0017;
|
|
|
|
|
else
|
|
|
|
|
temp = 0x22f7;
|
|
|
|
|
}
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
} else {
|
2024-05-29 20:47:22 +02:00
|
|
|
if ((dev->local & 0xff) >= 0x02) {
|
|
|
|
|
if (mach->pci_bus)
|
|
|
|
|
temp = 0x17;
|
|
|
|
|
else
|
|
|
|
|
temp = 0xf7;
|
|
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
break;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0xfaef:
|
2023-07-14 23:38:04 +02:00
|
|
|
if (len == 1) {
|
2024-05-29 20:47:22 +02:00
|
|
|
if ((dev->local & 0xff) >= 0x02) {
|
|
|
|
|
if (mach->pci_bus)
|
|
|
|
|
temp = 0x00;
|
|
|
|
|
else
|
|
|
|
|
temp = 0x22;
|
|
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
break;
|
2023-08-11 20:32:56 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
|
2024-11-13 22:55:16 +01:00
|
|
|
mach_log("[%04X:%08X]: Port FIFO IN=%04x, temp=%04x, len=%d.\n", CS, cpu_state.pc, port, temp, len);
|
2024-01-15 21:43:33 +01:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
return temp;
|
|
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
static uint8_t
|
2024-01-15 21:43:33 +01:00
|
|
|
mach_accel_in_call(uint16_t port, mach_t *mach, svga_t *svga, ibm8514_t *dev)
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
{
|
2024-10-26 21:32:47 +02:00
|
|
|
uint8_t temp = 0;
|
2024-11-02 20:50:06 +01:00
|
|
|
int16_t clip_t = dev->accel.clip_top;
|
|
|
|
|
int16_t clip_l = dev->accel.clip_left;
|
|
|
|
|
int16_t clip_b = dev->accel.clip_bottom;
|
|
|
|
|
int16_t clip_r = dev->accel.clip_right;
|
|
|
|
|
uint16_t clip_b_ibm = dev->accel.clip_bottom;
|
|
|
|
|
uint16_t clip_r_ibm = dev->accel.clip_right;
|
|
|
|
|
int cmd = dev->accel.cmd >> 13;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
switch (port) {
|
|
|
|
|
case 0x2e8:
|
|
|
|
|
case 0x6e8:
|
|
|
|
|
case 0x22e8:
|
|
|
|
|
case 0x26e8:
|
2024-05-29 20:47:22 +02:00
|
|
|
case 0x26e9:
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x2ee8:
|
|
|
|
|
case 0x2ee9:
|
2024-05-29 20:47:22 +02:00
|
|
|
temp = ibm8514_accel_in(port, svga);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x42e8:
|
2023-08-11 20:32:56 -04:00
|
|
|
case 0x42e9:
|
2024-05-29 20:47:22 +02:00
|
|
|
if (dev->vc == dev->v_syncstart)
|
2024-11-13 22:55:16 +01:00
|
|
|
temp |= 0x01;
|
2024-11-02 20:50:06 +01:00
|
|
|
|
|
|
|
|
if (mach->accel.cmd_type == -1) {
|
|
|
|
|
if (cmd == 6) {
|
|
|
|
|
if ((dev->accel.dx >= clip_l) &&
|
|
|
|
|
(dev->accel.dx <= clip_r_ibm) &&
|
|
|
|
|
(dev->accel.dy >= clip_t) &&
|
|
|
|
|
(dev->accel.dy <= clip_b_ibm))
|
2024-11-13 22:55:16 +01:00
|
|
|
temp |= 0x02;
|
2024-11-02 20:50:06 +01:00
|
|
|
} else {
|
|
|
|
|
if ((dev->accel.cx >= clip_l) &&
|
|
|
|
|
(dev->accel.cx <= clip_r_ibm) &&
|
|
|
|
|
(dev->accel.cy >= clip_t) &&
|
|
|
|
|
(dev->accel.cy <= clip_b_ibm))
|
2024-11-13 22:55:16 +01:00
|
|
|
temp |= 0x02;
|
2024-11-02 20:50:06 +01:00
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
switch (mach->accel.cmd_type) {
|
|
|
|
|
case 1:
|
|
|
|
|
case 2:
|
|
|
|
|
case 5:
|
|
|
|
|
if ((dev->accel.dx >= clip_l) &&
|
|
|
|
|
(dev->accel.dx <= clip_r) &&
|
|
|
|
|
(dev->accel.dy >= clip_t) &&
|
|
|
|
|
(dev->accel.dy <= clip_b))
|
2024-11-13 22:55:16 +01:00
|
|
|
temp |= 0x02;
|
2024-11-02 20:50:06 +01:00
|
|
|
break;
|
|
|
|
|
case 3:
|
|
|
|
|
case 4:
|
2024-11-13 22:55:16 +01:00
|
|
|
if ((dev->accel.cx >= clip_l) &&
|
|
|
|
|
(dev->accel.cx <= clip_r) &&
|
|
|
|
|
(dev->accel.cy >= clip_t) &&
|
|
|
|
|
(dev->accel.cy <= clip_b))
|
|
|
|
|
temp |= 0x02;
|
2024-11-02 20:50:06 +01:00
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
2024-05-29 20:47:22 +02:00
|
|
|
|
2024-11-13 22:55:16 +01:00
|
|
|
if ((!dev->fifo_idx || !dev->ext_fifo_idx)) {
|
|
|
|
|
if ((!dev->force_busy && !dev->force_busy2) || !mach->force_busy)
|
|
|
|
|
temp |= 0x08;
|
|
|
|
|
}
|
2024-01-15 21:43:33 +01:00
|
|
|
if (port & 1)
|
2024-10-26 21:32:47 +02:00
|
|
|
temp = dev->vram_512k_8514 ? 0x00 : 0x80;
|
2024-01-15 21:43:33 +01:00
|
|
|
else {
|
2024-11-13 22:55:16 +01:00
|
|
|
temp |= (dev->subsys_stat | (dev->vram_512k_8514 ? 0x00 : 0x80));
|
2024-01-15 21:43:33 +01:00
|
|
|
if (mach->accel.ext_ge_config & 0x08)
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
temp |= ((mach->accel.ext_ge_config & 0x07) << 4);
|
2024-01-15 21:43:33 +01:00
|
|
|
else
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
temp |= 0x20;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
2024-05-29 20:47:22 +02:00
|
|
|
mach_log("0x%04x read: Subsystem Status=%02x.\n", port, temp);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
|
|
|
|
|
/*ATI Mach8/32 specific registers*/
|
|
|
|
|
case 0x12ee:
|
|
|
|
|
case 0x12ef:
|
|
|
|
|
READ8(port, mach->config1);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
|
|
|
|
|
case 0x16ee:
|
|
|
|
|
case 0x16ef:
|
|
|
|
|
READ8(port, mach->config2);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
2024-05-29 20:47:22 +02:00
|
|
|
case 0x1aee:
|
|
|
|
|
case 0x1aef:
|
|
|
|
|
temp = 0x00;
|
|
|
|
|
break;
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x22ee:
|
2024-01-15 21:43:33 +01:00
|
|
|
if (mach->pci_bus)
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
temp = mach->pci_cntl_reg;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
|
|
|
|
|
case 0x32ee:
|
|
|
|
|
case 0x32ef:
|
|
|
|
|
READ8(port, mach->local_cntl);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x36ee:
|
|
|
|
|
case 0x36ef:
|
2024-11-13 22:55:16 +01:00
|
|
|
if ((dev->local & 0xff) >= 0x02) {
|
|
|
|
|
READ8(port, mach->misc);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
|
2024-11-13 22:55:16 +01:00
|
|
|
if (!(port & 1)) {
|
|
|
|
|
temp &= ~0x0c;
|
|
|
|
|
switch (dev->vram_amount) {
|
|
|
|
|
case 1024:
|
|
|
|
|
temp |= 0x04;
|
|
|
|
|
break;
|
|
|
|
|
case 2048:
|
|
|
|
|
temp |= 0x08;
|
|
|
|
|
break;
|
|
|
|
|
case 4096:
|
|
|
|
|
temp |= 0x0c;
|
|
|
|
|
break;
|
2023-08-11 20:32:56 -04:00
|
|
|
|
2024-11-13 22:55:16 +01:00
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
}
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
break;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
|
|
|
|
|
case 0x42ee:
|
|
|
|
|
case 0x42ef:
|
2023-12-28 02:01:45 +01:00
|
|
|
READ8(port, mach->accel.test2);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x46ee:
|
|
|
|
|
case 0x46ef:
|
2024-01-15 21:43:33 +01:00
|
|
|
READ8(port, mach->shadow_cntl);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x4aee:
|
|
|
|
|
case 0x4aef:
|
|
|
|
|
READ8(port, mach->accel.clock_sel);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
|
|
|
|
|
case 0x52ee:
|
|
|
|
|
case 0x52ef:
|
|
|
|
|
READ8(port, mach->accel.scratch0);
|
2024-11-13 22:55:16 +01:00
|
|
|
if (mach->mca_bus) {
|
|
|
|
|
if (svga->ext8514 != NULL) {
|
|
|
|
|
temp = (((dev->bios_rom.mapping.base >> 7) - 0x1000) >> 4);
|
2024-11-02 20:50:06 +01:00
|
|
|
if (port & 1)
|
2024-11-13 22:55:16 +01:00
|
|
|
temp |= 0x01;
|
2024-11-02 20:50:06 +01:00
|
|
|
}
|
|
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x56ee:
|
|
|
|
|
case 0x56ef:
|
|
|
|
|
READ8(port, mach->accel.scratch1);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
|
|
|
|
|
case 0x5eee:
|
|
|
|
|
case 0x5eef:
|
|
|
|
|
if (mach->pci_bus)
|
|
|
|
|
mach->memory_aperture = (mach->memory_aperture & ~0xfff0) | ((mach->linear_base >> 20) << 4);
|
2023-08-15 00:11:56 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
READ8(port, mach->memory_aperture);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x62ee:
|
|
|
|
|
temp = mach->accel.clip_overrun;
|
|
|
|
|
mach_log("ClipOverrun = %02x.\n", temp);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x62ef:
|
|
|
|
|
if (mach->force_busy)
|
|
|
|
|
temp |= 0x20;
|
2023-12-14 21:47:10 +01:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
mach->force_busy = 0;
|
|
|
|
|
if (ati_eeprom_read(&mach->eeprom))
|
|
|
|
|
temp |= 0x40;
|
2024-05-29 20:47:22 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
mach_log("Mach busy temp=%02x.\n", temp);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x6aee:
|
|
|
|
|
case 0x6aef:
|
|
|
|
|
READ8(port, mach->accel.max_waitstates);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
|
|
|
|
|
case 0x72ee:
|
|
|
|
|
case 0x72ef:
|
2024-01-05 21:22:01 +01:00
|
|
|
READ8(port, (mach->accel.bleft));
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x76ee:
|
|
|
|
|
case 0x76ef:
|
2024-01-05 21:22:01 +01:00
|
|
|
READ8(port, (mach->accel.btop));
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
|
|
|
|
|
case 0x7aee:
|
|
|
|
|
case 0x7aef:
|
2024-01-05 21:22:01 +01:00
|
|
|
READ8(port, (mach->accel.bright));
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
2023-06-09 23:46:54 -04:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
case 0x7eee:
|
|
|
|
|
case 0x7eef:
|
2024-01-05 21:22:01 +01:00
|
|
|
READ8(port, (mach->accel.bbottom));
|
2023-06-09 23:46:54 -04:00
|
|
|
break;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
|
2023-08-11 20:32:56 -04:00
|
|
|
default:
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
2024-11-13 22:55:16 +01:00
|
|
|
mach_log("[%04X:%08X]: Port NORMAL IN=%04x, temp=%04x.\n", CS, cpu_state.pc, port, temp);
|
2024-01-15 21:43:33 +01:00
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
return temp;
|
|
|
|
|
}
|
|
|
|
|
|
2024-01-15 21:43:33 +01:00
|
|
|
static void
|
|
|
|
|
ati8514_accel_out(uint16_t port, uint8_t val, svga_t *svga)
|
|
|
|
|
{
|
|
|
|
|
mach_log("[%04X:%08X]: Port NORMAL OUT=%04x, val=%04x.\n", CS, cpu_state.pc, port, val);
|
|
|
|
|
|
|
|
|
|
mach_accel_out_call(port, val, (mach_t *)svga->ext8514, svga, (ibm8514_t *) svga->dev8514);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
ati8514_accel_outb(uint16_t port, uint8_t val, void *priv)
|
|
|
|
|
{
|
|
|
|
|
svga_t *svga = (svga_t *)priv;
|
|
|
|
|
mach_t *mach = (mach_t *)svga->ext8514;
|
|
|
|
|
|
|
|
|
|
if (port & 0x8000)
|
|
|
|
|
mach_accel_out_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port, val, 1);
|
|
|
|
|
else
|
|
|
|
|
ati8514_accel_out(port, val, svga);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
ati8514_accel_outw(uint16_t port, uint16_t val, void *priv)
|
|
|
|
|
{
|
|
|
|
|
svga_t *svga = (svga_t *)priv;
|
|
|
|
|
mach_t *mach = (mach_t *)svga->ext8514;
|
|
|
|
|
|
|
|
|
|
if (port & 0x8000)
|
|
|
|
|
mach_accel_out_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port, val, 2);
|
|
|
|
|
else {
|
|
|
|
|
ati8514_accel_out(port, val, svga);
|
|
|
|
|
ati8514_accel_out(port + 1, (val >> 8), svga);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
ati8514_accel_outl(uint16_t port, uint32_t val, void *priv)
|
|
|
|
|
{
|
|
|
|
|
svga_t *svga = (svga_t *)priv;
|
|
|
|
|
mach_t *mach = (mach_t *)svga->ext8514;
|
|
|
|
|
|
|
|
|
|
if (port & 0x8000) {
|
|
|
|
|
mach_accel_out_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port, val & 0xffff, 2);
|
|
|
|
|
mach_accel_out_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port + 2, val >> 16, 2);
|
|
|
|
|
} else {
|
|
|
|
|
ati8514_accel_out(port, val, svga);
|
|
|
|
|
ati8514_accel_out(port + 1, (val >> 8), svga);
|
|
|
|
|
ati8514_accel_out(port + 2, (val >> 16), svga);
|
|
|
|
|
ati8514_accel_out(port + 3, (val >> 24), svga);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
static void
|
2023-06-09 23:46:54 -04:00
|
|
|
mach_accel_outb(uint16_t port, uint8_t val, void *priv)
|
2023-07-14 23:38:04 +02:00
|
|
|
{
|
2023-06-09 23:46:54 -04:00
|
|
|
mach_t *mach = (mach_t *) priv;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
svga_t *svga = &mach->svga;
|
|
|
|
|
|
|
|
|
|
if (port & 0x8000)
|
2023-10-09 20:14:03 +02:00
|
|
|
mach_accel_out_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port, val, 1);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
else
|
|
|
|
|
mach_accel_out(port, val, mach);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2023-06-09 23:46:54 -04:00
|
|
|
mach_accel_outw(uint16_t port, uint16_t val, void *priv)
|
2023-07-14 23:38:04 +02:00
|
|
|
{
|
2023-06-09 23:46:54 -04:00
|
|
|
mach_t *mach = (mach_t *) priv;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
svga_t *svga = &mach->svga;
|
|
|
|
|
|
|
|
|
|
if (port & 0x8000)
|
2023-10-09 20:14:03 +02:00
|
|
|
mach_accel_out_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port, val, 2);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
else {
|
|
|
|
|
mach_accel_out(port, val, mach);
|
|
|
|
|
mach_accel_out(port + 1, (val >> 8), mach);
|
|
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
static void
|
|
|
|
|
mach_accel_outl(uint16_t port, uint32_t val, void *priv)
|
|
|
|
|
{
|
|
|
|
|
mach_t *mach = (mach_t *) priv;
|
|
|
|
|
svga_t *svga = &mach->svga;
|
|
|
|
|
|
|
|
|
|
if (port & 0x8000) {
|
2023-10-09 20:14:03 +02:00
|
|
|
mach_accel_out_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port, val & 0xffff, 2);
|
|
|
|
|
mach_accel_out_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port + 2, val >> 16, 2);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
} else {
|
|
|
|
|
mach_accel_out(port, val, mach);
|
|
|
|
|
mach_accel_out(port + 1, (val >> 8), mach);
|
|
|
|
|
mach_accel_out(port + 2, (val >> 16), mach);
|
|
|
|
|
mach_accel_out(port + 3, (val >> 24), mach);
|
|
|
|
|
}
|
|
|
|
|
}
|
2024-01-15 21:43:33 +01:00
|
|
|
|
|
|
|
|
static uint8_t
|
|
|
|
|
ati8514_accel_in(uint16_t port, svga_t *svga)
|
|
|
|
|
{
|
|
|
|
|
return mach_accel_in_call(port, (mach_t *) svga->ext8514, svga, (ibm8514_t *) svga->dev8514);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static uint8_t
|
|
|
|
|
ati8514_accel_inb(uint16_t port, void *priv)
|
|
|
|
|
{
|
|
|
|
|
svga_t *svga = (svga_t *)priv;
|
|
|
|
|
mach_t *mach = (mach_t *)svga->ext8514;
|
|
|
|
|
uint8_t temp;
|
|
|
|
|
|
|
|
|
|
if (port & 0x8000)
|
|
|
|
|
temp = mach_accel_in_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port, 1);
|
|
|
|
|
else
|
|
|
|
|
temp = ati8514_accel_in(port, svga);
|
|
|
|
|
|
|
|
|
|
return temp;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static uint16_t
|
|
|
|
|
ati8514_accel_inw(uint16_t port, void *priv)
|
|
|
|
|
{
|
|
|
|
|
svga_t *svga = (svga_t *)priv;
|
|
|
|
|
mach_t *mach = (mach_t *)svga->ext8514;
|
|
|
|
|
uint16_t temp;
|
|
|
|
|
|
|
|
|
|
if (port & 0x8000)
|
|
|
|
|
temp = mach_accel_in_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port, 2);
|
|
|
|
|
else {
|
|
|
|
|
temp = ati8514_accel_in(port, svga);
|
|
|
|
|
temp |= (ati8514_accel_in(port + 1, svga) << 8);
|
|
|
|
|
}
|
|
|
|
|
return temp;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static uint32_t
|
|
|
|
|
ati8514_accel_inl(uint16_t port, void *priv)
|
|
|
|
|
{
|
|
|
|
|
svga_t *svga = (svga_t *)priv;
|
|
|
|
|
mach_t *mach = (mach_t *)svga->ext8514;
|
|
|
|
|
uint32_t temp;
|
|
|
|
|
|
|
|
|
|
if (port & 0x8000) {
|
|
|
|
|
temp = mach_accel_in_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port, 2);
|
|
|
|
|
temp = (mach_accel_in_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port + 2, 2) << 16);
|
|
|
|
|
} else {
|
|
|
|
|
temp = ati8514_accel_in(port, svga);
|
|
|
|
|
temp |= (ati8514_accel_in(port + 1, svga) << 8);
|
|
|
|
|
temp |= (ati8514_accel_in(port + 2, svga) << 16);
|
|
|
|
|
temp |= (ati8514_accel_in(port + 3, svga) << 24);
|
|
|
|
|
}
|
|
|
|
|
return temp;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static uint8_t
|
|
|
|
|
mach_accel_in(uint16_t port, mach_t *mach)
|
|
|
|
|
{
|
|
|
|
|
svga_t *svga = &mach->svga;
|
|
|
|
|
return mach_accel_in_call(port, mach, svga, (ibm8514_t *) svga->dev8514);
|
|
|
|
|
}
|
|
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
static uint8_t
|
2023-06-09 23:46:54 -04:00
|
|
|
mach_accel_inb(uint16_t port, void *priv)
|
2023-07-14 23:38:04 +02:00
|
|
|
{
|
2023-06-09 23:46:54 -04:00
|
|
|
mach_t *mach = (mach_t *) priv;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
svga_t *svga = &mach->svga;
|
|
|
|
|
uint8_t temp;
|
|
|
|
|
|
|
|
|
|
if (port & 0x8000)
|
2023-10-09 20:14:03 +02:00
|
|
|
temp = mach_accel_in_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port, 1);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
else
|
|
|
|
|
temp = mach_accel_in(port, mach);
|
|
|
|
|
|
|
|
|
|
return temp;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static uint16_t
|
2023-06-09 23:46:54 -04:00
|
|
|
mach_accel_inw(uint16_t port, void *priv)
|
2023-07-14 23:38:04 +02:00
|
|
|
{
|
2023-06-09 23:46:54 -04:00
|
|
|
mach_t *mach = (mach_t *) priv;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
svga_t *svga = &mach->svga;
|
|
|
|
|
uint16_t temp;
|
|
|
|
|
|
|
|
|
|
if (port & 0x8000)
|
2023-10-09 20:14:03 +02:00
|
|
|
temp = mach_accel_in_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port, 2);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
else {
|
|
|
|
|
temp = mach_accel_in(port, mach);
|
|
|
|
|
temp |= (mach_accel_in(port + 1, mach) << 8);
|
|
|
|
|
}
|
|
|
|
|
return temp;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static uint32_t
|
|
|
|
|
mach_accel_inl(uint16_t port, void *priv)
|
|
|
|
|
{
|
|
|
|
|
mach_t *mach = (mach_t *) priv;
|
|
|
|
|
svga_t *svga = &mach->svga;
|
|
|
|
|
uint32_t temp;
|
|
|
|
|
|
|
|
|
|
if (port & 0x8000) {
|
2023-10-09 20:14:03 +02:00
|
|
|
temp = mach_accel_in_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port, 2);
|
|
|
|
|
temp = (mach_accel_in_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port + 2, 2) << 16);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
} else {
|
|
|
|
|
temp = mach_accel_in(port, mach);
|
|
|
|
|
temp |= (mach_accel_in(port + 1, mach) << 8);
|
|
|
|
|
temp |= (mach_accel_in(port + 2, mach) << 16);
|
|
|
|
|
temp |= (mach_accel_in(port + 3, mach) << 24);
|
|
|
|
|
}
|
|
|
|
|
return temp;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
2023-12-06 15:00:31 +01:00
|
|
|
static __inline void
|
2024-05-29 20:47:22 +02:00
|
|
|
mach32_write_common(uint32_t addr, uint8_t val, int linear, mach_t *mach, svga_t *svga)
|
2023-08-15 00:11:56 +02:00
|
|
|
{
|
2023-10-09 20:14:03 +02:00
|
|
|
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
2023-08-15 00:11:56 +02:00
|
|
|
int writemask2 = svga->writemask;
|
|
|
|
|
int reset_wm = 0;
|
2024-05-16 22:33:50 +02:00
|
|
|
latch8514_t vall;
|
2023-08-15 00:11:56 +02:00
|
|
|
uint8_t wm = svga->writemask;
|
|
|
|
|
uint8_t i;
|
|
|
|
|
|
|
|
|
|
cycles -= svga->monitor->mon_video_timing_write_b;
|
|
|
|
|
|
2024-05-16 22:33:50 +02:00
|
|
|
if (linear) {
|
2024-10-26 21:32:47 +02:00
|
|
|
if (!dev->vram_512k_8514 && ((mach->accel.ext_ge_config & 0x30) == 0x00))
|
|
|
|
|
addr <<= 1;
|
|
|
|
|
|
2024-05-16 22:33:50 +02:00
|
|
|
addr &= dev->vram_mask;
|
|
|
|
|
dev->changedvram[addr >> 12] = svga->monitor->mon_changeframecount;
|
2024-10-26 21:32:47 +02:00
|
|
|
if (!dev->vram_512k_8514 && ((mach->accel.ext_ge_config & 0x30) == 0x00)) {
|
|
|
|
|
switch (addr & 0x06) {
|
|
|
|
|
case 0x00:
|
|
|
|
|
case 0x06:
|
|
|
|
|
dev->vram[addr] = val & 0x0f;
|
|
|
|
|
dev->vram[addr + 1] = (val >> 4) & 0x0f;
|
|
|
|
|
break;
|
|
|
|
|
case 0x02:
|
|
|
|
|
dev->vram[addr + 2] = val & 0x0f;
|
|
|
|
|
dev->vram[addr + 3] = (val >> 4) & 0x0f;
|
|
|
|
|
break;
|
|
|
|
|
case 0x04:
|
|
|
|
|
dev->vram[addr - 2] = val & 0x0f;
|
|
|
|
|
dev->vram[addr - 1] = (val >> 4) & 0x0f;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
} else
|
|
|
|
|
dev->vram[addr] = val;
|
|
|
|
|
|
2024-05-16 22:33:50 +02:00
|
|
|
return;
|
2023-12-06 15:00:31 +01:00
|
|
|
}
|
|
|
|
|
|
2023-08-15 00:11:56 +02:00
|
|
|
if (!(svga->gdcreg[6] & 1))
|
|
|
|
|
svga->fullchange = 2;
|
|
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if (svga->chain4) {
|
2023-08-15 00:11:56 +02:00
|
|
|
writemask2 = 1 << (addr & 3);
|
|
|
|
|
addr &= ~3;
|
|
|
|
|
} else if (svga->chain2_write) {
|
|
|
|
|
writemask2 &= ~0xa;
|
|
|
|
|
if (addr & 1)
|
|
|
|
|
writemask2 <<= 1;
|
2024-10-26 21:32:47 +02:00
|
|
|
|
2023-08-15 00:11:56 +02:00
|
|
|
addr &= ~1;
|
|
|
|
|
addr &= dev->vram_mask;
|
|
|
|
|
} else {
|
|
|
|
|
writemask2 = 1 << (addr & 3);
|
|
|
|
|
addr &= ~3;
|
|
|
|
|
addr &= dev->vram_mask;
|
|
|
|
|
}
|
|
|
|
|
addr &= svga->decode_mask;
|
|
|
|
|
|
2024-10-27 23:36:11 +01:00
|
|
|
if (addr >= dev->vram_size) {
|
|
|
|
|
mach_log("WriteOver! %x.\n", addr);
|
2023-08-15 00:11:56 +02:00
|
|
|
return;
|
2024-10-27 23:36:11 +01:00
|
|
|
}
|
2023-08-15 00:11:56 +02:00
|
|
|
|
|
|
|
|
addr &= dev->vram_mask;
|
|
|
|
|
dev->changedvram[addr >> 12] = svga->monitor->mon_changeframecount;
|
|
|
|
|
|
2024-10-27 23:36:11 +01:00
|
|
|
switch (svga->writemode) {
|
|
|
|
|
case 0:
|
|
|
|
|
val = ((val >> (svga->gdcreg[3] & 7)) | (val << (8 - (svga->gdcreg[3] & 7))));
|
|
|
|
|
if ((svga->gdcreg[8] == 0xff) && !(svga->gdcreg[3] & 0x18) && (!svga->gdcreg[1] || svga->set_reset_disabled)) {
|
2024-10-26 21:32:47 +02:00
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
|
if (writemask2 & (1 << i))
|
2024-10-27 23:36:11 +01:00
|
|
|
dev->vram[addr | i] = val;
|
2023-08-15 00:11:56 +02:00
|
|
|
}
|
2024-10-27 23:36:11 +01:00
|
|
|
return;
|
|
|
|
|
} else {
|
2024-10-26 21:32:47 +02:00
|
|
|
for (i = 0; i < 4; i++) {
|
2024-10-27 23:36:11 +01:00
|
|
|
if (svga->gdcreg[1] & (1 << i))
|
|
|
|
|
vall.b[i] = !!(svga->gdcreg[0] & (1 << i)) * 0xff;
|
|
|
|
|
else
|
|
|
|
|
vall.b[i] = val;
|
2023-08-15 00:11:56 +02:00
|
|
|
}
|
2024-10-27 23:36:11 +01:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 1:
|
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
|
if (writemask2 & (1 << i))
|
|
|
|
|
dev->vram[addr | i] = dev->latch.b[i];
|
|
|
|
|
}
|
|
|
|
|
return;
|
|
|
|
|
case 2:
|
|
|
|
|
for (i = 0; i < 4; i++)
|
|
|
|
|
vall.b[i] = !!(val & (1 << i)) * 0xff;
|
|
|
|
|
|
|
|
|
|
if (!(svga->gdcreg[3] & 0x18) && (!svga->gdcreg[1] || svga->set_reset_disabled)) {
|
2024-10-26 21:32:47 +02:00
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
|
if (writemask2 & (1 << i))
|
2024-10-27 23:36:11 +01:00
|
|
|
dev->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) | (dev->latch.b[i] & ~svga->gdcreg[8]);
|
2024-10-26 21:32:47 +02:00
|
|
|
}
|
2024-10-27 23:36:11 +01:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 3:
|
|
|
|
|
val = ((val >> (svga->gdcreg[3] & 7)) | (val << (8 - (svga->gdcreg[3] & 7))));
|
|
|
|
|
wm = svga->gdcreg[8];
|
|
|
|
|
svga->gdcreg[8] &= val;
|
2023-08-15 00:11:56 +02:00
|
|
|
|
2024-10-27 23:36:11 +01:00
|
|
|
for (i = 0; i < 4; i++)
|
|
|
|
|
vall.b[i] = !!(svga->gdcreg[0] & (1 << i)) * 0xff;
|
|
|
|
|
|
|
|
|
|
reset_wm = 1;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
switch (svga->gdcreg[3] & 0x18) {
|
|
|
|
|
case 0x00: /* Set */
|
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
|
if (writemask2 & (1 << i))
|
|
|
|
|
dev->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) | (dev->latch.b[i] & ~svga->gdcreg[8]);
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0x08: /* AND */
|
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
|
if (writemask2 & (1 << i))
|
|
|
|
|
dev->vram[addr | i] = (vall.b[i] | ~svga->gdcreg[8]) & dev->latch.b[i];
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0x10: /* OR */
|
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
|
if (writemask2 & (1 << i))
|
|
|
|
|
dev->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) | dev->latch.b[i];
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0x18: /* XOR */
|
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
|
if (writemask2 & (1 << i))
|
|
|
|
|
dev->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) ^ dev->latch.b[i];
|
|
|
|
|
}
|
|
|
|
|
break;
|
2023-08-15 00:11:56 +02:00
|
|
|
|
2024-10-27 23:36:11 +01:00
|
|
|
default:
|
|
|
|
|
break;
|
2023-08-15 00:11:56 +02:00
|
|
|
}
|
2024-10-27 23:36:11 +01:00
|
|
|
|
|
|
|
|
if (reset_wm)
|
|
|
|
|
svga->gdcreg[8] = wm;
|
2023-08-15 00:11:56 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
mach32_write(uint32_t addr, uint8_t val, void *priv)
|
|
|
|
|
{
|
Video, Storage and MCA changes/fixes.
1. Cirrus Logic GD54xx, Paradise/WD VGA now reset the interlace once a text mode is issued if not done automatically.
2. Paradise/WD's 15/16bpp modes using the 800x600 resolution now have the correct ma_latch, should fix most operating systems drivers using this combo.
3. More fixes (hopefully) to the accelerated pitch and rowoffset of the Trident TGUI cards (9440AGi and 96x0XGi), should fix issues with delayed displays mode changes under various operating systems (e.g.: Win3.1x).
4. Preliminary implementation of the Area Fill command of XGA, which is issued while using various painting and/or calc utilities on Win3.1x (IBM XGA updated drivers, e.g.: 2.12).
5. Preliminary (and incomplete) 4bpp XGA mode.
6. The XGA memory test for the 0xa5 using writes (used by various operating systems) no longer conflicts with DOS' XGAKIT's memory detection.
7. Small ROP fixes to both XGA and 8514/A.
8. Re-organized the mapping of the Mach32 chipset, especially when to enable the ATI mode or switching back to IBM mode, should fix LFB conflicts with various operating systems.
9. According to The OS/2 Museum, the Adaptec AHA-154xB series of SCSI cards fail the ASPI4DOS.SYS 3.36 signature check, so now make the changes accordingly.
10. Remove useless and crashy bios-less option of the Trantor T128.
11. The Image Manager 1024 card can also be used on a XT (although only if it has a V20/V30).
12. Re-organized the IBM PS/2 model 60 initialization as well as its right POS machine ID (though an update to sc.exe is still required for the POST memory amount to work normally).
2023-09-30 22:08:08 +02:00
|
|
|
mach_t *mach = (mach_t *) priv;
|
2024-10-26 21:32:47 +02:00
|
|
|
svga_t *svga = &mach->svga;
|
|
|
|
|
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
|
|
|
|
|
|
|
|
|
xga_write_test(addr, val, svga);
|
|
|
|
|
addr = (addr & svga->banked_mask) + svga->write_bank;
|
|
|
|
|
|
|
|
|
|
if ((((dev->local & 0xff) >= 0x02) && !dev->vram_512k_8514) && ((mach->accel.ext_ge_config & 0x30) == 0x00)) {
|
|
|
|
|
addr <<= 1;
|
|
|
|
|
switch (addr & 0x06) {
|
|
|
|
|
case 0x00:
|
|
|
|
|
case 0x06:
|
|
|
|
|
mach32_write_common(addr, val & 0x0f, 0, mach, svga);
|
|
|
|
|
mach32_write_common(addr + 1, (val >> 4) & 0x0f, 0, mach, svga);
|
|
|
|
|
break;
|
|
|
|
|
case 0x02:
|
|
|
|
|
mach32_write_common(addr + 2, val & 0x0f, 0, mach, svga);
|
|
|
|
|
mach32_write_common(addr + 3, (val >> 4) & 0x0f, 0, mach, svga);
|
|
|
|
|
break;
|
|
|
|
|
case 0x04:
|
|
|
|
|
mach32_write_common(addr - 2, val & 0x0f, 0, mach, svga);
|
|
|
|
|
mach32_write_common(addr - 1, (val >> 4) & 0x0f, 0, mach, svga);
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
} else
|
|
|
|
|
mach32_write_common(addr, val, 0, mach, svga);
|
2023-08-15 00:11:56 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
mach32_writew(uint32_t addr, uint16_t val, void *priv)
|
|
|
|
|
{
|
Video, Storage and MCA changes/fixes.
1. Cirrus Logic GD54xx, Paradise/WD VGA now reset the interlace once a text mode is issued if not done automatically.
2. Paradise/WD's 15/16bpp modes using the 800x600 resolution now have the correct ma_latch, should fix most operating systems drivers using this combo.
3. More fixes (hopefully) to the accelerated pitch and rowoffset of the Trident TGUI cards (9440AGi and 96x0XGi), should fix issues with delayed displays mode changes under various operating systems (e.g.: Win3.1x).
4. Preliminary implementation of the Area Fill command of XGA, which is issued while using various painting and/or calc utilities on Win3.1x (IBM XGA updated drivers, e.g.: 2.12).
5. Preliminary (and incomplete) 4bpp XGA mode.
6. The XGA memory test for the 0xa5 using writes (used by various operating systems) no longer conflicts with DOS' XGAKIT's memory detection.
7. Small ROP fixes to both XGA and 8514/A.
8. Re-organized the mapping of the Mach32 chipset, especially when to enable the ATI mode or switching back to IBM mode, should fix LFB conflicts with various operating systems.
9. According to The OS/2 Museum, the Adaptec AHA-154xB series of SCSI cards fail the ASPI4DOS.SYS 3.36 signature check, so now make the changes accordingly.
10. Remove useless and crashy bios-less option of the Trantor T128.
11. The Image Manager 1024 card can also be used on a XT (although only if it has a V20/V30).
12. Re-organized the IBM PS/2 model 60 initialization as well as its right POS machine ID (though an update to sc.exe is still required for the POST memory amount to work normally).
2023-09-30 22:08:08 +02:00
|
|
|
mach_t *mach = (mach_t *) priv;
|
2024-10-26 21:32:47 +02:00
|
|
|
svga_t *svga = &mach->svga;
|
|
|
|
|
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
|
|
|
|
|
|
|
|
|
xga_write_test(addr, val, svga);
|
|
|
|
|
addr = (addr & svga->banked_mask) + svga->write_bank;
|
|
|
|
|
|
|
|
|
|
if ((((dev->local & 0xff) >= 0x02) && !dev->vram_512k_8514) && ((mach->accel.ext_ge_config & 0x30) == 0x00)) {
|
|
|
|
|
addr <<= 1;
|
|
|
|
|
if (addr & 0x04) {
|
|
|
|
|
mach32_write_common(addr - 2, val & 0x0f, 0, mach, svga);
|
|
|
|
|
mach32_write_common(addr - 1, (val >> 4) & 0x0f, 0, mach, svga);
|
|
|
|
|
mach32_write_common(addr + 2, (val >> 8) & 0x0f, 0, mach, svga);
|
|
|
|
|
mach32_write_common(addr + 3, (val >> 12) & 0x0f, 0, mach, svga);
|
|
|
|
|
} else {
|
|
|
|
|
mach32_write_common(addr, val & 0x0f, 0, mach, svga);
|
|
|
|
|
mach32_write_common(addr + 1, (val >> 4) & 0x0f, 0, mach, svga);
|
|
|
|
|
mach32_write_common(addr + 4, (val >> 8) & 0x0f, 0, mach, svga);
|
|
|
|
|
mach32_write_common(addr + 5, (val >> 12) & 0x0f, 0, mach, svga);
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
mach32_write_common(addr, val & 0xff, 0, mach, svga);
|
|
|
|
|
mach32_write_common(addr + 1, val >> 8, 0, mach, svga);
|
|
|
|
|
}
|
2023-08-15 00:11:56 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
mach32_writel(uint32_t addr, uint32_t val, void *priv)
|
|
|
|
|
{
|
Video, Storage and MCA changes/fixes.
1. Cirrus Logic GD54xx, Paradise/WD VGA now reset the interlace once a text mode is issued if not done automatically.
2. Paradise/WD's 15/16bpp modes using the 800x600 resolution now have the correct ma_latch, should fix most operating systems drivers using this combo.
3. More fixes (hopefully) to the accelerated pitch and rowoffset of the Trident TGUI cards (9440AGi and 96x0XGi), should fix issues with delayed displays mode changes under various operating systems (e.g.: Win3.1x).
4. Preliminary implementation of the Area Fill command of XGA, which is issued while using various painting and/or calc utilities on Win3.1x (IBM XGA updated drivers, e.g.: 2.12).
5. Preliminary (and incomplete) 4bpp XGA mode.
6. The XGA memory test for the 0xa5 using writes (used by various operating systems) no longer conflicts with DOS' XGAKIT's memory detection.
7. Small ROP fixes to both XGA and 8514/A.
8. Re-organized the mapping of the Mach32 chipset, especially when to enable the ATI mode or switching back to IBM mode, should fix LFB conflicts with various operating systems.
9. According to The OS/2 Museum, the Adaptec AHA-154xB series of SCSI cards fail the ASPI4DOS.SYS 3.36 signature check, so now make the changes accordingly.
10. Remove useless and crashy bios-less option of the Trantor T128.
11. The Image Manager 1024 card can also be used on a XT (although only if it has a V20/V30).
12. Re-organized the IBM PS/2 model 60 initialization as well as its right POS machine ID (though an update to sc.exe is still required for the POST memory amount to work normally).
2023-09-30 22:08:08 +02:00
|
|
|
mach_t *mach = (mach_t *) priv;
|
2024-10-26 21:32:47 +02:00
|
|
|
svga_t *svga = &mach->svga;
|
|
|
|
|
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
|
|
|
|
|
|
|
|
|
xga_write_test(addr, val, svga);
|
|
|
|
|
addr = (addr & svga->banked_mask) + svga->write_bank;
|
|
|
|
|
|
|
|
|
|
if ((((dev->local & 0xff) >= 0x02) && !dev->vram_512k_8514) && ((mach->accel.ext_ge_config & 0x30) == 0x00)) {
|
|
|
|
|
addr <<= 1;
|
|
|
|
|
mach32_write_common(addr, val & 0x0f, 0, mach, svga);
|
|
|
|
|
mach32_write_common(addr + 1, (val >> 4) & 0x0f, 0, mach, svga);
|
|
|
|
|
mach32_write_common(addr + 4, (val >> 8) & 0x0f, 0, mach, svga);
|
|
|
|
|
mach32_write_common(addr + 5, (val >> 12) & 0x0f, 0, mach, svga);
|
|
|
|
|
mach32_write_common(addr + 2, (val >> 16) & 0x0f, 0, mach, svga);
|
|
|
|
|
mach32_write_common(addr + 3, (val >> 20) & 0x0f, 0, mach, svga);
|
|
|
|
|
mach32_write_common(addr + 6, (val >> 24) & 0x0f, 0, mach, svga);
|
|
|
|
|
mach32_write_common(addr + 7, (val >> 28) & 0x0f, 0, mach, svga);
|
|
|
|
|
} else {
|
|
|
|
|
mach32_write_common(addr, val & 0xff, 0, mach, svga);
|
|
|
|
|
mach32_write_common(addr + 1, val >> 8, 0, mach, svga);
|
|
|
|
|
mach32_write_common(addr + 2, val >> 16, 0, mach, svga);
|
|
|
|
|
mach32_write_common(addr + 3, val >> 24, 0, mach, svga);
|
|
|
|
|
}
|
2023-08-15 00:11:56 +02:00
|
|
|
}
|
|
|
|
|
|
2024-05-16 22:33:50 +02:00
|
|
|
static __inline void
|
|
|
|
|
mach32_writew_linear(uint32_t addr, uint16_t val, mach_t *mach)
|
|
|
|
|
{
|
|
|
|
|
svga_t *svga = &mach->svga;
|
|
|
|
|
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
|
|
|
|
|
|
|
|
|
cycles -= svga->monitor->mon_video_timing_write_w;
|
2024-10-26 21:32:47 +02:00
|
|
|
if (!dev->vram_512k_8514 && ((mach->accel.ext_ge_config & 0x30) == 0x00))
|
|
|
|
|
addr <<= 1;
|
2024-05-16 22:33:50 +02:00
|
|
|
|
|
|
|
|
addr &= dev->vram_mask;
|
|
|
|
|
dev->changedvram[addr >> 12] = svga->monitor->mon_changeframecount;
|
2024-10-26 21:32:47 +02:00
|
|
|
if (!dev->vram_512k_8514 && ((mach->accel.ext_ge_config & 0x30) == 0x00)) {
|
|
|
|
|
if (addr & 0x04) {
|
|
|
|
|
dev->vram[addr - 2] = val & 0x0f;
|
|
|
|
|
dev->vram[addr - 1] = (val >> 4) & 0x0f;
|
|
|
|
|
dev->vram[addr + 2] = (val >> 8) & 0x0f;
|
|
|
|
|
dev->vram[addr + 3] = (val >> 12) & 0x0f;
|
|
|
|
|
} else {
|
|
|
|
|
dev->vram[addr] = val & 0x0f;
|
|
|
|
|
dev->vram[addr + 1] = (val >> 4) & 0x0f;
|
|
|
|
|
dev->vram[addr + 4] = (val >> 8) & 0x0f;
|
|
|
|
|
dev->vram[addr + 5] = (val >> 12) & 0x0f;
|
|
|
|
|
}
|
|
|
|
|
} else
|
|
|
|
|
*(uint16_t *) &dev->vram[addr] = val;
|
2024-05-16 22:33:50 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline void
|
|
|
|
|
mach32_writel_linear(uint32_t addr, uint32_t val, mach_t *mach)
|
|
|
|
|
{
|
|
|
|
|
svga_t *svga = &mach->svga;
|
|
|
|
|
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
|
|
|
|
|
|
|
|
|
cycles -= svga->monitor->mon_video_timing_write_l;
|
|
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if (!dev->vram_512k_8514 && ((mach->accel.ext_ge_config & 0x30) == 0x00))
|
|
|
|
|
addr <<= 1;
|
|
|
|
|
|
2024-05-16 22:33:50 +02:00
|
|
|
addr &= dev->vram_mask;
|
|
|
|
|
dev->changedvram[addr >> 12] = svga->monitor->mon_changeframecount;
|
2024-10-26 21:32:47 +02:00
|
|
|
if (!dev->vram_512k_8514 && ((mach->accel.ext_ge_config & 0x30) == 0x00)) {
|
|
|
|
|
dev->vram[addr] = val & 0x0f;
|
|
|
|
|
dev->vram[addr + 1] = (val >> 4) & 0x0f;
|
|
|
|
|
dev->vram[addr + 4] = (val >> 8) & 0x0f;
|
|
|
|
|
dev->vram[addr + 5] = (val >> 12) & 0x0f;
|
|
|
|
|
dev->vram[addr + 2] = (val >> 16) & 0x0f;
|
|
|
|
|
dev->vram[addr + 3] = (val >> 20) & 0x0f;
|
|
|
|
|
dev->vram[addr + 6] = (val >> 24) & 0x0f;
|
|
|
|
|
dev->vram[addr + 7] = (val >> 28) & 0x0f;
|
|
|
|
|
} else
|
|
|
|
|
*(uint32_t *) &dev->vram[addr] = val;
|
2024-05-16 22:33:50 +02:00
|
|
|
}
|
|
|
|
|
|
2023-12-06 15:00:31 +01:00
|
|
|
static __inline uint8_t
|
2024-05-29 20:47:22 +02:00
|
|
|
mach32_read_common(uint32_t addr, int linear, mach_t *mach, svga_t *svga)
|
2023-08-15 00:11:56 +02:00
|
|
|
{
|
2024-05-16 22:33:50 +02:00
|
|
|
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
2023-08-14 18:59:02 -04:00
|
|
|
uint32_t latch_addr = 0;
|
|
|
|
|
int readplane = svga->readplane;
|
|
|
|
|
uint8_t count;
|
|
|
|
|
uint8_t temp;
|
2024-10-26 21:32:47 +02:00
|
|
|
uint8_t ret = 0x00;
|
2023-08-15 00:11:56 +02:00
|
|
|
|
|
|
|
|
cycles -= svga->monitor->mon_video_timing_read_b;
|
|
|
|
|
|
2024-05-16 22:33:50 +02:00
|
|
|
if (linear) {
|
2024-10-26 21:32:47 +02:00
|
|
|
if (!dev->vram_512k_8514 && ((mach->accel.ext_ge_config & 0x30) == 0x00))
|
|
|
|
|
addr <<= 1;
|
|
|
|
|
|
|
|
|
|
addr &= dev->vram_mask;
|
|
|
|
|
if (!dev->vram_512k_8514 && ((mach->accel.ext_ge_config & 0x30) == 0x00)) {
|
|
|
|
|
switch (addr & 0x06) {
|
|
|
|
|
case 0x00:
|
|
|
|
|
case 0x06:
|
|
|
|
|
ret = dev->vram[addr] & 0x0f;
|
|
|
|
|
ret |= (dev->vram[addr + 1] << 4);
|
|
|
|
|
break;
|
|
|
|
|
case 0x02:
|
|
|
|
|
ret = dev->vram[addr + 2] & 0x0f;
|
|
|
|
|
ret |= (dev->vram[addr + 3] << 4);
|
|
|
|
|
break;
|
|
|
|
|
case 0x04:
|
|
|
|
|
ret = dev->vram[addr - 2] & 0x0f;
|
|
|
|
|
ret |= (dev->vram[addr - 1] << 4);
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
} else
|
|
|
|
|
ret = dev->vram[addr];
|
|
|
|
|
|
|
|
|
|
return ret;
|
2023-12-06 15:00:31 +01:00
|
|
|
}
|
|
|
|
|
|
2023-08-15 00:11:56 +02:00
|
|
|
count = 2;
|
|
|
|
|
|
|
|
|
|
latch_addr = (addr << count) & svga->decode_mask;
|
|
|
|
|
count = (1 << count);
|
|
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if (svga->chain4) {
|
2023-08-15 00:11:56 +02:00
|
|
|
addr &= svga->decode_mask;
|
2024-10-27 23:36:11 +01:00
|
|
|
if (addr >= dev->vram_size) {
|
|
|
|
|
mach_log("ReadOver! (chain4) %x.\n", addr);
|
2023-08-15 00:11:56 +02:00
|
|
|
return 0xff;
|
2024-10-27 23:36:11 +01:00
|
|
|
}
|
2023-08-15 00:11:56 +02:00
|
|
|
latch_addr = (addr & dev->vram_mask) & ~3;
|
|
|
|
|
for (uint8_t i = 0; i < count; i++)
|
2024-05-16 22:33:50 +02:00
|
|
|
dev->latch.b[i] = dev->vram[latch_addr | i];
|
2023-08-15 00:11:56 +02:00
|
|
|
return dev->vram[addr & dev->vram_mask];
|
|
|
|
|
} else if (svga->chain2_read) {
|
|
|
|
|
readplane = (readplane & 2) | (addr & 1);
|
|
|
|
|
addr &= ~1;
|
|
|
|
|
addr &= dev->vram_mask;
|
|
|
|
|
} else {
|
|
|
|
|
addr &= svga->decode_mask;
|
2024-10-27 23:36:11 +01:00
|
|
|
if (addr >= dev->vram_size) {
|
|
|
|
|
mach_log("ReadOver! (normal) %x.\n", addr);
|
2023-08-15 00:11:56 +02:00
|
|
|
return 0xff;
|
2024-10-27 23:36:11 +01:00
|
|
|
}
|
2023-08-15 00:11:56 +02:00
|
|
|
latch_addr = (addr & dev->vram_mask) & ~3;
|
|
|
|
|
for (uint8_t i = 0; i < count; i++)
|
2024-05-16 22:33:50 +02:00
|
|
|
dev->latch.b[i] = dev->vram[latch_addr | i];
|
2024-11-02 20:50:06 +01:00
|
|
|
|
|
|
|
|
mach_log("Read (normal) addr=%06x, ret=%02x.\n", addr, dev->vram[addr & dev->vram_mask]);
|
2023-08-15 00:11:56 +02:00
|
|
|
return dev->vram[addr & dev->vram_mask];
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
addr &= svga->decode_mask;
|
|
|
|
|
|
|
|
|
|
/* standard VGA latched access */
|
|
|
|
|
if (latch_addr >= dev->vram_size) {
|
2024-10-27 23:36:11 +01:00
|
|
|
mach_log("Over VRAM Latch addr=%x.\n", latch_addr);
|
2023-08-15 00:11:56 +02:00
|
|
|
for (uint8_t i = 0; i < count; i++)
|
2024-05-16 22:33:50 +02:00
|
|
|
dev->latch.b[i] = 0xff;
|
2023-08-15 00:11:56 +02:00
|
|
|
} else {
|
|
|
|
|
latch_addr &= dev->vram_mask;
|
|
|
|
|
|
|
|
|
|
for (uint8_t i = 0; i < count; i++)
|
2024-05-16 22:33:50 +02:00
|
|
|
dev->latch.b[i] = dev->vram[latch_addr | i];
|
2023-08-15 00:11:56 +02:00
|
|
|
}
|
|
|
|
|
|
2024-10-27 23:36:11 +01:00
|
|
|
if (addr >= dev->vram_size) {
|
|
|
|
|
mach_log("ReadOver! (chain2) %x.\n", addr);
|
2023-08-15 00:11:56 +02:00
|
|
|
return 0xff;
|
2024-10-27 23:36:11 +01:00
|
|
|
}
|
2023-08-15 00:11:56 +02:00
|
|
|
|
|
|
|
|
addr &= dev->vram_mask;
|
|
|
|
|
|
|
|
|
|
if (svga->readmode) {
|
|
|
|
|
temp = 0xff;
|
|
|
|
|
|
|
|
|
|
for (uint8_t pixel = 0; pixel < 8; pixel++) {
|
|
|
|
|
for (uint8_t plane = 0; plane < count; plane++) {
|
|
|
|
|
if (svga->colournocare & (1 << plane)) {
|
|
|
|
|
/* If we care about a plane, and the pixel has a mismatch on it, clear its bit. */
|
2024-05-16 22:33:50 +02:00
|
|
|
if (((dev->latch.b[plane] >> pixel) & 1) != ((svga->colourcompare >> plane) & 1))
|
2023-08-15 00:11:56 +02:00
|
|
|
temp &= ~(1 << pixel);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ret = temp;
|
|
|
|
|
} else
|
|
|
|
|
ret = dev->vram[addr | readplane];
|
|
|
|
|
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_log("ReadMode=%02x, addr=%06x, ret=%02x.\n", svga->readmode, addr, ret);
|
2023-08-15 00:11:56 +02:00
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static uint8_t
|
|
|
|
|
mach32_read(uint32_t addr, void *priv)
|
|
|
|
|
{
|
Video, Storage and MCA changes/fixes.
1. Cirrus Logic GD54xx, Paradise/WD VGA now reset the interlace once a text mode is issued if not done automatically.
2. Paradise/WD's 15/16bpp modes using the 800x600 resolution now have the correct ma_latch, should fix most operating systems drivers using this combo.
3. More fixes (hopefully) to the accelerated pitch and rowoffset of the Trident TGUI cards (9440AGi and 96x0XGi), should fix issues with delayed displays mode changes under various operating systems (e.g.: Win3.1x).
4. Preliminary implementation of the Area Fill command of XGA, which is issued while using various painting and/or calc utilities on Win3.1x (IBM XGA updated drivers, e.g.: 2.12).
5. Preliminary (and incomplete) 4bpp XGA mode.
6. The XGA memory test for the 0xa5 using writes (used by various operating systems) no longer conflicts with DOS' XGAKIT's memory detection.
7. Small ROP fixes to both XGA and 8514/A.
8. Re-organized the mapping of the Mach32 chipset, especially when to enable the ATI mode or switching back to IBM mode, should fix LFB conflicts with various operating systems.
9. According to The OS/2 Museum, the Adaptec AHA-154xB series of SCSI cards fail the ASPI4DOS.SYS 3.36 signature check, so now make the changes accordingly.
10. Remove useless and crashy bios-less option of the Trantor T128.
11. The Image Manager 1024 card can also be used on a XT (although only if it has a V20/V30).
12. Re-organized the IBM PS/2 model 60 initialization as well as its right POS machine ID (though an update to sc.exe is still required for the POST memory amount to work normally).
2023-09-30 22:08:08 +02:00
|
|
|
mach_t *mach = (mach_t *) priv;
|
2024-10-26 21:32:47 +02:00
|
|
|
svga_t *svga = &mach->svga;
|
|
|
|
|
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
|
|
|
|
uint8_t ret = 0x00;
|
|
|
|
|
|
|
|
|
|
(void) xga_read_test(addr, svga);
|
|
|
|
|
addr = (addr & svga->banked_mask) + svga->read_bank;
|
|
|
|
|
|
|
|
|
|
if ((((dev->local & 0xff) >= 0x02) && !dev->vram_512k_8514) && ((mach->accel.ext_ge_config & 0x30) == 0x00)) {
|
|
|
|
|
addr <<= 1;
|
|
|
|
|
switch (addr & 0x06) {
|
|
|
|
|
case 0x00:
|
|
|
|
|
case 0x06:
|
|
|
|
|
ret = mach32_read_common(addr, 0, mach, svga) & 0x0f;
|
|
|
|
|
ret |= (mach32_read_common(addr + 1, 0, mach, svga) << 4);
|
|
|
|
|
break;
|
|
|
|
|
case 0x02:
|
|
|
|
|
ret = mach32_read_common(addr + 2, 0, mach, svga) & 0x0f;
|
|
|
|
|
ret |= (mach32_read_common(addr + 3, 0, mach, svga) << 4);
|
|
|
|
|
break;
|
|
|
|
|
case 0x04:
|
|
|
|
|
ret = mach32_read_common(addr - 2, 0, mach, svga) & 0x0f;
|
|
|
|
|
ret |= (mach32_read_common(addr - 1, 0, mach, svga) << 4);
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
} else
|
|
|
|
|
ret = mach32_read_common(addr, 0, mach, svga);
|
2023-08-15 00:11:56 +02:00
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static uint16_t
|
|
|
|
|
mach32_readw(uint32_t addr, void *priv)
|
|
|
|
|
{
|
Video, Storage and MCA changes/fixes.
1. Cirrus Logic GD54xx, Paradise/WD VGA now reset the interlace once a text mode is issued if not done automatically.
2. Paradise/WD's 15/16bpp modes using the 800x600 resolution now have the correct ma_latch, should fix most operating systems drivers using this combo.
3. More fixes (hopefully) to the accelerated pitch and rowoffset of the Trident TGUI cards (9440AGi and 96x0XGi), should fix issues with delayed displays mode changes under various operating systems (e.g.: Win3.1x).
4. Preliminary implementation of the Area Fill command of XGA, which is issued while using various painting and/or calc utilities on Win3.1x (IBM XGA updated drivers, e.g.: 2.12).
5. Preliminary (and incomplete) 4bpp XGA mode.
6. The XGA memory test for the 0xa5 using writes (used by various operating systems) no longer conflicts with DOS' XGAKIT's memory detection.
7. Small ROP fixes to both XGA and 8514/A.
8. Re-organized the mapping of the Mach32 chipset, especially when to enable the ATI mode or switching back to IBM mode, should fix LFB conflicts with various operating systems.
9. According to The OS/2 Museum, the Adaptec AHA-154xB series of SCSI cards fail the ASPI4DOS.SYS 3.36 signature check, so now make the changes accordingly.
10. Remove useless and crashy bios-less option of the Trantor T128.
11. The Image Manager 1024 card can also be used on a XT (although only if it has a V20/V30).
12. Re-organized the IBM PS/2 model 60 initialization as well as its right POS machine ID (though an update to sc.exe is still required for the POST memory amount to work normally).
2023-09-30 22:08:08 +02:00
|
|
|
mach_t *mach = (mach_t *) priv;
|
2024-10-26 21:32:47 +02:00
|
|
|
svga_t *svga = &mach->svga;
|
|
|
|
|
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
|
|
|
|
uint16_t ret;
|
|
|
|
|
|
|
|
|
|
(void) xga_read_test(addr, svga);
|
|
|
|
|
addr = (addr & svga->banked_mask) + svga->read_bank;
|
|
|
|
|
|
|
|
|
|
if ((((dev->local & 0xff) >= 0x02) && !dev->vram_512k_8514) && ((mach->accel.ext_ge_config & 0x30) == 0x00)) {
|
|
|
|
|
addr <<= 1;
|
|
|
|
|
if (addr & 0x04) {
|
|
|
|
|
ret = mach32_read_common(addr - 2, 0, mach, svga) & 0x0f;
|
|
|
|
|
ret |= (mach32_read_common(addr - 1, 0, mach, svga) << 4);
|
|
|
|
|
ret |= (mach32_read_common(addr + 2, 0, mach, svga) << 8);
|
|
|
|
|
ret |= (mach32_read_common(addr + 3, 0, mach, svga) << 12);
|
|
|
|
|
} else {
|
|
|
|
|
ret = mach32_read_common(addr, 0, mach, svga) & 0x0f;
|
|
|
|
|
ret |= (mach32_read_common(addr + 1, 0, mach, svga) << 4);
|
|
|
|
|
ret |= (mach32_read_common(addr + 4, 0, mach, svga) << 8);
|
|
|
|
|
ret |= (mach32_read_common(addr + 5, 0, mach, svga) << 12);
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
ret = mach32_read_common(addr, 0, mach, svga);
|
|
|
|
|
ret |= (mach32_read_common(addr + 1, 0, mach, svga) << 8);
|
|
|
|
|
}
|
2023-08-15 00:11:56 +02:00
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static uint32_t
|
|
|
|
|
mach32_readl(uint32_t addr, void *priv)
|
|
|
|
|
{
|
Video, Storage and MCA changes/fixes.
1. Cirrus Logic GD54xx, Paradise/WD VGA now reset the interlace once a text mode is issued if not done automatically.
2. Paradise/WD's 15/16bpp modes using the 800x600 resolution now have the correct ma_latch, should fix most operating systems drivers using this combo.
3. More fixes (hopefully) to the accelerated pitch and rowoffset of the Trident TGUI cards (9440AGi and 96x0XGi), should fix issues with delayed displays mode changes under various operating systems (e.g.: Win3.1x).
4. Preliminary implementation of the Area Fill command of XGA, which is issued while using various painting and/or calc utilities on Win3.1x (IBM XGA updated drivers, e.g.: 2.12).
5. Preliminary (and incomplete) 4bpp XGA mode.
6. The XGA memory test for the 0xa5 using writes (used by various operating systems) no longer conflicts with DOS' XGAKIT's memory detection.
7. Small ROP fixes to both XGA and 8514/A.
8. Re-organized the mapping of the Mach32 chipset, especially when to enable the ATI mode or switching back to IBM mode, should fix LFB conflicts with various operating systems.
9. According to The OS/2 Museum, the Adaptec AHA-154xB series of SCSI cards fail the ASPI4DOS.SYS 3.36 signature check, so now make the changes accordingly.
10. Remove useless and crashy bios-less option of the Trantor T128.
11. The Image Manager 1024 card can also be used on a XT (although only if it has a V20/V30).
12. Re-organized the IBM PS/2 model 60 initialization as well as its right POS machine ID (though an update to sc.exe is still required for the POST memory amount to work normally).
2023-09-30 22:08:08 +02:00
|
|
|
mach_t *mach = (mach_t *) priv;
|
2024-10-26 21:32:47 +02:00
|
|
|
svga_t *svga = &mach->svga;
|
|
|
|
|
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
|
|
|
|
uint32_t ret;
|
|
|
|
|
|
|
|
|
|
(void) xga_read_test(addr, svga);
|
|
|
|
|
addr = (addr & svga->banked_mask) + svga->read_bank;
|
|
|
|
|
|
|
|
|
|
if ((((dev->local & 0xff) >= 0x02) && !dev->vram_512k_8514) && ((mach->accel.ext_ge_config & 0x30) == 0x00)) {
|
|
|
|
|
addr <<= 1;
|
|
|
|
|
ret = mach32_read_common(addr, 0, mach, svga) & 0x0f;
|
|
|
|
|
ret |= (mach32_read_common(addr + 1, 0, mach, svga) << 4);
|
|
|
|
|
ret |= (mach32_read_common(addr + 4, 0, mach, svga) << 8);
|
|
|
|
|
ret |= (mach32_read_common(addr + 5, 0, mach, svga) << 12);
|
|
|
|
|
ret |= (mach32_read_common(addr + 2, 0, mach, svga) << 16);
|
|
|
|
|
ret |= (mach32_read_common(addr + 3, 0, mach, svga) << 20);
|
|
|
|
|
ret |= (mach32_read_common(addr + 6, 0, mach, svga) << 24);
|
|
|
|
|
ret |= (mach32_read_common(addr + 7, 0, mach, svga) << 28);
|
|
|
|
|
} else {
|
|
|
|
|
ret = mach32_read_common(addr, 0, mach, svga);
|
|
|
|
|
ret |= (mach32_read_common(addr + 1, 0, mach, svga) << 8);
|
|
|
|
|
ret |= (mach32_read_common(addr + 2, 0, mach, svga) << 16);
|
|
|
|
|
ret |= (mach32_read_common(addr + 3, 0, mach, svga) << 24);
|
|
|
|
|
}
|
2023-08-15 00:11:56 +02:00
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2024-05-16 22:33:50 +02:00
|
|
|
static __inline uint16_t
|
|
|
|
|
mach32_readw_linear(uint32_t addr, mach_t *mach)
|
|
|
|
|
{
|
|
|
|
|
svga_t *svga = &mach->svga;
|
|
|
|
|
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
2024-10-26 21:32:47 +02:00
|
|
|
uint16_t ret;
|
2024-05-16 22:33:50 +02:00
|
|
|
|
|
|
|
|
cycles -= svga->monitor->mon_video_timing_read_w;
|
2024-10-26 21:32:47 +02:00
|
|
|
if (!dev->vram_512k_8514 && ((mach->accel.ext_ge_config & 0x30) == 0x00)) {
|
|
|
|
|
addr <<= 1;
|
|
|
|
|
addr &= dev->vram_mask;
|
|
|
|
|
if (addr & 0x04) {
|
|
|
|
|
ret = dev->vram[addr - 2] & 0x0f;
|
|
|
|
|
ret |= (dev->vram[addr - 1] << 4);
|
|
|
|
|
ret |= (dev->vram[addr + 2] << 8);
|
|
|
|
|
ret |= (dev->vram[addr + 3] << 12);
|
|
|
|
|
} else {
|
|
|
|
|
ret = dev->vram[addr] & 0x0f;
|
|
|
|
|
ret |= (dev->vram[addr + 1] << 4);
|
|
|
|
|
ret |= (dev->vram[addr + 4] << 8);
|
|
|
|
|
ret |= (dev->vram[addr + 5] << 12);
|
|
|
|
|
}
|
|
|
|
|
} else
|
|
|
|
|
ret = *(uint16_t *) &dev->vram[addr & dev->vram_mask];
|
2024-05-16 22:33:50 +02:00
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
return ret;
|
2024-05-16 22:33:50 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline uint32_t
|
|
|
|
|
mach32_readl_linear(uint32_t addr, mach_t *mach)
|
|
|
|
|
{
|
|
|
|
|
svga_t *svga = &mach->svga;
|
|
|
|
|
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
2024-10-26 21:32:47 +02:00
|
|
|
uint32_t ret;
|
2024-05-16 22:33:50 +02:00
|
|
|
|
|
|
|
|
cycles -= svga->monitor->mon_video_timing_read_l;
|
2024-10-26 21:32:47 +02:00
|
|
|
if (!dev->vram_512k_8514 && ((mach->accel.ext_ge_config & 0x30) == 0x00)) {
|
|
|
|
|
addr <<= 1;
|
|
|
|
|
addr &= dev->vram_mask;
|
|
|
|
|
ret = dev->vram[addr] & 0x0f;
|
|
|
|
|
ret |= (dev->vram[addr + 1] << 4);
|
|
|
|
|
ret |= (dev->vram[addr + 4] << 8);
|
|
|
|
|
ret |= (dev->vram[addr + 5] << 12);
|
|
|
|
|
ret |= (dev->vram[addr + 2] << 16);
|
|
|
|
|
ret |= (dev->vram[addr + 3] << 20);
|
|
|
|
|
ret |= (dev->vram[addr + 6] << 24);
|
|
|
|
|
ret |= (dev->vram[addr + 7] << 28);
|
|
|
|
|
} else
|
|
|
|
|
ret = *(uint32_t *) &dev->vram[addr & dev->vram_mask];
|
|
|
|
|
|
|
|
|
|
return ret;
|
2024-05-16 22:33:50 +02:00
|
|
|
}
|
|
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
static void
|
2023-06-09 23:46:54 -04:00
|
|
|
mach32_ap_writeb(uint32_t addr, uint8_t val, void *priv)
|
2023-07-14 23:38:04 +02:00
|
|
|
{
|
2023-12-06 15:00:31 +01:00
|
|
|
mach_t *mach = (mach_t *) priv;
|
|
|
|
|
svga_t *svga = &mach->svga;
|
|
|
|
|
const ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
2025-02-20 15:35:56 +01:00
|
|
|
uint8_t port_dword = (addr - mach->linear_base) & 0xfc;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (((mach->local_cntl & 0x20) || (mach->pci_cntl_reg & 0x80)) &&
|
2025-02-20 15:35:56 +01:00
|
|
|
(((addr - mach->linear_base) >= ((mach->ap_size << 20) - 0x200)) && (addr < (mach->ap_size << 20)))) {
|
|
|
|
|
if ((addr - mach->linear_base) & 0x100) {
|
2023-07-14 23:38:04 +02:00
|
|
|
mach_log("Port WORDB Write=%04x.\n", 0x02ee + (port_dword << 8));
|
|
|
|
|
mach_accel_outb(0x02ee + (addr & 1) + (port_dword << 8), val, mach);
|
|
|
|
|
} else {
|
|
|
|
|
mach_log("Port WORDB Write=%04x.\n", 0x02e8 + (port_dword << 8));
|
|
|
|
|
mach_accel_outb(0x02e8 + (addr & 1) + (port_dword << 8), val, mach);
|
|
|
|
|
}
|
|
|
|
|
} else {
|
2025-02-01 03:29:03 -05:00
|
|
|
mach_log("Linear WORDB Write=%08x, val=%02x, ON=%x, dpconfig=%04x, apsize=%08x.\n",
|
|
|
|
|
addr & dev->vram_mask, val, dev->on, mach->accel.dp_config, mach->ap_size << 20);
|
2024-10-27 23:36:11 +01:00
|
|
|
if (dev->on)
|
2025-02-20 15:35:56 +01:00
|
|
|
mach32_write_common(addr - mach->linear_base, val, 1, mach, svga);
|
2024-10-27 23:36:11 +01:00
|
|
|
else
|
2025-02-20 15:35:56 +01:00
|
|
|
svga_write_linear(addr - mach->linear_base, val, svga);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2023-06-09 23:46:54 -04:00
|
|
|
mach32_ap_writew(uint32_t addr, uint16_t val, void *priv)
|
2023-07-14 23:38:04 +02:00
|
|
|
{
|
2023-12-06 15:00:31 +01:00
|
|
|
mach_t *mach = (mach_t *) priv;
|
|
|
|
|
svga_t *svga = &mach->svga;
|
|
|
|
|
const ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
2025-02-20 15:35:56 +01:00
|
|
|
uint8_t port_dword = (addr - mach->linear_base) & 0xfc;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (((mach->local_cntl & 0x20) || (mach->pci_cntl_reg & 0x80)) &&
|
2025-02-20 15:35:56 +01:00
|
|
|
(((addr - mach->linear_base) >= ((mach->ap_size << 20) - 0x200)) && ((addr - mach->linear_base) < (mach->ap_size << 20)))) {
|
|
|
|
|
if ((addr - mach->linear_base) & 0x100) {
|
2023-07-14 23:38:04 +02:00
|
|
|
mach_log("Port WORDW Write=%04x.\n", 0x02ee + (port_dword << 8));
|
|
|
|
|
mach_accel_outw(0x02ee + (port_dword << 8), val, mach);
|
|
|
|
|
} else {
|
|
|
|
|
mach_log("Port WORDW Write=%04x.\n", 0x02e8 + (port_dword << 8));
|
|
|
|
|
mach_accel_outw(0x02e8 + (port_dword << 8), val, mach);
|
|
|
|
|
}
|
|
|
|
|
} else {
|
2025-02-01 03:29:03 -05:00
|
|
|
mach_log("Linear WORDW Write=%08x, val=%04x, ON=%x, dpconfig=%04x, apsize=%08x.\n",
|
2025-02-20 15:35:56 +01:00
|
|
|
addr - mach->linear_base, val, dev->on, mach->accel.dp_config, mach->ap_size << 20);
|
2024-10-27 23:36:11 +01:00
|
|
|
if (dev->on)
|
2025-02-20 15:35:56 +01:00
|
|
|
mach32_writew_linear(addr - mach->linear_base, val, mach);
|
2024-10-27 23:36:11 +01:00
|
|
|
else
|
2025-02-20 15:35:56 +01:00
|
|
|
svga_writew_linear(addr - mach->linear_base, val, svga);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2023-06-09 23:46:54 -04:00
|
|
|
mach32_ap_writel(uint32_t addr, uint32_t val, void *priv)
|
2023-07-14 23:38:04 +02:00
|
|
|
{
|
2023-12-06 15:00:31 +01:00
|
|
|
mach_t *mach = (mach_t *) priv;
|
|
|
|
|
svga_t *svga = &mach->svga;
|
|
|
|
|
const ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
2025-02-20 15:35:56 +01:00
|
|
|
uint8_t port_dword = (addr - mach->linear_base) & 0xfc;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (((mach->local_cntl & 0x20) || (mach->pci_cntl_reg & 0x80)) &&
|
2025-02-20 15:35:56 +01:00
|
|
|
(((addr - mach->linear_base) >= ((mach->ap_size << 20) - 0x200)) && ((addr - mach->linear_base) < (mach->ap_size << 20)))) {
|
|
|
|
|
if ((addr - mach->linear_base) & 0x100) {
|
2023-07-14 23:38:04 +02:00
|
|
|
mach_log("Port WORDL Write=%04x.\n", 0x02ee + (port_dword << 8));
|
|
|
|
|
mach_accel_outw(0x02ee + (port_dword << 8), val & 0xffff, mach);
|
|
|
|
|
mach_accel_outw(0x02ee + (port_dword << 8) + 4, val >> 16, mach);
|
|
|
|
|
} else {
|
|
|
|
|
mach_log("Port WORDL Write=%04x.\n", 0x02e8 + (port_dword << 8));
|
|
|
|
|
mach_accel_outw(0x02e8 + (port_dword << 8), val & 0xffff, mach);
|
|
|
|
|
mach_accel_outw(0x02e8 + (port_dword << 8) + 4, val >> 16, mach);
|
|
|
|
|
}
|
|
|
|
|
} else {
|
2025-02-01 03:29:03 -05:00
|
|
|
mach_log("Linear WORDL Write=%08x, val=%08x, ON=%x, dpconfig=%04x, apsize=%08x.\n",
|
2025-02-20 15:35:56 +01:00
|
|
|
addr - mach->linear_base, val, dev->on, mach->accel.dp_config, mach->ap_size << 20);
|
2024-10-27 23:36:11 +01:00
|
|
|
if (dev->on)
|
2025-02-20 15:35:56 +01:00
|
|
|
mach32_writel_linear(addr - mach->linear_base, val, mach);
|
2024-10-27 23:36:11 +01:00
|
|
|
else
|
2025-02-20 15:35:56 +01:00
|
|
|
svga_writel_linear(addr - mach->linear_base, val, svga);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static uint8_t
|
2023-06-09 23:46:54 -04:00
|
|
|
mach32_ap_readb(uint32_t addr, void *priv)
|
2023-07-14 23:38:04 +02:00
|
|
|
{
|
2023-12-06 15:00:31 +01:00
|
|
|
mach_t *mach = (mach_t *) priv;
|
|
|
|
|
svga_t *svga = &mach->svga;
|
|
|
|
|
const ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
2023-07-14 23:38:04 +02:00
|
|
|
uint8_t temp;
|
2025-02-20 15:35:56 +01:00
|
|
|
uint8_t port_dword = (addr - mach->linear_base) & 0xfc;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (((mach->local_cntl & 0x20) || (mach->pci_cntl_reg & 0x80)) &&
|
2025-02-20 15:35:56 +01:00
|
|
|
(((addr - mach->linear_base) >= ((mach->ap_size << 20) - 0x200)) && ((addr - mach->linear_base) < (mach->ap_size << 20)))) {
|
|
|
|
|
if ((addr - mach->linear_base) & 0x100)
|
2023-07-14 23:38:04 +02:00
|
|
|
temp = mach_accel_inb(0x02ee + (addr & 1) + (port_dword << 8), mach);
|
2023-12-06 15:00:31 +01:00
|
|
|
else
|
2023-07-14 23:38:04 +02:00
|
|
|
temp = mach_accel_inb(0x02e8 + (addr & 1) + (port_dword << 8), mach);
|
2023-12-06 15:00:31 +01:00
|
|
|
} else {
|
2024-10-26 21:32:47 +02:00
|
|
|
if (dev->on)
|
2025-02-20 15:35:56 +01:00
|
|
|
temp = mach32_read_common(addr - mach->linear_base, 1, mach, svga);
|
2023-12-06 15:00:31 +01:00
|
|
|
else
|
2025-02-20 15:35:56 +01:00
|
|
|
temp = svga_read_linear(addr - mach->linear_base, svga);
|
2023-12-06 15:00:31 +01:00
|
|
|
|
|
|
|
|
mach_log("Linear WORDB Read=%08x, ret=%02x, fast=%d.\n", addr, temp, svga->fast);
|
|
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
|
|
|
|
|
return temp;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static uint16_t
|
2023-06-09 23:46:54 -04:00
|
|
|
mach32_ap_readw(uint32_t addr, void *priv)
|
2023-07-14 23:38:04 +02:00
|
|
|
{
|
2023-12-06 15:00:31 +01:00
|
|
|
mach_t *mach = (mach_t *) priv;
|
|
|
|
|
svga_t *svga = &mach->svga;
|
|
|
|
|
const ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
2023-07-14 23:38:04 +02:00
|
|
|
uint16_t temp;
|
2025-02-20 15:35:56 +01:00
|
|
|
uint8_t port_dword = (addr - mach->linear_base) & 0xfc;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (((mach->local_cntl & 0x20) || (mach->pci_cntl_reg & 0x80)) &&
|
2025-02-20 15:35:56 +01:00
|
|
|
(((addr - mach->linear_base) >= ((mach->ap_size << 20) - 0x200)) && ((addr - mach->linear_base) < (mach->ap_size << 20)))) {
|
|
|
|
|
if ((addr - mach->linear_base) & 0x100)
|
2023-07-14 23:38:04 +02:00
|
|
|
temp = mach_accel_inw(0x02ee + (port_dword << 8), mach);
|
2023-12-06 15:00:31 +01:00
|
|
|
else
|
2023-07-14 23:38:04 +02:00
|
|
|
temp = mach_accel_inw(0x02e8 + (port_dword << 8), mach);
|
2023-08-15 00:11:56 +02:00
|
|
|
} else {
|
2024-10-27 23:36:11 +01:00
|
|
|
if (dev->on)
|
2025-02-20 15:35:56 +01:00
|
|
|
temp = mach32_readw_linear(addr - mach->linear_base, mach);
|
2024-10-27 23:36:11 +01:00
|
|
|
else
|
2025-02-20 15:35:56 +01:00
|
|
|
temp = svga_readw_linear(addr - mach->linear_base, svga);
|
2023-12-06 15:00:31 +01:00
|
|
|
|
|
|
|
|
mach_log("Linear WORDW Read=%08x, ret=%04x.\n", addr, temp);
|
2023-08-15 00:11:56 +02:00
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
|
|
|
|
|
return temp;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static uint32_t
|
2023-06-09 23:46:54 -04:00
|
|
|
mach32_ap_readl(uint32_t addr, void *priv)
|
2023-07-14 23:38:04 +02:00
|
|
|
{
|
2023-12-06 15:00:31 +01:00
|
|
|
mach_t *mach = (mach_t *) priv;
|
|
|
|
|
svga_t *svga = &mach->svga;
|
|
|
|
|
const ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
2023-07-14 23:38:04 +02:00
|
|
|
uint32_t temp;
|
2025-02-20 15:35:56 +01:00
|
|
|
uint8_t port_dword = (addr - mach->linear_base) & 0xfc;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (((mach->local_cntl & 0x20) || (mach->pci_cntl_reg & 0x80)) &&
|
2025-02-20 15:35:56 +01:00
|
|
|
(((addr - mach->linear_base) >= ((mach->ap_size << 20) - 0x200)) && ((addr - mach->linear_base) < (mach->ap_size << 20)))) {
|
|
|
|
|
if ((addr - mach->linear_base) & 0x100) {
|
2023-07-14 23:38:04 +02:00
|
|
|
temp = mach_accel_inw(0x02ee + (port_dword << 8), mach);
|
|
|
|
|
temp |= (mach_accel_inw(0x02ee + (port_dword << 8) + 4, mach) << 8);
|
|
|
|
|
} else {
|
|
|
|
|
temp = mach_accel_inw(0x02e8 + (port_dword << 8), mach);
|
|
|
|
|
temp |= (mach_accel_inw(0x02e8 + (port_dword << 8) + 4, mach) << 8);
|
|
|
|
|
}
|
2023-08-15 00:11:56 +02:00
|
|
|
} else {
|
2024-10-27 23:36:11 +01:00
|
|
|
if (dev->on)
|
2025-02-20 15:35:56 +01:00
|
|
|
temp = mach32_readl_linear(addr - mach->linear_base, mach);
|
2024-10-27 23:36:11 +01:00
|
|
|
else
|
2025-02-20 15:35:56 +01:00
|
|
|
temp = svga_readl_linear(addr - mach->linear_base, svga);
|
2023-12-06 15:00:31 +01:00
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
mach_log("Linear WORDL Read=%08x, ret=%08x, ON%d.\n", addr, temp, dev->on);
|
2023-08-15 00:11:56 +02:00
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
|
|
|
|
|
return temp;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2024-01-15 21:43:33 +01:00
|
|
|
mach32_updatemapping(mach_t *mach, svga_t *svga)
|
2023-07-14 23:38:04 +02:00
|
|
|
{
|
2023-10-09 20:14:03 +02:00
|
|
|
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
2023-06-09 23:46:54 -04:00
|
|
|
if (mach->pci_bus && (!(mach->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM))) {
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_log("No Mapping.\n");
|
2023-07-14 23:38:04 +02:00
|
|
|
mem_mapping_disable(&svga->mapping);
|
|
|
|
|
mem_mapping_disable(&mach->mmio_linear_mapping);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
if (mach->regs[0xbd] & 0x04) {
|
2023-07-14 23:38:04 +02:00
|
|
|
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000);
|
|
|
|
|
svga->banked_mask = 0xffff;
|
|
|
|
|
} else {
|
|
|
|
|
switch (svga->gdcreg[6] & 0x0c) {
|
|
|
|
|
case 0x0: /*128k at A0000*/
|
|
|
|
|
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000);
|
|
|
|
|
svga->banked_mask = 0xffff;
|
|
|
|
|
break;
|
|
|
|
|
case 0x4: /*64k at A0000*/
|
|
|
|
|
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
|
|
|
|
|
svga->banked_mask = 0xffff;
|
|
|
|
|
break;
|
|
|
|
|
case 0x8: /*32k at B0000*/
|
|
|
|
|
mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000);
|
|
|
|
|
svga->banked_mask = 0x7fff;
|
|
|
|
|
break;
|
|
|
|
|
case 0xC: /*32k at B8000*/
|
|
|
|
|
mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000);
|
|
|
|
|
svga->banked_mask = 0x7fff;
|
2024-11-03 04:46:32 +01:00
|
|
|
if (((dev->local & 0xff) >= 0x02) && !(dev->accel.advfunc_cntl & 0x01) && !(mach->accel.clock_sel & 0x01)) {
|
|
|
|
|
if ((svga->gdcreg[6] & 0x01) || (svga->attrregs[0x10] & 0x01)) {
|
|
|
|
|
if (svga->attrregs[0x10] & 0x40) {
|
2024-11-03 23:21:18 +01:00
|
|
|
dev->vendor_mode = 0;
|
2024-11-03 04:46:32 +01:00
|
|
|
dev->on &= ~0x01;
|
|
|
|
|
svga_recalctimings(svga);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
2023-06-09 23:46:54 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2025-02-01 03:29:03 -05:00
|
|
|
mach_log("Linear base = %08x, aperture = %04x, localcntl = %02x svgagdc = %x.\n",
|
|
|
|
|
mach->linear_base, mach->memory_aperture, mach->local_cntl, svga->gdcreg[6] & 0x0c);
|
2023-07-14 23:38:04 +02:00
|
|
|
if (mach->linear_base) {
|
|
|
|
|
if (((mach->memory_aperture & 3) == 1) && !mach->pci_bus) {
|
|
|
|
|
/*1 MB aperture*/
|
|
|
|
|
mach->ap_size = 1;
|
2024-10-26 21:32:47 +02:00
|
|
|
mach_log("Linear Enabled APSIZE=1.\n");
|
2023-07-14 23:38:04 +02:00
|
|
|
mem_mapping_set_addr(&mach->mmio_linear_mapping, mach->linear_base, mach->ap_size << 20);
|
|
|
|
|
} else {
|
|
|
|
|
/*4 MB aperture*/
|
|
|
|
|
mach->ap_size = 4;
|
2024-10-26 21:32:47 +02:00
|
|
|
mach_log("Linear Enabled APSIZE=4.\n");
|
2023-07-14 23:38:04 +02:00
|
|
|
mem_mapping_set_addr(&mach->mmio_linear_mapping, mach->linear_base, mach->ap_size << 20);
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
mach->ap_size = 4;
|
2024-10-26 21:32:47 +02:00
|
|
|
mach_log("Linear Disabled APSIZE=4.\n");
|
2023-07-14 23:38:04 +02:00
|
|
|
mem_mapping_disable(&mach->mmio_linear_mapping);
|
|
|
|
|
}
|
2024-11-02 20:50:06 +01:00
|
|
|
if ((dev->local & 0xff) >= 0x02) {
|
2024-11-03 23:21:18 +01:00
|
|
|
if (dev->on && dev->vendor_mode) {
|
2024-11-02 20:50:06 +01:00
|
|
|
mach_log("Mach32 banked mapping.\n");
|
2024-05-29 20:47:22 +02:00
|
|
|
mem_mapping_set_handler(&svga->mapping, mach32_read, mach32_readw, mach32_readl, mach32_write, mach32_writew, mach32_writel);
|
|
|
|
|
mem_mapping_set_p(&svga->mapping, mach);
|
2024-11-02 20:50:06 +01:00
|
|
|
} else {
|
|
|
|
|
mach_log("IBM compatible banked mapping.\n");
|
|
|
|
|
mem_mapping_set_handler(&svga->mapping, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel);
|
|
|
|
|
mem_mapping_set_p(&svga->mapping, svga);
|
2024-05-29 20:47:22 +02:00
|
|
|
}
|
Video, Storage and MCA changes/fixes.
1. Cirrus Logic GD54xx, Paradise/WD VGA now reset the interlace once a text mode is issued if not done automatically.
2. Paradise/WD's 15/16bpp modes using the 800x600 resolution now have the correct ma_latch, should fix most operating systems drivers using this combo.
3. More fixes (hopefully) to the accelerated pitch and rowoffset of the Trident TGUI cards (9440AGi and 96x0XGi), should fix issues with delayed displays mode changes under various operating systems (e.g.: Win3.1x).
4. Preliminary implementation of the Area Fill command of XGA, which is issued while using various painting and/or calc utilities on Win3.1x (IBM XGA updated drivers, e.g.: 2.12).
5. Preliminary (and incomplete) 4bpp XGA mode.
6. The XGA memory test for the 0xa5 using writes (used by various operating systems) no longer conflicts with DOS' XGAKIT's memory detection.
7. Small ROP fixes to both XGA and 8514/A.
8. Re-organized the mapping of the Mach32 chipset, especially when to enable the ATI mode or switching back to IBM mode, should fix LFB conflicts with various operating systems.
9. According to The OS/2 Museum, the Adaptec AHA-154xB series of SCSI cards fail the ASPI4DOS.SYS 3.36 signature check, so now make the changes accordingly.
10. Remove useless and crashy bios-less option of the Trantor T128.
11. The Image Manager 1024 card can also be used on a XT (although only if it has a V20/V30).
12. Re-organized the IBM PS/2 model 60 initialization as well as its right POS machine ID (though an update to sc.exe is still required for the POST memory amount to work normally).
2023-09-30 22:08:08 +02:00
|
|
|
} else {
|
2024-10-26 21:32:47 +02:00
|
|
|
mach_log("IBM compatible banked mapping.\n");
|
Video, Storage and MCA changes/fixes.
1. Cirrus Logic GD54xx, Paradise/WD VGA now reset the interlace once a text mode is issued if not done automatically.
2. Paradise/WD's 15/16bpp modes using the 800x600 resolution now have the correct ma_latch, should fix most operating systems drivers using this combo.
3. More fixes (hopefully) to the accelerated pitch and rowoffset of the Trident TGUI cards (9440AGi and 96x0XGi), should fix issues with delayed displays mode changes under various operating systems (e.g.: Win3.1x).
4. Preliminary implementation of the Area Fill command of XGA, which is issued while using various painting and/or calc utilities on Win3.1x (IBM XGA updated drivers, e.g.: 2.12).
5. Preliminary (and incomplete) 4bpp XGA mode.
6. The XGA memory test for the 0xa5 using writes (used by various operating systems) no longer conflicts with DOS' XGAKIT's memory detection.
7. Small ROP fixes to both XGA and 8514/A.
8. Re-organized the mapping of the Mach32 chipset, especially when to enable the ATI mode or switching back to IBM mode, should fix LFB conflicts with various operating systems.
9. According to The OS/2 Museum, the Adaptec AHA-154xB series of SCSI cards fail the ASPI4DOS.SYS 3.36 signature check, so now make the changes accordingly.
10. Remove useless and crashy bios-less option of the Trantor T128.
11. The Image Manager 1024 card can also be used on a XT (although only if it has a V20/V30).
12. Re-organized the IBM PS/2 model 60 initialization as well as its right POS machine ID (though an update to sc.exe is still required for the POST memory amount to work normally).
2023-09-30 22:08:08 +02:00
|
|
|
mem_mapping_set_handler(&svga->mapping, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel);
|
|
|
|
|
mem_mapping_set_p(&svga->mapping, svga);
|
|
|
|
|
}
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
mach32_hwcursor_draw(svga_t *svga, int displine)
|
|
|
|
|
{
|
2023-08-11 20:32:56 -04:00
|
|
|
const mach_t *mach = (mach_t *) svga->priv;
|
2023-10-09 20:14:03 +02:00
|
|
|
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
2023-07-30 18:33:29 -04:00
|
|
|
uint16_t dat;
|
|
|
|
|
int comb;
|
2024-11-02 20:50:06 +01:00
|
|
|
int offset;
|
2023-07-30 18:33:29 -04:00
|
|
|
uint32_t color0;
|
|
|
|
|
uint32_t color1;
|
2023-12-14 21:47:10 +01:00
|
|
|
uint32_t *p;
|
|
|
|
|
int x_pos;
|
|
|
|
|
int y_pos;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
2024-11-02 20:50:06 +01:00
|
|
|
offset = dev->hwcursor_latch.x - dev->hwcursor_latch.xoff;
|
|
|
|
|
|
2024-09-22 21:05:10 +02:00
|
|
|
mach_log("BPP=%d, displine=%d.\n", dev->accel_bpp, displine);
|
2023-12-06 15:00:31 +01:00
|
|
|
switch (dev->accel_bpp) {
|
2023-12-14 21:56:17 +01:00
|
|
|
default:
|
2023-12-06 15:00:31 +01:00
|
|
|
case 8:
|
|
|
|
|
color0 = dev->pallook[mach->cursor_col_0];
|
|
|
|
|
color1 = dev->pallook[mach->cursor_col_1];
|
2024-10-26 21:32:47 +02:00
|
|
|
mach_log("4/8BPP: Color0=%08x, Color1=%08x.\n", color0, color1);
|
2023-12-06 15:00:31 +01:00
|
|
|
break;
|
|
|
|
|
case 15:
|
|
|
|
|
color0 = video_15to32[((mach->ext_cur_col_0_r << 16) | (mach->ext_cur_col_0_g << 8) | mach->cursor_col_0) & 0xffff];
|
|
|
|
|
color1 = video_15to32[((mach->ext_cur_col_1_r << 16) | (mach->ext_cur_col_1_g << 8) | mach->cursor_col_1) & 0xffff];
|
|
|
|
|
break;
|
|
|
|
|
case 16:
|
|
|
|
|
color0 = video_16to32[((mach->ext_cur_col_0_r << 16) | (mach->ext_cur_col_0_g << 8) | mach->cursor_col_0) & 0xffff];
|
|
|
|
|
color1 = video_16to32[((mach->ext_cur_col_1_r << 16) | (mach->ext_cur_col_1_g << 8) | mach->cursor_col_1) & 0xffff];
|
|
|
|
|
break;
|
|
|
|
|
case 24:
|
|
|
|
|
case 32:
|
|
|
|
|
color0 = ((mach->ext_cur_col_0_r << 16) | (mach->ext_cur_col_0_g << 8) | mach->cursor_col_0);
|
|
|
|
|
color1 = ((mach->ext_cur_col_1_r << 16) | (mach->ext_cur_col_1_g << 8) | mach->cursor_col_1);
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (dev->interlace && dev->hwcursor_oddeven)
|
|
|
|
|
dev->hwcursor_latch.addr += 16;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
|
|
|
|
for (int x = 0; x < 64; x += 8) {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
dat = dev->vram[dev->hwcursor_latch.addr & dev->vram_mask] | (dev->vram[(dev->hwcursor_latch.addr + 1) & dev->vram_mask] << 8);
|
2024-10-26 21:32:47 +02:00
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
for (int xx = 0; xx < 8; xx++) {
|
|
|
|
|
comb = (dat >> (xx << 1)) & 0x03;
|
2023-12-14 21:47:10 +01:00
|
|
|
|
|
|
|
|
y_pos = displine;
|
|
|
|
|
x_pos = offset + svga->x_add;
|
|
|
|
|
p = buffer32->line[y_pos];
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (offset >= dev->hwcursor_latch.x) {
|
2023-12-14 21:47:10 +01:00
|
|
|
mach_log("COMB=%d.\n", comb);
|
2023-07-14 23:38:04 +02:00
|
|
|
switch (comb) {
|
|
|
|
|
case 0:
|
2023-12-14 21:47:10 +01:00
|
|
|
p[x_pos] = color0;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 1:
|
2023-12-14 21:47:10 +01:00
|
|
|
p[x_pos] = color1;
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 3:
|
2023-12-14 21:47:10 +01:00
|
|
|
p[x_pos] ^= 0xffffff;
|
2023-06-09 23:46:54 -04:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
offset++;
|
|
|
|
|
}
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
dev->hwcursor_latch.addr += 2;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
2024-11-02 20:50:06 +01:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (dev->interlace && !dev->hwcursor_oddeven)
|
|
|
|
|
dev->hwcursor_latch.addr += 16;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2024-01-15 21:43:33 +01:00
|
|
|
ati8514_io_set(svga_t *svga)
|
2023-07-14 23:38:04 +02:00
|
|
|
{
|
2024-11-13 22:55:16 +01:00
|
|
|
io_sethandler(0x2e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
2024-01-15 21:43:33 +01:00
|
|
|
io_sethandler(0x6e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xae8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xee8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x12e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x16e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x1ae8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x1ee8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x22e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x26e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x2ee8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x42e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x4ae8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x52e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x56e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x5ae8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x5ee8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x82e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x86e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x8ae8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x8ee8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x92e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x96e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x9ae8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x9ee8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xa2e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xa6e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xaae8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xaee8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xb2e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xb6e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xbae8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xbee8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xe2e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
|
|
|
|
|
io_sethandler(0xc2e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xc6e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xcae8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xcee8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xd2e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xd6e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xdae8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xdee8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xe6e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xeae8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xeee8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
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|
|
|
|
io_sethandler(0xf2e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
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|
|
|
|
io_sethandler(0xf6e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
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|
|
|
|
io_sethandler(0xfae8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
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|
|
|
|
io_sethandler(0xfee8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
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|
|
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|
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|
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|
|
io_sethandler(0x02ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
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|
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|
io_sethandler(0x06ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
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|
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|
io_sethandler(0x0aee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
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|
|
|
|
io_sethandler(0x0eee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
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|
|
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|
io_sethandler(0x12ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
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|
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|
io_sethandler(0x16ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
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|
io_sethandler(0x1aee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
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|
|
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|
io_sethandler(0x1eee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
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|
|
|
|
io_sethandler(0x22ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
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|
io_sethandler(0x26ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
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|
|
|
|
io_sethandler(0x2aee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
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|
|
|
|
io_sethandler(0x2eee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
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|
|
|
|
io_sethandler(0x32ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
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|
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|
|
io_sethandler(0x36ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
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|
|
|
|
io_sethandler(0x3aee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x3eee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x42ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
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|
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|
|
io_sethandler(0x46ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
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|
|
|
|
io_sethandler(0x4aee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x52ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x56ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x5aee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x5eee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x62ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x66ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x6aee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x6eee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x72ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x76ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x7aee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x7eee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x82ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x86ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x8eee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x92ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x96ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0x9aee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xa2ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
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|
|
|
|
io_sethandler(0xa6ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xaaee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xaeee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xb2ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xb6ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xbaee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xbeee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xc2ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xc6ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xcaee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xceee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xd2ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xd6ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xdaee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xdeee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xe2ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xe6ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xeeee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xf2ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xf6ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
|
|
|
|
io_sethandler(0xfeee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
|
2023-07-14 23:38:04 +02:00
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}
|
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2024-11-05 01:08:13 +01:00
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|
|
static void
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|
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|
|
mach_io_remove(mach_t *mach)
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|
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|
|
{
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|
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|
io_removehandler(0x2e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
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|
|
io_removehandler(0x6e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
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|
|
io_removehandler(0x12e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x16e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
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|
|
io_removehandler(0x1ae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
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|
|
io_removehandler(0x1ee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
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io_removehandler(0x22e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
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|
|
io_removehandler(0x26e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
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|
io_removehandler(0x2ee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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io_removehandler(0x42e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
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|
io_removehandler(0x4ae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
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io_removehandler(0x52e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
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io_removehandler(0x56e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
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io_removehandler(0x5ae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
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io_removehandler(0x5ee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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io_removehandler(0x82e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
io_removehandler(0x86e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x8ae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
|
|
|
io_removehandler(0x8ee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
|
|
|
io_removehandler(0x92e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x96e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
|
|
|
io_removehandler(0x9ae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x9ee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
|
|
|
io_removehandler(0xa2e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
|
|
|
io_removehandler(0xa6e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
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|
io_removehandler(0xaae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
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|
io_removehandler(0xaee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
|
|
|
io_removehandler(0xb2e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
|
|
|
io_removehandler(0xb6e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
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|
io_removehandler(0xbae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
|
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|
io_removehandler(0xbee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
|
|
|
io_removehandler(0xe2e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
|
|
|
|
|
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|
|
io_removehandler(0xc2e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
|
|
|
io_removehandler(0xc6e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
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|
|
io_removehandler(0xcae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
|
|
|
io_removehandler(0xcee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xd2e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xd6e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xdae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xdee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xe6e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xeae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xeee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xf2e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xf6e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xfae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xfee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
|
|
|
|
|
io_removehandler(0x02ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x06ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x0aee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x0eee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x12ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x16ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x1aee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x1eee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x22ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x26ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x2aee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x2eee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x32ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x36ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x3aee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x3eee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x42ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x46ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x4aee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x52ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x56ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x5aee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x5eee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x62ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x66ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x6aee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x6eee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x72ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x76ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x7aee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x7eee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x82ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x86ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x8eee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x92ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x96ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0x9aee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xa2ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xa6ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xaaee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xaeee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xb2ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xb6ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xbaee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xbeee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xc2ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xc6ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xcaee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xceee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xd2ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xd6ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xdaee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xdeee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xe2ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xe6ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xeeee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xf2ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xf6ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xfaee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_removehandler(0xfeee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
}
|
|
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
static void
|
|
|
|
|
mach_io_set(mach_t *mach)
|
|
|
|
|
{
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
io_sethandler(0x2e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x6e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
|
|
|
io_sethandler(0xee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x12e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x16e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
|
|
|
io_sethandler(0x1ae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x1ee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
|
|
|
io_sethandler(0x22e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
|
|
|
io_sethandler(0x26e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
|
|
|
io_sethandler(0x2ee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
|
|
|
io_sethandler(0x42e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
|
|
|
io_sethandler(0x4ae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
|
|
|
io_sethandler(0x52e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x56e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
|
|
|
io_sethandler(0x5ae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
|
|
|
io_sethandler(0x5ee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x82e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
|
|
|
io_sethandler(0x86e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
|
|
|
io_sethandler(0x8ae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
|
|
|
io_sethandler(0x8ee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x92e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x96e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x9ae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x9ee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xa2e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xa6e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xaae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xaee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xb2e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xb6e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xbae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xbee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xe2e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
|
|
|
|
|
io_sethandler(0xc2e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xc6e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xcae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xcee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xd2e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xd6e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xdae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xdee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xe6e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xeae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xeee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xf2e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xf6e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xfae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xfee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
|
|
|
|
|
io_sethandler(0x02ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x06ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x0aee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x0eee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x12ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x16ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x1aee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x1eee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x22ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x26ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x2aee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x2eee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
|
|
|
io_sethandler(0x32ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x36ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x3aee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x3eee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
|
|
|
io_sethandler(0x42ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x46ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x4aee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
|
|
|
io_sethandler(0x52ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x56ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x5aee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
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|
|
|
|
io_sethandler(0x5eee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x62ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x66ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x6aee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x6eee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x72ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x76ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x7aee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x7eee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x82ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
2023-12-28 02:01:45 +01:00
|
|
|
io_sethandler(0x86ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
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|
|
io_sethandler(0x8eee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x92ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x96ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0x9aee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xa2ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xa6ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xaaee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xaeee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xb2ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xb6ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xbaee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xbeee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xc2ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xc6ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xcaee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xceee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xd2ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xd6ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xdaee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xdeee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xe2ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xe6ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xeeee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
io_sethandler(0xf2ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
2023-12-28 02:01:45 +01:00
|
|
|
io_sethandler(0xf6ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
2024-05-29 20:47:22 +02:00
|
|
|
io_sethandler(0xfaee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
io_sethandler(0xfeee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static uint8_t
|
2023-08-11 20:32:56 -04:00
|
|
|
mach_mca_read(int port, void *priv)
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
{
|
2023-08-11 20:32:56 -04:00
|
|
|
const mach_t *mach = (mach_t *) priv;
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
mach_log("[%04X]: MCA read port = %x, val = %02x.\n", CS, port & 7, mach->pos_regs[port & 7]);
|
|
|
|
|
return mach->pos_regs[port & 7];
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
mach_mca_write(int port, uint8_t val, void *priv)
|
|
|
|
|
{
|
2023-08-11 20:32:56 -04:00
|
|
|
mach_t *mach = (mach_t *) priv;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
|
|
|
|
|
if (port < 0x102)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
mach->pos_regs[port & 7] = val;
|
2025-02-01 03:29:03 -05:00
|
|
|
mach_log("[%04X]: MCA write port = %x, val = %02x, biosaddr = %05x.\n",
|
|
|
|
|
CS, port & 7, mach->pos_regs[port & 7], (((mach->pos_regs[3] & 0x3e) << 0x0c) >> 1) + 0xc0000);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
mem_mapping_disable(&mach->bios_rom.mapping);
|
|
|
|
|
mem_mapping_disable(&mach->bios_rom2.mapping);
|
|
|
|
|
if (mach->pos_regs[2] & 0x01) {
|
|
|
|
|
mem_mapping_enable(&mach->bios_rom.mapping);
|
|
|
|
|
mem_mapping_enable(&mach->bios_rom2.mapping);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static uint8_t
|
2023-08-11 20:32:56 -04:00
|
|
|
mach_mca_feedb(void *priv)
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
{
|
2023-08-11 20:32:56 -04:00
|
|
|
const mach_t *mach = (mach_t *) priv;
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
mach_log("FeedB = %x.\n", mach->pos_regs[2] & 0x01);
|
|
|
|
|
return mach->pos_regs[2] & 0x01;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2023-08-11 20:32:56 -04:00
|
|
|
mach_mca_reset(void *priv)
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
{
|
2023-08-11 20:32:56 -04:00
|
|
|
mach_t *mach = (mach_t *) priv;
|
2023-08-15 00:11:56 +02:00
|
|
|
svga_t *svga = &mach->svga;
|
2023-10-09 20:14:03 +02:00
|
|
|
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
|
|
|
|
|
mach_log("MCA reset.\n");
|
2024-10-26 21:32:47 +02:00
|
|
|
dev->on = 0;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
mach_mca_write(0x102, 0, mach);
|
2025-01-26 14:25:35 +01:00
|
|
|
svga_set_poll(svga);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
2024-01-15 21:43:33 +01:00
|
|
|
uint8_t
|
|
|
|
|
ati8514_mca_read(int port, void *priv)
|
|
|
|
|
{
|
|
|
|
|
const svga_t *svga = (svga_t *) priv;
|
|
|
|
|
const ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
|
|
|
|
|
|
|
|
|
return (dev->pos_regs[port & 7]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
ati8514_mca_write(int port, uint8_t val, void *priv)
|
|
|
|
|
{
|
|
|
|
|
svga_t *svga = (svga_t *) priv;
|
|
|
|
|
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
|
|
|
|
|
|
|
|
|
if (port < 0x102)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
dev->pos_regs[port & 7] = val;
|
2025-02-01 03:29:03 -05:00
|
|
|
mach_log("[%04X]: MCA write port = %x, val = %02x, biosaddr = %05x.\n",
|
|
|
|
|
CS, port & 7, dev->pos_regs[port & 7], (((dev->pos_regs[3] & 0x3e) << 0x0c) >> 1) + 0xc0000);
|
2024-01-15 21:43:33 +01:00
|
|
|
mem_mapping_disable(&dev->bios_rom.mapping);
|
|
|
|
|
|
|
|
|
|
if (dev->pos_regs[2] & 0x01)
|
|
|
|
|
mem_mapping_enable(&dev->bios_rom.mapping);
|
|
|
|
|
}
|
2024-05-29 20:47:22 +02:00
|
|
|
|
|
|
|
|
void
|
|
|
|
|
ati8514_pos_write(uint16_t port, uint8_t val, void *priv)
|
|
|
|
|
{
|
|
|
|
|
ati8514_mca_write(port, val, priv);
|
|
|
|
|
}
|
2024-01-15 21:43:33 +01:00
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
static uint8_t
|
2023-06-09 23:46:54 -04:00
|
|
|
mach32_pci_read(UNUSED(int func), int addr, void *priv)
|
2023-07-14 23:38:04 +02:00
|
|
|
{
|
2023-07-30 18:33:29 -04:00
|
|
|
const mach_t *mach = (mach_t *) priv;
|
|
|
|
|
uint8_t ret = 0x00;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if ((addr >= 0x30) && (addr <= 0x33) && !mach->has_bios)
|
|
|
|
|
return ret;
|
|
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
switch (addr) {
|
|
|
|
|
case 0x00:
|
|
|
|
|
ret = 0x02; /*ATI*/
|
|
|
|
|
break;
|
|
|
|
|
case 0x01:
|
|
|
|
|
ret = 0x10;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x02:
|
|
|
|
|
ret = 0x58;
|
|
|
|
|
break;
|
|
|
|
|
case 0x03:
|
|
|
|
|
ret = 0x41;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case PCI_REG_COMMAND:
|
|
|
|
|
ret = mach->pci_regs[PCI_REG_COMMAND] | 0x80; /*Respond to IO and memory accesses*/
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x07:
|
|
|
|
|
ret = 0x01; /*Medium DEVSEL timing*/
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x0a:
|
|
|
|
|
ret = 0x00; /*Supports VGA interface*/
|
|
|
|
|
break;
|
|
|
|
|
case 0x0b:
|
|
|
|
|
ret = 0x03;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x10:
|
|
|
|
|
ret = 0x00; /*Linear frame buffer address*/
|
|
|
|
|
break;
|
|
|
|
|
case 0x11:
|
|
|
|
|
ret = 0x00;
|
|
|
|
|
break;
|
|
|
|
|
case 0x12:
|
|
|
|
|
ret = mach->linear_base >> 16;
|
|
|
|
|
break;
|
|
|
|
|
case 0x13:
|
|
|
|
|
ret = mach->linear_base >> 24;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x30:
|
|
|
|
|
ret = (mach->pci_regs[0x30] & 0x01); /*BIOS ROM address*/
|
|
|
|
|
break;
|
|
|
|
|
case 0x31:
|
|
|
|
|
ret = 0x00;
|
|
|
|
|
break;
|
|
|
|
|
case 0x32:
|
|
|
|
|
ret = mach->pci_regs[0x32];
|
|
|
|
|
break;
|
|
|
|
|
case 0x33:
|
|
|
|
|
ret = mach->pci_regs[0x33];
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x3c:
|
|
|
|
|
ret = mach->int_line;
|
|
|
|
|
break;
|
|
|
|
|
case 0x3d:
|
|
|
|
|
ret = PCI_INTA;
|
|
|
|
|
break;
|
2023-06-09 23:46:54 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2023-06-09 23:46:54 -04:00
|
|
|
mach32_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
|
2023-07-14 23:38:04 +02:00
|
|
|
{
|
2023-06-09 23:46:54 -04:00
|
|
|
mach_t *mach = (mach_t *) priv;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if ((addr >= 0x30) && (addr <= 0x33) && !mach->has_bios)
|
|
|
|
|
return;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
|
|
|
|
switch (addr) {
|
|
|
|
|
case PCI_REG_COMMAND:
|
|
|
|
|
mach->pci_regs[PCI_REG_COMMAND] = val & 0x27;
|
|
|
|
|
if (val & PCI_COMMAND_IO) {
|
2024-11-05 01:08:13 +01:00
|
|
|
mach_log("Remove and set handlers.\n");
|
|
|
|
|
io_removehandler(0x01ce, 2, mach_in, NULL, NULL, mach_out, NULL, NULL, mach);
|
2023-10-11 18:46:15 +02:00
|
|
|
io_removehandler(0x02ea, 4, mach_in, NULL, NULL, mach_out, NULL, NULL, mach);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
io_removehandler(0x03c0, 32, mach_in, NULL, NULL, mach_out, NULL, NULL, mach);
|
2024-11-05 01:08:13 +01:00
|
|
|
mach_io_remove(mach);
|
|
|
|
|
io_sethandler(0x01ce, 2, mach_in, NULL, NULL, mach_out, NULL, NULL, mach);
|
2023-10-11 18:46:15 +02:00
|
|
|
io_sethandler(0x02ea, 4, mach_in, NULL, NULL, mach_out, NULL, NULL, mach);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
io_sethandler(0x03c0, 32, mach_in, NULL, NULL, mach_out, NULL, NULL, mach);
|
2024-11-05 01:08:13 +01:00
|
|
|
mach_io_set(mach);
|
2023-10-11 18:46:15 +02:00
|
|
|
} else {
|
2024-11-05 01:08:13 +01:00
|
|
|
mach_log("Remove handlers.\n");
|
|
|
|
|
io_removehandler(0x01ce, 2, mach_in, NULL, NULL, mach_out, NULL, NULL, mach);
|
2023-10-11 18:46:15 +02:00
|
|
|
io_removehandler(0x02ea, 4, mach_in, NULL, NULL, mach_out, NULL, NULL, mach);
|
2024-01-15 21:43:33 +01:00
|
|
|
io_removehandler(0x03c0, 32, mach_in, NULL, NULL, mach_out, NULL, NULL, mach);
|
2024-11-05 01:08:13 +01:00
|
|
|
mach_io_remove(mach);
|
2023-10-11 18:46:15 +02:00
|
|
|
}
|
2024-01-15 21:43:33 +01:00
|
|
|
mach32_updatemapping(mach, &mach->svga);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x12:
|
|
|
|
|
mach->linear_base = (mach->linear_base & 0xff000000) | ((val & 0xc0) << 16);
|
2024-01-15 21:43:33 +01:00
|
|
|
mach32_updatemapping(mach, &mach->svga);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
case 0x13:
|
|
|
|
|
mach->linear_base = (mach->linear_base & 0xc00000) | (val << 24);
|
2024-01-15 21:43:33 +01:00
|
|
|
mach32_updatemapping(mach, &mach->svga);
|
2023-07-14 23:38:04 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x30:
|
|
|
|
|
case 0x32:
|
|
|
|
|
case 0x33:
|
|
|
|
|
mach->pci_regs[addr] = val;
|
|
|
|
|
if (mach->pci_regs[0x30] & 0x01) {
|
|
|
|
|
uint32_t bios_addr = (mach->pci_regs[0x32] << 16) | (mach->pci_regs[0x33] << 24);
|
|
|
|
|
mach_log("Mach32 bios_rom enabled at %08x\n", bios_addr);
|
|
|
|
|
mem_mapping_set_addr(&mach->bios_rom.mapping, bios_addr, 0x8000);
|
|
|
|
|
} else {
|
|
|
|
|
mach_log("Mach32 bios_rom disabled\n");
|
|
|
|
|
mem_mapping_disable(&mach->bios_rom.mapping);
|
|
|
|
|
}
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
case 0x3c:
|
|
|
|
|
mach->int_line = val;
|
|
|
|
|
break;
|
2023-06-09 23:46:54 -04:00
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void *
|
|
|
|
|
mach8_init(const device_t *info)
|
|
|
|
|
{
|
2023-07-30 18:33:29 -04:00
|
|
|
mach_t *mach;
|
|
|
|
|
svga_t *svga;
|
2023-07-14 23:38:04 +02:00
|
|
|
ibm8514_t *dev;
|
|
|
|
|
|
2023-10-09 20:14:03 +02:00
|
|
|
mach = calloc(1, sizeof(mach_t));
|
2023-07-14 23:38:04 +02:00
|
|
|
|
2023-10-09 20:14:03 +02:00
|
|
|
svga = &mach->svga;
|
|
|
|
|
dev = (ibm8514_t *) calloc(1, sizeof(ibm8514_t));
|
|
|
|
|
|
|
|
|
|
svga->dev8514 = dev;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
|
|
|
|
mach->pci_bus = !!(info->flags & DEVICE_PCI);
|
|
|
|
|
mach->vlb_bus = !!(info->flags & DEVICE_VLB);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
mach->mca_bus = !!(info->flags & DEVICE_MCA);
|
|
|
|
|
dev->type = info->flags;
|
|
|
|
|
dev->local = info->local & 0xff;
|
|
|
|
|
mach->has_bios = !(info->local & 0xff00);
|
|
|
|
|
mach->ramdac_type = mach->pci_bus ? device_get_config_int("ramdac") : 1;
|
2024-10-26 21:32:47 +02:00
|
|
|
dev->vram_amount = device_get_config_int("memory");
|
|
|
|
|
dev->vram_512k_8514 = dev->vram_amount == 512;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
|
2023-12-06 15:00:31 +01:00
|
|
|
if ((dev->local & 0xff) >= 0x02) {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (mach->pci_bus) {
|
|
|
|
|
if (mach->has_bios) {
|
|
|
|
|
rom_init(&mach->bios_rom,
|
|
|
|
|
BIOS_MACH32_PCI_ROM_PATH,
|
|
|
|
|
0xc0000, 0x8000, 0x7fff,
|
|
|
|
|
0, MEM_MAPPING_EXTERNAL);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (mach->vlb_bus)
|
2023-07-14 23:38:04 +02:00
|
|
|
rom_init(&mach->bios_rom,
|
|
|
|
|
BIOS_MACH32_VLB_ROM_PATH,
|
|
|
|
|
0xc0000, 0x8000, 0x7fff,
|
|
|
|
|
0, MEM_MAPPING_EXTERNAL);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
else if (mach->mca_bus) {
|
2023-07-14 23:38:04 +02:00
|
|
|
rom_init(&mach->bios_rom,
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
BIOS_MACH32_MCA_ROM_PATH,
|
2023-07-14 23:38:04 +02:00
|
|
|
0xc0000, 0x8000, 0x7fff,
|
|
|
|
|
0, MEM_MAPPING_EXTERNAL);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
rom_init(&mach->bios_rom2,
|
|
|
|
|
BIOS_MACH32_MCA_ROM_PATH,
|
|
|
|
|
0xc8000, 0x1000, 0x0fff,
|
|
|
|
|
0x8000, MEM_MAPPING_EXTERNAL);
|
|
|
|
|
} else {
|
2023-07-14 23:38:04 +02:00
|
|
|
rom_init(&mach->bios_rom,
|
|
|
|
|
BIOS_MACH32_ISA_ROM_PATH,
|
|
|
|
|
0xc0000, 0x8000, 0x7fff,
|
|
|
|
|
0, MEM_MAPPING_EXTERNAL);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
}
|
2024-01-15 21:43:33 +01:00
|
|
|
} else
|
2023-07-14 23:38:04 +02:00
|
|
|
rom_init(&mach->bios_rom,
|
2024-01-15 21:43:33 +01:00
|
|
|
BIOS_MACH8_VGA_ROM_PATH,
|
2023-07-14 23:38:04 +02:00
|
|
|
0xc0000, 0x8000, 0x7fff,
|
|
|
|
|
0, MEM_MAPPING_EXTERNAL);
|
|
|
|
|
|
2023-12-06 15:00:31 +01:00
|
|
|
if ((dev->local & 0xff) >= 0x02) {
|
2024-10-26 21:32:47 +02:00
|
|
|
svga_init(info, svga, mach, dev->vram_amount << 10, /*default: 2MB for Mach32*/
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
mach_recalctimings,
|
|
|
|
|
mach_in, mach_out,
|
|
|
|
|
mach32_hwcursor_draw,
|
|
|
|
|
NULL);
|
2024-10-26 21:32:47 +02:00
|
|
|
dev->vram_size = dev->vram_amount << 10;
|
2023-08-15 00:11:56 +02:00
|
|
|
dev->vram = calloc(dev->vram_size, 1);
|
2024-07-08 21:21:06 +02:00
|
|
|
dev->changedvram = calloc((dev->vram_size >> 12) + 1, 1);
|
2023-08-15 00:11:56 +02:00
|
|
|
dev->vram_mask = dev->vram_size - 1;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
dev->hwcursor.cur_ysize = 64;
|
|
|
|
|
mach->config1 = 0x20;
|
|
|
|
|
if (mach->pci_bus && !mach->ramdac_type)
|
|
|
|
|
svga->ramdac = device_add(&ati68860_ramdac_device);
|
|
|
|
|
else
|
|
|
|
|
svga->ramdac = device_add(&ati68875_ramdac_device);
|
2023-07-14 23:38:04 +02:00
|
|
|
if (mach->vlb_bus) {
|
|
|
|
|
video_inform(VIDEO_FLAG_TYPE_8514, &timing_mach32_vlb);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (!is486)
|
|
|
|
|
mach->config1 |= 0x0a;
|
|
|
|
|
else
|
|
|
|
|
mach->config1 |= 0x0c;
|
|
|
|
|
mach->config1 |= 0x0400;
|
2024-09-22 21:05:10 +02:00
|
|
|
svga->clock_gen = device_add(&ati18811_1_device);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
} else if (mach->mca_bus) {
|
|
|
|
|
video_inform(VIDEO_FLAG_TYPE_8514, &timing_mach32_mca);
|
|
|
|
|
if (is286 && !is386)
|
|
|
|
|
mach->config1 |= 0x04;
|
|
|
|
|
else
|
|
|
|
|
mach->config1 |= 0x06;
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->config1 |= 0x0400;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
svga->clock_gen = device_add(&ati18811_1_device);
|
2023-07-14 23:38:04 +02:00
|
|
|
} else if (mach->pci_bus) {
|
|
|
|
|
video_inform(VIDEO_FLAG_TYPE_8514, &timing_mach32_pci);
|
|
|
|
|
mach->config1 |= 0x0e;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (mach->ramdac_type)
|
|
|
|
|
mach->config1 |= 0x0400;
|
|
|
|
|
else
|
|
|
|
|
mach->config1 |= 0x0a00;
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->config2 |= 0x2000;
|
2024-09-22 21:05:10 +02:00
|
|
|
svga->clock_gen = device_add(&ati18811_1_device);
|
2023-07-14 23:38:04 +02:00
|
|
|
} else {
|
|
|
|
|
video_inform(VIDEO_FLAG_TYPE_8514, &timing_gfxultra_isa);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
mach->config1 |= 0x0400;
|
2024-09-22 21:05:10 +02:00
|
|
|
svga->clock_gen = device_add(&ati18811_1_device);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
mem_mapping_add(&mach->mmio_linear_mapping, 0, 0, mach32_ap_readb, mach32_ap_readw, mach32_ap_readl, mach32_ap_writeb, mach32_ap_writew, mach32_ap_writel, NULL, MEM_MAPPING_EXTERNAL, mach);
|
|
|
|
|
mem_mapping_disable(&mach->mmio_linear_mapping);
|
|
|
|
|
} else {
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
svga_init(info, svga, mach, (512 << 10), /*default: 512kB VGA for 28800-6 + 1MB for Mach8*/
|
|
|
|
|
mach_recalctimings,
|
|
|
|
|
mach_in, mach_out,
|
|
|
|
|
NULL,
|
|
|
|
|
NULL);
|
2024-10-26 21:32:47 +02:00
|
|
|
dev->vram_size = (dev->vram_amount << 10);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
dev->vram = calloc(dev->vram_size, 1);
|
2024-07-08 21:21:06 +02:00
|
|
|
dev->changedvram = calloc((dev->vram_size >> 12) + 1, 1);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
dev->vram_mask = dev->vram_size - 1;
|
2023-07-14 23:38:04 +02:00
|
|
|
video_inform(VIDEO_FLAG_TYPE_8514, &timing_gfxultra_isa);
|
2024-10-26 21:32:47 +02:00
|
|
|
mach->config1 = 0x01 | 0x02 | 0x08 | 0x80;
|
|
|
|
|
if (dev->vram_amount >= 1024)
|
|
|
|
|
mach->config1 |= 0x20;
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
mach->config2 = 0x02;
|
2024-09-22 21:05:10 +02:00
|
|
|
svga->clock_gen = device_add(&ati18811_0_device);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
2024-05-29 20:47:22 +02:00
|
|
|
dev->bpp = 0;
|
|
|
|
|
svga->getclock = ics2494_getclock;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
dev->on = 0;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
dev->ext_pitch = 1024;
|
|
|
|
|
dev->ext_crt_pitch = 0x80;
|
2023-08-15 00:11:56 +02:00
|
|
|
dev->accel_bpp = 8;
|
2023-07-14 23:38:04 +02:00
|
|
|
svga->force_old_addr = 1;
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
svga->miscout = 1;
|
|
|
|
|
svga->bpp = 8;
|
|
|
|
|
svga->packed_chain4 = 1;
|
|
|
|
|
dev->rowoffset = 0x80;
|
|
|
|
|
io_sethandler(0x01ce, 2, mach_in, NULL, NULL, mach_out, NULL, NULL, mach);
|
|
|
|
|
io_sethandler(0x03c0, 32, mach_in, NULL, NULL, mach_out, NULL, NULL, mach);
|
|
|
|
|
io_sethandler(0x02ea, 4, mach_in, NULL, NULL, mach_out, NULL, NULL, mach);
|
2023-07-14 23:38:04 +02:00
|
|
|
mach_io_set(mach);
|
2024-11-13 22:55:16 +01:00
|
|
|
mach->accel.cmd_type = -2;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
2023-12-06 15:00:31 +01:00
|
|
|
if ((dev->local & 0xff) >= 0x02) {
|
2023-07-30 18:33:29 -04:00
|
|
|
svga->decode_mask = (4 << 20) - 1;
|
|
|
|
|
mach->cursor_col_1 = 0xff;
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->ext_cur_col_1_r = 0xff;
|
|
|
|
|
mach->ext_cur_col_1_g = 0xff;
|
|
|
|
|
if (mach->vlb_bus)
|
|
|
|
|
ati_eeprom_load(&mach->eeprom, "mach32_vlb.nvr", 1);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
else if (mach->mca_bus) {
|
|
|
|
|
ati_eeprom_load(&mach->eeprom, "mach32_mca.nvr", 1);
|
2023-07-14 23:38:04 +02:00
|
|
|
mem_mapping_disable(&mach->bios_rom.mapping);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
mem_mapping_disable(&mach->bios_rom2.mapping);
|
|
|
|
|
mach->pos_regs[0] = 0x89;
|
|
|
|
|
mach->pos_regs[1] = 0x80;
|
|
|
|
|
mca_add(mach_mca_read, mach_mca_write, mach_mca_feedb, mach_mca_reset, mach);
|
|
|
|
|
} else if (mach->pci_bus) {
|
|
|
|
|
ati_eeprom_load(&mach->eeprom, "mach32_pci.nvr", 1);
|
2023-08-11 20:32:56 -04:00
|
|
|
if (mach->has_bios) {
|
|
|
|
|
mem_mapping_disable(&mach->bios_rom.mapping);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
pci_add_card(PCI_ADD_NORMAL, mach32_pci_read, mach32_pci_write, mach, &mach->pci_slot);
|
2023-08-11 20:32:56 -04:00
|
|
|
} else
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
pci_add_card(PCI_ADD_VIDEO, mach32_pci_read, mach32_pci_write, mach, &mach->pci_slot);
|
2024-01-15 21:43:33 +01:00
|
|
|
|
2024-11-13 22:55:16 +01:00
|
|
|
mach->pci_regs[PCI_REG_COMMAND] = 0x87;
|
2023-07-14 23:38:04 +02:00
|
|
|
mach->pci_regs[0x30] = 0x00;
|
|
|
|
|
mach->pci_regs[0x32] = 0x0c;
|
|
|
|
|
mach->pci_regs[0x33] = 0x00;
|
|
|
|
|
} else
|
|
|
|
|
ati_eeprom_load(&mach->eeprom, "mach32.nvr", 1);
|
2024-01-15 21:43:33 +01:00
|
|
|
} else
|
2024-11-13 22:55:16 +01:00
|
|
|
ati_eeprom_load_mach8_vga(&mach->eeprom, "mach8.nvr");
|
2023-07-14 23:38:04 +02:00
|
|
|
|
2023-06-09 23:46:54 -04:00
|
|
|
return mach;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
2024-01-15 21:43:33 +01:00
|
|
|
void
|
|
|
|
|
ati8514_init(svga_t *svga, void *ext8514, void *dev8514)
|
|
|
|
|
{
|
2024-05-29 20:47:22 +02:00
|
|
|
mach_t *mach = (mach_t *) ext8514;
|
|
|
|
|
ibm8514_t *dev = (ibm8514_t *) dev8514;
|
2024-01-15 21:43:33 +01:00
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
dev->on = 0;
|
2024-01-15 21:43:33 +01:00
|
|
|
dev->ext_pitch = 1024;
|
|
|
|
|
dev->ext_crt_pitch = 0x80;
|
|
|
|
|
dev->accel_bpp = 8;
|
|
|
|
|
dev->rowoffset = 0x80;
|
2024-11-02 20:50:06 +01:00
|
|
|
dev->hdisp = 1024;
|
|
|
|
|
dev->vdisp = 768;
|
2024-01-15 21:43:33 +01:00
|
|
|
|
|
|
|
|
io_sethandler(0x02ea, 4, ati8514_in, NULL, NULL, ati8514_out, NULL, NULL, svga);
|
|
|
|
|
ati8514_io_set(svga);
|
|
|
|
|
mach->mca_bus = !!(dev->type & DEVICE_MCA);
|
|
|
|
|
|
2024-11-13 22:55:16 +01:00
|
|
|
mach->config1 = 0x02 | 0x08 | 0x80;
|
2024-11-02 20:50:06 +01:00
|
|
|
|
2024-01-15 21:43:33 +01:00
|
|
|
if (mach->mca_bus)
|
2024-11-02 20:50:06 +01:00
|
|
|
mach->config1 |= 0x04;
|
2024-10-26 21:32:47 +02:00
|
|
|
|
|
|
|
|
if (dev->vram_amount >= 1024)
|
|
|
|
|
mach->config1 |= 0x20;
|
2024-01-15 21:43:33 +01:00
|
|
|
|
2025-02-01 22:19:55 +01:00
|
|
|
mach->config2 = 0x01 | 0x02;
|
2024-01-15 21:43:33 +01:00
|
|
|
}
|
|
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
static int
|
2024-01-15 21:43:33 +01:00
|
|
|
mach8_vga_available(void)
|
2023-07-14 23:38:04 +02:00
|
|
|
{
|
2024-01-15 21:43:33 +01:00
|
|
|
return rom_present(BIOS_MACH8_VGA_ROM_PATH);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
mach32_isa_available(void)
|
|
|
|
|
{
|
|
|
|
|
return rom_present(BIOS_MACH32_ISA_ROM_PATH);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
mach32_vlb_available(void)
|
|
|
|
|
{
|
|
|
|
|
return rom_present(BIOS_MACH32_VLB_ROM_PATH);
|
|
|
|
|
}
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
static int
|
|
|
|
|
mach32_mca_available(void)
|
|
|
|
|
{
|
|
|
|
|
return rom_present(BIOS_MACH32_MCA_ROM_PATH);
|
|
|
|
|
}
|
|
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
static int
|
|
|
|
|
mach32_pci_available(void)
|
|
|
|
|
{
|
|
|
|
|
return rom_present(BIOS_MACH32_PCI_ROM_PATH);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2023-06-09 23:46:54 -04:00
|
|
|
mach_close(void *priv)
|
2023-07-14 23:38:04 +02:00
|
|
|
{
|
2023-07-30 18:33:29 -04:00
|
|
|
mach_t *mach = (mach_t *) priv;
|
|
|
|
|
svga_t *svga = &mach->svga;
|
2023-10-09 20:14:03 +02:00
|
|
|
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
|
2023-07-14 23:38:04 +02:00
|
|
|
|
2023-08-15 00:11:56 +02:00
|
|
|
if (dev) {
|
2023-07-14 23:38:04 +02:00
|
|
|
free(dev->vram);
|
|
|
|
|
free(dev->changedvram);
|
2023-10-09 20:14:03 +02:00
|
|
|
|
|
|
|
|
free(dev);
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
svga_close(svga);
|
|
|
|
|
free(mach);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2023-06-09 23:46:54 -04:00
|
|
|
mach_speed_changed(void *priv)
|
2023-07-14 23:38:04 +02:00
|
|
|
{
|
2023-06-09 23:46:54 -04:00
|
|
|
mach_t *mach = (mach_t *) priv;
|
2023-07-14 23:38:04 +02:00
|
|
|
svga_t *svga = &mach->svga;
|
|
|
|
|
|
|
|
|
|
svga_recalctimings(svga);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
2023-06-09 23:46:54 -04:00
|
|
|
mach_force_redraw(void *priv)
|
2023-07-14 23:38:04 +02:00
|
|
|
{
|
2023-06-09 23:46:54 -04:00
|
|
|
mach_t *mach = (mach_t *) priv;
|
2023-07-14 23:38:04 +02:00
|
|
|
svga_t *svga = &mach->svga;
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
svga->fullchange = svga->monitor->mon_changeframecount;
|
2023-07-14 23:38:04 +02:00
|
|
|
}
|
|
|
|
|
|
2024-10-26 21:32:47 +02:00
|
|
|
// clang-format off
|
|
|
|
|
static const device_config_t mach8_config[] = {
|
|
|
|
|
{
|
2025-02-03 20:00:58 -05:00
|
|
|
.name = "memory",
|
|
|
|
|
.description = "Memory size",
|
|
|
|
|
.type = CONFIG_SELECTION,
|
|
|
|
|
.default_string = NULL,
|
|
|
|
|
.default_int = 1024,
|
|
|
|
|
.file_filter = NULL,
|
|
|
|
|
.spinner = { 0 },
|
|
|
|
|
.selection = {
|
|
|
|
|
{ .description = "512 KB", .value = 512 },
|
|
|
|
|
{ .description = "1 MB", .value = 1024 },
|
|
|
|
|
{ .description = "" }
|
|
|
|
|
},
|
|
|
|
|
.bios = { { 0 } }
|
2024-10-26 21:32:47 +02:00
|
|
|
},
|
2025-01-07 01:12:42 -05:00
|
|
|
{ .name = "", .description = "", .type = CONFIG_END }
|
2024-10-26 21:32:47 +02:00
|
|
|
};
|
|
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
static const device_config_t mach32_config[] = {
|
|
|
|
|
{
|
2025-02-03 20:00:58 -05:00
|
|
|
.name = "memory",
|
|
|
|
|
.description = "Memory size",
|
|
|
|
|
.type = CONFIG_SELECTION,
|
|
|
|
|
.default_string = NULL,
|
|
|
|
|
.default_int = 2048,
|
|
|
|
|
.file_filter = NULL,
|
|
|
|
|
.spinner = { 0 },
|
|
|
|
|
.selection = {
|
|
|
|
|
{ .description = "512 KB", .value = 512 },
|
|
|
|
|
{ .description = "1 MB", .value = 1024 },
|
|
|
|
|
{ .description = "2 MB", .value = 2048 },
|
|
|
|
|
{ .description = "4 MB", .value = 4096 },
|
|
|
|
|
{ .description = "" }
|
|
|
|
|
},
|
|
|
|
|
.bios = { { 0 } }
|
2023-07-14 23:38:04 +02:00
|
|
|
},
|
2025-01-07 01:12:42 -05:00
|
|
|
{ .name = "", .description = "", .type = CONFIG_END }
|
2023-07-14 23:38:04 +02:00
|
|
|
};
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
static const device_config_t mach32_pci_config[] = {
|
|
|
|
|
{
|
2025-02-03 20:00:58 -05:00
|
|
|
.name = "ramdac",
|
|
|
|
|
.description = "RAMDAC type",
|
|
|
|
|
.type = CONFIG_SELECTION,
|
|
|
|
|
.default_string = NULL,
|
|
|
|
|
.default_int = 0,
|
|
|
|
|
.file_filter = NULL,
|
|
|
|
|
.spinner = { 0 },
|
|
|
|
|
.selection = {
|
|
|
|
|
{ .description = "ATI 68860", .value = 0 },
|
|
|
|
|
{ .description = "ATI 68875", .value = 1 },
|
|
|
|
|
{ .description = "" }
|
|
|
|
|
},
|
|
|
|
|
.bios = { { 0 } }
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
},
|
|
|
|
|
{
|
2025-02-03 20:00:58 -05:00
|
|
|
.name = "memory",
|
|
|
|
|
.description = "Memory size",
|
|
|
|
|
.type = CONFIG_SELECTION,
|
|
|
|
|
.default_string = NULL,
|
|
|
|
|
.default_int = 2048,
|
|
|
|
|
.file_filter = NULL,
|
|
|
|
|
.spinner = { 0 },
|
|
|
|
|
.selection = {
|
|
|
|
|
{ .description = "512 KB", .value = 512 },
|
|
|
|
|
{ .description = "1 MB", .value = 1024 },
|
|
|
|
|
{ .description = "2 MB", .value = 2048 },
|
|
|
|
|
{ .description = "4 MB", .value = 4096 },
|
|
|
|
|
{ .description = "" }
|
|
|
|
|
},
|
|
|
|
|
.bios = { { 0 } }
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
},
|
2025-01-07 01:12:42 -05:00
|
|
|
{ .name = "", .description = "", .type = CONFIG_END }
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
};
|
2025-01-07 01:12:42 -05:00
|
|
|
// clang-format on
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
|
2024-01-15 21:43:33 +01:00
|
|
|
const device_t mach8_vga_isa_device = {
|
2025-01-07 01:12:42 -05:00
|
|
|
.name = "ATI Mach8 (ATI Graphics Ultra) (ISA)",
|
2024-01-15 21:43:33 +01:00
|
|
|
.internal_name = "mach8_vga_isa",
|
2025-01-07 01:12:42 -05:00
|
|
|
.flags = DEVICE_ISA,
|
|
|
|
|
.local = 1,
|
|
|
|
|
.init = mach8_init,
|
|
|
|
|
.close = mach_close,
|
|
|
|
|
.reset = NULL,
|
|
|
|
|
.available = mach8_vga_available,
|
2023-07-14 23:38:04 +02:00
|
|
|
.speed_changed = mach_speed_changed,
|
2025-01-07 01:12:42 -05:00
|
|
|
.force_redraw = mach_force_redraw,
|
|
|
|
|
.config = mach8_config
|
2023-07-14 23:38:04 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
const device_t mach32_isa_device = {
|
2025-01-07 01:12:42 -05:00
|
|
|
.name = "ATI Mach32 (ISA)",
|
2023-07-14 23:38:04 +02:00
|
|
|
.internal_name = "mach32_isa",
|
2025-01-07 01:12:42 -05:00
|
|
|
.flags = DEVICE_ISA,
|
|
|
|
|
.local = 2,
|
|
|
|
|
.init = mach8_init,
|
|
|
|
|
.close = mach_close,
|
|
|
|
|
.reset = NULL,
|
|
|
|
|
.available = mach32_isa_available,
|
2023-07-14 23:38:04 +02:00
|
|
|
.speed_changed = mach_speed_changed,
|
2025-01-07 01:12:42 -05:00
|
|
|
.force_redraw = mach_force_redraw,
|
|
|
|
|
.config = mach32_config
|
2023-07-14 23:38:04 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
const device_t mach32_vlb_device = {
|
2025-01-07 01:12:42 -05:00
|
|
|
.name = "ATI Mach32 (VLB)",
|
2023-07-14 23:38:04 +02:00
|
|
|
.internal_name = "mach32_vlb",
|
2025-01-07 01:12:42 -05:00
|
|
|
.flags = DEVICE_VLB,
|
|
|
|
|
.local = 2,
|
|
|
|
|
.init = mach8_init,
|
|
|
|
|
.close = mach_close,
|
|
|
|
|
.reset = NULL,
|
|
|
|
|
.available = mach32_vlb_available,
|
2023-07-14 23:38:04 +02:00
|
|
|
.speed_changed = mach_speed_changed,
|
2025-01-07 01:12:42 -05:00
|
|
|
.force_redraw = mach_force_redraw,
|
|
|
|
|
.config = mach32_config
|
2023-07-14 23:38:04 +02:00
|
|
|
};
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
const device_t mach32_mca_device = {
|
2025-01-07 01:12:42 -05:00
|
|
|
.name = "ATI Mach32 (MCA)",
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
.internal_name = "mach32_mca",
|
2025-01-07 01:12:42 -05:00
|
|
|
.flags = DEVICE_MCA,
|
|
|
|
|
.local = 2,
|
|
|
|
|
.init = mach8_init,
|
|
|
|
|
.close = mach_close,
|
|
|
|
|
.reset = NULL,
|
|
|
|
|
.available = mach32_mca_available,
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
.speed_changed = mach_speed_changed,
|
2025-01-07 01:12:42 -05:00
|
|
|
.force_redraw = mach_force_redraw,
|
|
|
|
|
.config = mach32_config
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
};
|
|
|
|
|
|
2023-07-14 23:38:04 +02:00
|
|
|
const device_t mach32_pci_device = {
|
2025-01-07 01:12:42 -05:00
|
|
|
.name = "ATI Mach32 (PCI)",
|
2023-07-14 23:38:04 +02:00
|
|
|
.internal_name = "mach32_pci",
|
2025-01-07 01:12:42 -05:00
|
|
|
.flags = DEVICE_PCI,
|
|
|
|
|
.local = 2,
|
|
|
|
|
.init = mach8_init,
|
|
|
|
|
.close = mach_close,
|
|
|
|
|
.reset = NULL,
|
|
|
|
|
.available = mach32_pci_available,
|
2023-07-14 23:38:04 +02:00
|
|
|
.speed_changed = mach_speed_changed,
|
2025-01-07 01:12:42 -05:00
|
|
|
.force_redraw = mach_force_redraw,
|
|
|
|
|
.config = mach32_pci_config
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
const device_t mach32_onboard_pci_device = {
|
2025-01-07 01:12:42 -05:00
|
|
|
.name = "ATI Mach32 (PCI) On-Board",
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
.internal_name = "mach32_pci_onboard",
|
2025-01-07 01:12:42 -05:00
|
|
|
.flags = DEVICE_PCI,
|
|
|
|
|
.local = 2 | 0x100,
|
|
|
|
|
.init = mach8_init,
|
|
|
|
|
.close = mach_close,
|
|
|
|
|
.reset = NULL,
|
|
|
|
|
.available = NULL,
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
.speed_changed = mach_speed_changed,
|
2025-01-07 01:12:42 -05:00
|
|
|
.force_redraw = mach_force_redraw,
|
|
|
|
|
.config = mach32_pci_config
|
2023-07-14 23:38:04 +02:00
|
|
|
};
|