2017-10-11 05:40:44 -04:00
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/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Paradise VGA emulation
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* PC2086, PC3086 use PVGA1A
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* MegaPC uses W90C11A
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*
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2020-03-25 00:46:02 +02:00
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*
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2017-10-11 05:40:44 -04:00
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*
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* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
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* Miran Grca, <mgrca8@gmail.com>
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*
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Added the IBM 5161 ISA expansion for PC and XT;
Cleaned up the parallel port emulation, added IRQ support, and made enabling/disabling per port;
Added the Award 430NX and the Intel Classic/PCI (Alfredo, 420TX);
Finished the 586MC1;
Added 8087 emulation;
Moved Cyrix 6x86'es to the Dev branch;
Sanitized/cleaned up memregs.c/h and intel.c/h;
Split the chipsets from machines and sanitized Port 92 emulation;
Added support for the 15bpp mode to the Compaq ATI 28800;
Moved the MR 386DX and 486 machines to the Dev branch;
Ported the new dynamic recompiler from PCem, but it remains in Dev branch until after v2.00;
Ported the new timer code from PCem;
Cleaned up the CPU table of unused stuff and better optimized its structure;
Ported the Open-XT and Open-AT from VARCem, the Open-AT is in the Dev branch;
Ported the XT MFM controller rewrite and adding of more controllers (incl. two RLL ones), from VARCem;
Added the AHA-1540A and the BusTek BT-542B;
Moved the Sumo SCSI-AT to the Dev branch;
Minor IDE, FDC, and floppy drive code clean-ups;
Made NCR 5380/53C400-based cards' BIOS address configurable;
Got rid of the legacy romset variable;
Unified (video) buffer and buffer32 into one and make the unified buffer 32-bit;
Added the Amstead PPC512 per PCem patch by John Elliott;
Switched memory mapping granularity from 16k to 4k (less than 1k not possible due to internal pages);
Rewrote the CL-GD 54xx blitter, fixes Win-OS/2 on the 54x6 among other thing;
Added the Image Manager 1024 and Professional Graphics Controller per PCem patch by John Elliott and work done on VARCem;
Added Headland HT-216, GC-205 and Video 7 VGA 1024i emulation based on PCem commit;
Implemented the fuction keys for the Toshiba T1000/T1200/T3100 enhancement;
Amstrad MegaPC does now works correctly with non-internal graphics card;
The SLiRP code no longer casts a packed struct type to a non-packed struct type;
The Xi8088 and PB410a no longer hang on 86Box when PS/2 mouse is not present;
The S3 Virge on BeOS is no longer broken (was broken by build #1591);
OS/2 2.0 build 6.167 now sees key presses again;
Xi8088 now work on CGA again;
86F images converted from either the old or new variants of the HxC MFM format now work correctly;
Hardware interrupts with a vector of 0xFF are now handled correctly;
OPTi 495SX boards no longer incorrectly have 64 MB maximum RAM when 32 MB is correct;
Fixed VNC keyboard input bugs;
Fixed AT RTC periodic interrupt - Chicago 58s / 73f / 73g / 81 MIDI play no longer hangs with the build's own VTD driver;
Fixed mouse polling with internal mice - Amstrad and Olivetti mice now work correctly;
Triones ATAPI DMA driver now correctly reads a file at the end of a CD image with a sectors number not divisible by 4;
Compaq Portable now works with all graphics cards;
Fixed various MDSI Genius bugs;
Added segment limit checks and improved page fault checks for several CPU instructions - Memphis 15xx WINSETUP and Chicago 58s WINDISK.CPL no longer issue a GPF, and some S3 drivers that used to have glitches, now work correctly;
Further improved the 808x emulation, also fixes the noticably choppy sound when using 808x CPU's, also fixes #355;
OS/2 installer no logner locks up on splash screen on PS/2 Model 70 and 80, fixes #400.
Fixed several Amstead bugs, GEM no longer crashes on the Amstrad 1640, fixes #391.
Ported John Elliott's Amstrad fixes and improvement from PCem, and fixed the default language so it's correctly Engliish, fixes #278, fixes #389.
Fixed a minor IDE timing bug, fixes #388.
Fixed Toshiba T1000 RAM issues, fixes #379.
Fixed EGA/(S)VGA overscan border handling, fixes #378;
Got rid of the now long useless IDE channel 2 auto-removal, fixes #370;
Fixed the BIOS files used by the AMSTRAD PC1512, fixes #366;
Ported the Unicode CD image file name fix from VARCem, fixes #365;
Fixed high density floppy disks on the Xi8088, fixes #359;
Fixed some bugs in the Hercules emulation, fixes #346, fixes #358;
Fixed the SCSI hard disk mode sense pages, fixes #356;
Removed the AMI Unknown 386SX because of impossibility to identify the chipset, closes #349;
Fixed bugs in the serial mouse emulation, fixes #344;
Compiled 86Box binaries now include all the required .DLL's, fixes #341;
Made some combo boxes in the Settings dialog slightly wider, fixes #276.
2019-09-20 14:02:30 +02:00
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* Copyright 2008-2019 Sarah Walker.
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* Copyright 2016-2019 Miran Grca.
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2017-10-11 05:40:44 -04:00
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*/
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2017-09-25 04:31:20 -04:00
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#include <stdio.h>
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#include <stdint.h>
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#include <string.h>
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2016-06-26 00:34:39 +02:00
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#include <stdlib.h>
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2017-09-25 04:31:20 -04:00
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#include <wchar.h>
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2020-03-29 14:24:42 +02:00
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#include <86box/86box.h>
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#include <86box/io.h>
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#include <86box/timer.h>
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#include <86box/mem.h>
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#include <86box/rom.h>
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#include <86box/device.h>
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#include <86box/video.h>
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#include <86box/vid_svga.h>
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#include <86box/vid_svga_render.h>
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2016-06-26 00:34:39 +02:00
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2017-05-06 17:48:33 +02:00
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2016-06-26 00:34:39 +02:00
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typedef struct paradise_t
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{
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svga_t svga;
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2022-02-20 02:26:27 -05:00
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2016-06-26 00:34:39 +02:00
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rom_t bios_rom;
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2022-02-20 02:26:27 -05:00
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uint8_t bank_mask;
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2016-06-26 00:34:39 +02:00
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enum
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{
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PVGA1A = 0,
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2017-12-31 06:37:19 +01:00
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WD90C11,
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WD90C30
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2016-06-26 00:34:39 +02:00
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} type;
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2021-05-30 01:52:43 +02:00
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uint32_t vram_mask;
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2016-06-26 00:34:39 +02:00
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uint32_t read_bank[4], write_bank[4];
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2022-02-20 02:26:27 -05:00
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2021-08-17 18:58:37 +02:00
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int interlace;
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2021-11-18 23:58:04 +01:00
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int check, check2;
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2022-02-20 02:26:27 -05:00
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2021-08-17 18:58:37 +02:00
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struct {
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uint8_t reg_block_ptr;
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uint8_t reg_idx;
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uint8_t disable_autoinc;
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2022-02-20 02:26:27 -05:00
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2021-08-17 18:58:37 +02:00
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uint16_t int_status;
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uint16_t blt_ctrl1, blt_ctrl2;
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uint16_t srclow, srchigh;
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uint16_t dstlow, dsthigh;
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uint32_t srcaddr, dstaddr;
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2022-02-20 02:26:27 -05:00
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2021-08-17 18:58:37 +02:00
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int invalid_block;
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} accel;
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2016-06-26 00:34:39 +02:00
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} paradise_t;
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2018-09-19 20:13:32 +02:00
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static video_timings_t timing_paradise_pvga1a = {VIDEO_ISA, 6, 8, 16, 6, 8, 16};
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static video_timings_t timing_paradise_wd90c = {VIDEO_ISA, 3, 3, 6, 5, 5, 10};
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2016-06-26 00:34:39 +02:00
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void paradise_remap(paradise_t *paradise);
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2022-07-24 05:40:06 +02:00
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uint8_t paradise_in(uint16_t addr, void *p)
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{
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paradise_t *paradise = (paradise_t *)p;
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svga_t *svga = ¶dise->svga;
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if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
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addr ^= 0x60;
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switch (addr)
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{
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case 0x3c5:
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if (svga->seqaddr > 7)
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{
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if (paradise->type < WD90C11 || svga->seqregs[6] != 0x48)
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return 0xff;
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if (svga->seqaddr > 0x12)
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return 0xff;
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return svga->seqregs[svga->seqaddr & 0x1f];
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}
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break;
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case 0x3c6: case 0x3c7: case 0x3c8: case 0x3c9:
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if (paradise->type == WD90C30)
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return sc1148x_ramdac_in(addr, 0, svga->ramdac, svga);
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return svga_in(addr, svga);
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case 0x3cf:
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if (svga->gdcaddr >= 9 && svga->gdcaddr <= 0x0e) {
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if (svga->gdcreg[0x0f] & 0x10)
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return 0xff;
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}
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switch (svga->gdcaddr) {
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case 0x0b:
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if (paradise->type == WD90C30) {
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if (paradise->vram_mask == ((512 << 10) - 1)) {
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svga->gdcreg[0x0b] |= 0xc0;
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svga->gdcreg[0x0b] &= ~0x40;
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}
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}
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return svga->gdcreg[0x0b];
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case 0x0f:
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return (svga->gdcreg[0x0f] & 0x17) | 0x80;
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}
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break;
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case 0x3D4:
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return svga->crtcreg;
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case 0x3D5:
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if ((paradise->type == PVGA1A) && (svga->crtcreg & 0x20))
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return 0xff;
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if (svga->crtcreg > 0x29 && svga->crtcreg < 0x30 && (svga->crtc[0x29] & 0x88) != 0x80)
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return 0xff;
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return svga->crtc[svga->crtcreg];
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}
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return svga_in(addr, svga);
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}
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2016-06-26 00:34:39 +02:00
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void paradise_out(uint16_t addr, uint8_t val, void *p)
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{
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paradise_t *paradise = (paradise_t *)p;
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svga_t *svga = ¶dise->svga;
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2021-11-18 23:58:04 +01:00
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uint8_t old;
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2022-02-20 02:26:27 -05:00
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2021-08-17 18:58:37 +02:00
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if (paradise->vram_mask <= ((512 << 10) - 1))
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paradise->bank_mask = 0x7f;
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else
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paradise->bank_mask = 0xff;
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2022-02-20 02:26:27 -05:00
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if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
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2016-06-26 00:34:39 +02:00
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addr ^= 0x60;
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2021-08-17 18:58:37 +02:00
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2016-06-26 00:34:39 +02:00
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switch (addr)
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{
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case 0x3c5:
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2021-11-18 23:58:04 +01:00
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if (svga->seqaddr > 7) {
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2022-02-20 02:26:27 -05:00
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if (paradise->type < WD90C11 || svga->seqregs[6] != 0x48)
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2021-11-18 23:58:04 +01:00
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return;
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svga->seqregs[svga->seqaddr & 0x1f] = val;
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if (svga->seqaddr == 0x11) {
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paradise_remap(paradise);
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}
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return;
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2016-06-26 00:34:39 +02:00
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}
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break;
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2021-10-24 19:06:05 +02:00
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case 0x3c6: case 0x3c7: case 0x3c8: case 0x3c9:
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if (paradise->type == WD90C30)
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sc1148x_ramdac_out(addr, 0, val, svga->ramdac, svga);
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else
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svga_out(addr, val, svga);
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return;
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2016-06-26 00:34:39 +02:00
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case 0x3cf:
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2021-08-17 18:58:37 +02:00
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if (svga->gdcaddr >= 9 && svga->gdcaddr <= 0x0e) {
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2021-11-18 23:58:04 +01:00
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if ((svga->gdcreg[0x0f] & 7) != 5)
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2021-08-17 18:58:37 +02:00
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return;
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2016-06-26 00:34:39 +02:00
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}
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2021-11-18 23:58:04 +01:00
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2021-08-17 18:58:37 +02:00
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switch (svga->gdcaddr) {
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case 6:
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2021-11-18 23:58:04 +01:00
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if ((svga->gdcreg[6] & 0x0c) != (val & 0x0c)) {
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switch (val & 0x0c) {
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case 0x00: /*128k at A0000*/
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mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000);
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svga->banked_mask = 0xffff;
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break;
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case 0x04: /*64k at A0000*/
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mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
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svga->banked_mask = 0xffff;
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break;
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case 0x08: /*32k at B0000*/
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mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000);
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svga->banked_mask = 0x7fff;
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break;
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case 0x0c: /*32k at B8000*/
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mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000);
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svga->banked_mask = 0x7fff;
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break;
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}
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}
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svga->gdcreg[6] = val;
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2021-08-17 18:58:37 +02:00
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paradise_remap(paradise);
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2021-11-18 23:58:04 +01:00
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return;
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2022-02-20 02:26:27 -05:00
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2021-08-17 18:58:37 +02:00
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case 9:
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case 0x0a:
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2021-11-18 23:58:04 +01:00
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svga->gdcreg[svga->gdcaddr] = val & paradise->bank_mask;
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2021-08-17 18:58:37 +02:00
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paradise_remap(paradise);
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2021-11-18 23:58:04 +01:00
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return;
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2021-08-17 18:58:37 +02:00
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case 0x0b:
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2021-11-18 23:58:04 +01:00
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svga->gdcreg[0x0b] = val;
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2021-08-17 18:58:37 +02:00
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paradise_remap(paradise);
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2021-11-18 23:58:04 +01:00
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return;
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2021-05-30 01:52:43 +02:00
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}
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2016-06-26 00:34:39 +02:00
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break;
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2022-02-20 02:26:27 -05:00
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2016-06-26 00:34:39 +02:00
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case 0x3D4:
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2018-04-25 23:51:13 +02:00
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svga->crtcreg = val & 0x3f;
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2016-06-26 00:34:39 +02:00
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return;
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case 0x3D5:
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2018-04-25 23:51:13 +02:00
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if ((paradise->type == PVGA1A) && (svga->crtcreg & 0x20))
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return;
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2016-06-26 00:34:39 +02:00
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if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80))
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return;
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if ((svga->crtcreg == 7) && (svga->crtc[0x11] & 0x80))
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val = (svga->crtc[7] & ~0x10) | (val & 0x10);
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if (svga->crtcreg > 0x29 && (svga->crtc[0x29] & 7) != 5)
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return;
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if (svga->crtcreg >= 0x31 && svga->crtcreg <= 0x37)
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return;
|
|
|
|
|
old = svga->crtc[svga->crtcreg];
|
|
|
|
|
svga->crtc[svga->crtcreg] = val;
|
2022-02-20 02:26:27 -05:00
|
|
|
|
2016-06-26 00:34:39 +02:00
|
|
|
if (old != val)
|
|
|
|
|
{
|
2021-07-12 22:12:27 +02:00
|
|
|
if (svga->crtcreg < 0xe || svga->crtcreg > 0x10)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2021-07-12 22:12:27 +02:00
|
|
|
if ((svga->crtcreg == 0xc) || (svga->crtcreg == 0xd)) {
|
|
|
|
|
svga->fullchange = 3;
|
|
|
|
|
svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]) + ((svga->crtc[8] & 0x60) >> 5);
|
|
|
|
|
} else {
|
|
|
|
|
svga->fullchange = changeframecount;
|
|
|
|
|
svga_recalctimings(svga);
|
|
|
|
|
}
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
2022-07-24 05:40:06 +02:00
|
|
|
case 0x46e8:
|
|
|
|
|
io_removehandler(0x03c0, 0x0020, paradise_in, NULL, NULL, paradise_out, NULL, NULL, paradise);
|
|
|
|
|
mem_mapping_disable(¶dise->svga.mapping);
|
|
|
|
|
if (val & 8)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2022-07-24 05:40:06 +02:00
|
|
|
io_sethandler(0x03c0, 0x0020, paradise_in, NULL, NULL, paradise_out, NULL, NULL, paradise);
|
|
|
|
|
mem_mapping_enable(¶dise->svga.mapping);
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
2022-07-24 05:40:06 +02:00
|
|
|
|
|
|
|
|
svga_out(addr, val, svga);
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void paradise_remap(paradise_t *paradise)
|
|
|
|
|
{
|
2021-11-18 23:58:04 +01:00
|
|
|
svga_t *svga = ¶dise->svga;
|
|
|
|
|
paradise->check = 0;
|
|
|
|
|
|
|
|
|
|
if (svga->seqregs[0x11] & 0x80) {
|
|
|
|
|
paradise->read_bank[0] = paradise->read_bank[2] = svga->gdcreg[9] << 12;
|
|
|
|
|
paradise->read_bank[1] = paradise->read_bank[3] = (svga->gdcreg[9] << 12) + ((svga->gdcreg[6] & 0x08) ? 0 : 0x8000);
|
|
|
|
|
paradise->write_bank[0] = paradise->write_bank[2] = svga->gdcreg[0x0a] << 12;
|
|
|
|
|
paradise->write_bank[1] = paradise->write_bank[3] = (svga->gdcreg[0x0a] << 12) + ((svga->gdcreg[6] & 0x08) ? 0 : 0x8000);
|
|
|
|
|
} else if (svga->gdcreg[0x0b] & 0x08) {
|
|
|
|
|
if (svga->gdcreg[6] & 0x0c) {
|
|
|
|
|
paradise->read_bank[0] = paradise->read_bank[2] = svga->gdcreg[0x0a] << 12;
|
|
|
|
|
paradise->write_bank[0] = paradise->write_bank[2] = svga->gdcreg[0x0a] << 12;
|
|
|
|
|
paradise->read_bank[1] = paradise->read_bank[3] = (svga->gdcreg[9] << 12) + ((svga->gdcreg[6] & 0x08) ? 0 : 0x8000);
|
|
|
|
|
paradise->write_bank[1] = paradise->write_bank[3] = (svga->gdcreg[9] << 12) + ((svga->gdcreg[6] & 0x08) ? 0 : 0x8000);
|
|
|
|
|
} else {
|
|
|
|
|
paradise->read_bank[0] = paradise->write_bank[0] = svga->gdcreg[0x0a] << 12;
|
|
|
|
|
paradise->read_bank[1] = paradise->write_bank[1] = (svga->gdcreg[0xa] << 12) + ((svga->gdcreg[6] & 0x08) ? 0 : 0x8000);
|
|
|
|
|
paradise->read_bank[2] = paradise->write_bank[2] = svga->gdcreg[9] << 12;
|
|
|
|
|
paradise->read_bank[3] = paradise->write_bank[3] = (svga->gdcreg[9] << 12) + ((svga->gdcreg[6] & 0x08) ? 0 : 0x8000);
|
2021-05-30 01:52:43 +02:00
|
|
|
}
|
2021-11-18 23:58:04 +01:00
|
|
|
} else {
|
|
|
|
|
paradise->read_bank[0] = paradise->read_bank[2] = svga->gdcreg[9] << 12;
|
|
|
|
|
paradise->read_bank[1] = paradise->read_bank[3] = (svga->gdcreg[9] << 12) + ((svga->gdcreg[6] & 0x08) ? 0 : 0x8000);
|
|
|
|
|
paradise->write_bank[0] = paradise->write_bank[2] = svga->gdcreg[9] << 12;
|
|
|
|
|
paradise->write_bank[1] = paradise->write_bank[3] = (svga->gdcreg[9] << 12) + ((svga->gdcreg[6] & 0x08) ? 0 : 0x8000);
|
|
|
|
|
}
|
2022-02-20 02:26:27 -05:00
|
|
|
|
2021-11-18 23:58:04 +01:00
|
|
|
if ((((svga->gdcreg[0x0b] & 0xc0) == 0xc0) && !svga->chain4 && (svga->crtc[0x14] & 0x40) && ((svga->gdcreg[6] >> 2) & 3) == 1))
|
|
|
|
|
paradise->check = 1;
|
2022-02-20 02:26:27 -05:00
|
|
|
|
2021-11-18 23:58:04 +01:00
|
|
|
if (paradise->bank_mask == 0x7f) {
|
|
|
|
|
paradise->read_bank[1] &= 0x7ffff;
|
|
|
|
|
paradise->write_bank[1] &= 0x7ffff;
|
|
|
|
|
}
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void paradise_recalctimings(svga_t *svga)
|
|
|
|
|
{
|
2017-12-31 18:33:22 +01:00
|
|
|
paradise_t *paradise = (paradise_t *) svga->p;
|
|
|
|
|
|
2021-08-17 18:58:37 +02:00
|
|
|
svga->lowres = !(svga->gdcreg[0x0e] & 0x01);
|
2017-12-31 18:33:22 +01:00
|
|
|
|
2021-08-17 18:58:37 +02:00
|
|
|
if (paradise->type == WD90C30) {
|
|
|
|
|
if (svga->crtc[0x3e] & 0x01) svga->vtotal |= 0x400;
|
|
|
|
|
if (svga->crtc[0x3e] & 0x02) svga->dispend |= 0x400;
|
|
|
|
|
if (svga->crtc[0x3e] & 0x04) svga->vsyncstart |= 0x400;
|
|
|
|
|
if (svga->crtc[0x3e] & 0x08) svga->vblankstart |= 0x400;
|
|
|
|
|
if (svga->crtc[0x3e] & 0x10) svga->split |= 0x400;
|
|
|
|
|
|
|
|
|
|
svga->interlace = !!(svga->crtc[0x2d] & 0x20);
|
2022-02-20 02:26:27 -05:00
|
|
|
|
|
|
|
|
if (!svga->interlace && svga->lowres && (svga->hdisp >= 1024) &&
|
|
|
|
|
((svga->gdcreg[5] & 0x60) == 0) && (svga->miscout >= 0x27) &&
|
|
|
|
|
(svga->miscout <= 0x2f) && ((svga->gdcreg[6] & 1) ||
|
2021-08-17 18:58:37 +02:00
|
|
|
(svga->attrregs[0x10] & 1))) { /*Horrible tweak to re-enable the interlace after returning to
|
|
|
|
|
a windowed DOS box in Win3.x*/
|
|
|
|
|
svga->interlace = 1;
|
|
|
|
|
}
|
2020-07-05 02:57:15 +02:00
|
|
|
}
|
2022-02-20 02:26:27 -05:00
|
|
|
|
2021-10-24 19:06:05 +02:00
|
|
|
if (paradise->type < WD90C30) {
|
2021-10-31 19:06:16 +01:00
|
|
|
if (svga->bpp >= 8 && !svga->lowres) {
|
2021-10-24 19:06:05 +02:00
|
|
|
svga->render = svga_render_8bpp_highres;
|
2021-10-31 19:06:16 +01:00
|
|
|
}
|
2021-10-24 19:06:05 +02:00
|
|
|
} else {
|
|
|
|
|
if (svga->bpp >= 8 && !svga->lowres) {
|
|
|
|
|
if (svga->bpp == 16) {
|
|
|
|
|
svga->render = svga_render_16bpp_highres;
|
|
|
|
|
svga->hdisp >>= 1;
|
|
|
|
|
} else if (svga->bpp == 15) {
|
|
|
|
|
svga->render = svga_render_15bpp_highres;
|
|
|
|
|
svga->hdisp >>= 1;
|
|
|
|
|
} else {
|
|
|
|
|
svga->render = svga_render_8bpp_highres;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2018-02-01 03:14:55 +01:00
|
|
|
static void paradise_write(uint32_t addr, uint8_t val, void *p)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
|
|
|
|
paradise_t *paradise = (paradise_t *)p;
|
2021-08-17 18:58:37 +02:00
|
|
|
svga_t *svga = ¶dise->svga;
|
2021-11-18 23:58:04 +01:00
|
|
|
uint32_t prev_addr, prev_addr2;
|
2021-08-17 18:58:37 +02:00
|
|
|
|
2022-02-20 02:26:27 -05:00
|
|
|
addr = (addr & 0x7fff) + paradise->write_bank[(addr >> 15) & 3];
|
|
|
|
|
|
2021-11-18 23:58:04 +01:00
|
|
|
/*Could be done in a better way but it works.*/
|
|
|
|
|
if (!svga->lowres) {
|
|
|
|
|
if (paradise->check) {
|
|
|
|
|
prev_addr = addr & 3;
|
|
|
|
|
prev_addr2 = addr & 0xfffc;
|
|
|
|
|
if ((addr & 3) == 3) {
|
|
|
|
|
if ((addr & 0x30000) == 0x20000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x10000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x00000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
} else if ((addr & 3) == 2) {
|
|
|
|
|
if ((addr & 0x30000) == 0x30000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x10000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x00000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
} else if ((addr & 3) == 1) {
|
|
|
|
|
if ((addr & 0x30000) == 0x30000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x20000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x00000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
} else if ((addr & 3) == 0) {
|
|
|
|
|
if ((addr & 0x30000) == 0x30000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x20000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x10000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
2022-02-20 02:26:27 -05:00
|
|
|
|
2021-08-17 18:58:37 +02:00
|
|
|
svga_write_linear(addr, val, svga);
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
2018-02-01 03:14:55 +01:00
|
|
|
static void paradise_writew(uint32_t addr, uint16_t val, void *p)
|
|
|
|
|
{
|
|
|
|
|
paradise_t *paradise = (paradise_t *)p;
|
2021-08-17 18:58:37 +02:00
|
|
|
svga_t *svga = ¶dise->svga;
|
2021-11-18 23:58:04 +01:00
|
|
|
uint32_t prev_addr, prev_addr2;
|
2021-08-17 18:58:37 +02:00
|
|
|
|
|
|
|
|
addr = (addr & 0x7fff) + paradise->write_bank[(addr >> 15) & 3];
|
2022-02-20 02:26:27 -05:00
|
|
|
|
2021-11-18 23:58:04 +01:00
|
|
|
/*Could be done in a better way but it works.*/
|
|
|
|
|
if (!svga->lowres) {
|
|
|
|
|
if (paradise->check) {
|
|
|
|
|
prev_addr = addr & 3;
|
|
|
|
|
prev_addr2 = addr & 0xfffc;
|
|
|
|
|
if ((addr & 3) == 3) {
|
|
|
|
|
if ((addr & 0x30000) == 0x20000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x10000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x00000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
} else if ((addr & 3) == 2) {
|
|
|
|
|
if ((addr & 0x30000) == 0x30000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x10000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x00000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
} else if ((addr & 3) == 1) {
|
|
|
|
|
if ((addr & 0x30000) == 0x30000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x20000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x00000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
} else if ((addr & 3) == 0) {
|
|
|
|
|
if ((addr & 0x30000) == 0x30000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x20000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x10000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
2022-02-20 02:26:27 -05:00
|
|
|
|
2021-08-17 18:58:37 +02:00
|
|
|
svga_writew_linear(addr, val, svga);
|
2018-02-01 03:14:55 +01:00
|
|
|
}
|
2016-06-26 00:34:39 +02:00
|
|
|
|
2018-02-01 03:14:55 +01:00
|
|
|
static uint8_t paradise_read(uint32_t addr, void *p)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
|
|
|
|
paradise_t *paradise = (paradise_t *)p;
|
2021-08-17 18:58:37 +02:00
|
|
|
svga_t *svga = ¶dise->svga;
|
2021-11-18 23:58:04 +01:00
|
|
|
uint32_t prev_addr, prev_addr2;
|
2022-02-20 02:26:27 -05:00
|
|
|
|
2021-08-17 18:58:37 +02:00
|
|
|
addr = (addr & 0x7fff) + paradise->read_bank[(addr >> 15) & 3];
|
2022-02-20 02:26:27 -05:00
|
|
|
|
2021-11-18 23:58:04 +01:00
|
|
|
/*Could be done in a better way but it works.*/
|
|
|
|
|
if (!svga->lowres) {
|
|
|
|
|
if (paradise->check) {
|
|
|
|
|
prev_addr = addr & 3;
|
|
|
|
|
prev_addr2 = addr & 0xfffc;
|
|
|
|
|
if ((addr & 3) == 3) {
|
|
|
|
|
if ((addr & 0x30000) == 0x20000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x10000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x00000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
} else if ((addr & 3) == 2) {
|
|
|
|
|
if ((addr & 0x30000) == 0x30000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x10000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x00000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
} else if ((addr & 3) == 1) {
|
|
|
|
|
if ((addr & 0x30000) == 0x30000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x20000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x00000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
} else if ((addr & 3) == 0) {
|
|
|
|
|
if ((addr & 0x30000) == 0x30000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x20000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x10000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
2021-08-17 18:58:37 +02:00
|
|
|
|
|
|
|
|
return svga_read_linear(addr, svga);
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
2018-02-01 03:14:55 +01:00
|
|
|
static uint16_t paradise_readw(uint32_t addr, void *p)
|
|
|
|
|
{
|
|
|
|
|
paradise_t *paradise = (paradise_t *)p;
|
2021-08-17 18:58:37 +02:00
|
|
|
svga_t *svga = ¶dise->svga;
|
2021-11-18 23:58:04 +01:00
|
|
|
uint32_t prev_addr, prev_addr2;
|
2022-02-20 02:26:27 -05:00
|
|
|
|
2021-08-17 18:58:37 +02:00
|
|
|
addr = (addr & 0x7fff) + paradise->read_bank[(addr >> 15) & 3];
|
2022-02-20 02:26:27 -05:00
|
|
|
|
2021-11-18 23:58:04 +01:00
|
|
|
/*Could be done in a better way but it works.*/
|
|
|
|
|
if (!svga->lowres) {
|
|
|
|
|
if (paradise->check) {
|
|
|
|
|
prev_addr = addr & 3;
|
|
|
|
|
prev_addr2 = addr & 0xfffc;
|
|
|
|
|
if ((addr & 3) == 3) {
|
|
|
|
|
if ((addr & 0x30000) == 0x20000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x10000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x00000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
} else if ((addr & 3) == 2) {
|
|
|
|
|
if ((addr & 0x30000) == 0x30000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x10000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x00000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
} else if ((addr & 3) == 1) {
|
|
|
|
|
if ((addr & 0x30000) == 0x30000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x20000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x00000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
} else if ((addr & 3) == 0) {
|
|
|
|
|
if ((addr & 0x30000) == 0x30000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x20000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
else if ((addr & 0x30000) == 0x10000)
|
|
|
|
|
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
2021-08-17 18:58:37 +02:00
|
|
|
|
2021-11-18 23:58:04 +01:00
|
|
|
return svga_readw_linear(addr, svga);
|
2018-02-01 03:14:55 +01:00
|
|
|
}
|
2017-10-07 00:46:54 -04:00
|
|
|
|
2018-09-19 20:13:32 +02:00
|
|
|
void *paradise_init(const device_t *info, uint32_t memsize)
|
2017-12-31 06:37:19 +01:00
|
|
|
{
|
|
|
|
|
paradise_t *paradise = malloc(sizeof(paradise_t));
|
|
|
|
|
svga_t *svga = ¶dise->svga;
|
|
|
|
|
memset(paradise, 0, sizeof(paradise_t));
|
|
|
|
|
|
2018-09-19 20:13:32 +02:00
|
|
|
if (info->local == PVGA1A)
|
|
|
|
|
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_paradise_pvga1a);
|
|
|
|
|
else
|
|
|
|
|
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_paradise_wd90c);
|
|
|
|
|
|
|
|
|
|
switch(info->local) {
|
|
|
|
|
case PVGA1A:
|
2021-08-17 18:58:37 +02:00
|
|
|
svga_init(info, svga, paradise, memsize, /*256kb*/
|
2020-07-05 03:41:44 +02:00
|
|
|
paradise_recalctimings,
|
2018-09-19 20:13:32 +02:00
|
|
|
paradise_in, paradise_out,
|
|
|
|
|
NULL,
|
|
|
|
|
NULL);
|
2021-05-30 01:52:43 +02:00
|
|
|
paradise->vram_mask = memsize - 1;
|
2021-08-17 18:58:37 +02:00
|
|
|
svga->decode_mask = memsize - 1;
|
2018-09-19 20:13:32 +02:00
|
|
|
break;
|
|
|
|
|
case WD90C11:
|
2021-08-17 18:58:37 +02:00
|
|
|
svga_init(info, svga, paradise, 1 << 19, /*512kb*/
|
2018-09-19 20:13:32 +02:00
|
|
|
paradise_recalctimings,
|
|
|
|
|
paradise_in, paradise_out,
|
|
|
|
|
NULL,
|
|
|
|
|
NULL);
|
2021-05-30 01:52:43 +02:00
|
|
|
paradise->vram_mask = (1 << 19) - 1;
|
2021-08-17 18:58:37 +02:00
|
|
|
svga->decode_mask = (1 << 19) - 1;
|
2018-09-19 20:13:32 +02:00
|
|
|
break;
|
|
|
|
|
case WD90C30:
|
2021-08-17 18:58:37 +02:00
|
|
|
svga_init(info, svga, paradise, memsize,
|
2018-09-19 20:13:32 +02:00
|
|
|
paradise_recalctimings,
|
|
|
|
|
paradise_in, paradise_out,
|
|
|
|
|
NULL,
|
|
|
|
|
NULL);
|
2021-05-30 01:52:43 +02:00
|
|
|
paradise->vram_mask = memsize - 1;
|
2021-08-17 18:58:37 +02:00
|
|
|
svga->decode_mask = memsize - 1;
|
2021-10-24 19:06:05 +02:00
|
|
|
svga->ramdac = device_add(&sc11487_ramdac_device); /*Actually a Winbond W82c487-80, probably a clone.*/
|
2018-09-19 20:13:32 +02:00
|
|
|
break;
|
|
|
|
|
}
|
2022-02-20 02:26:27 -05:00
|
|
|
|
2021-08-17 18:58:37 +02:00
|
|
|
mem_mapping_set_handler(&svga->mapping, paradise_read, paradise_readw, NULL, paradise_write, paradise_writew, NULL);
|
|
|
|
|
mem_mapping_set_p(&svga->mapping, paradise);
|
2017-12-31 06:37:19 +01:00
|
|
|
|
2021-08-17 18:58:37 +02:00
|
|
|
io_sethandler(0x03c0, 0x0020, paradise_in, NULL, NULL, paradise_out, NULL, NULL, paradise);
|
2017-12-31 06:37:19 +01:00
|
|
|
|
2018-09-19 20:13:32 +02:00
|
|
|
/* Common to all three types. */
|
|
|
|
|
svga->crtc[0x31] = 'W';
|
|
|
|
|
svga->crtc[0x32] = 'D';
|
|
|
|
|
svga->crtc[0x33] = '9';
|
|
|
|
|
svga->crtc[0x34] = '0';
|
|
|
|
|
svga->crtc[0x35] = 'C';
|
|
|
|
|
|
|
|
|
|
switch(info->local) {
|
|
|
|
|
case WD90C11:
|
|
|
|
|
svga->crtc[0x36] = '1';
|
|
|
|
|
svga->crtc[0x37] = '1';
|
2022-07-24 05:40:06 +02:00
|
|
|
io_sethandler(0x46e8, 0x0001, paradise_in, NULL, NULL, paradise_out, NULL, NULL, paradise);
|
2018-09-19 20:13:32 +02:00
|
|
|
break;
|
|
|
|
|
case WD90C30:
|
|
|
|
|
svga->crtc[0x36] = '3';
|
|
|
|
|
svga->crtc[0x37] = '0';
|
|
|
|
|
break;
|
|
|
|
|
}
|
2017-12-31 06:37:19 +01:00
|
|
|
|
2021-08-17 18:58:37 +02:00
|
|
|
svga->bpp = 8;
|
|
|
|
|
svga->miscout = 1;
|
2018-04-25 23:51:13 +02:00
|
|
|
|
2021-08-17 18:58:37 +02:00
|
|
|
paradise->type = info->local;
|
2022-02-20 02:26:27 -05:00
|
|
|
|
2021-08-17 18:58:37 +02:00
|
|
|
return paradise;
|
2017-12-31 06:37:19 +01:00
|
|
|
}
|
|
|
|
|
|
2021-01-23 17:59:02 +01:00
|
|
|
static void *paradise_pvga1a_ncr3302_init(const device_t *info)
|
|
|
|
|
{
|
|
|
|
|
paradise_t *paradise = paradise_init(info, 1 << 18);
|
2022-02-20 02:26:27 -05:00
|
|
|
|
2021-01-23 17:59:02 +01:00
|
|
|
if (paradise)
|
2021-11-21 13:17:30 -03:00
|
|
|
rom_init(¶dise->bios_rom, "roms/machines/3302/c000-wd_1987-1989-740011-003058-019c.bin", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
|
2022-02-20 02:26:27 -05:00
|
|
|
|
2021-01-23 17:59:02 +01:00
|
|
|
return paradise;
|
|
|
|
|
}
|
|
|
|
|
|
2018-03-19 01:02:04 +01:00
|
|
|
static void *paradise_pvga1a_pc2086_init(const device_t *info)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2018-09-19 20:13:32 +02:00
|
|
|
paradise_t *paradise = paradise_init(info, 1 << 18);
|
2022-02-20 02:26:27 -05:00
|
|
|
|
2016-06-26 00:34:39 +02:00
|
|
|
if (paradise)
|
2021-03-14 20:35:01 +01:00
|
|
|
rom_init(¶dise->bios_rom, "roms/machines/pc2086/40186.ic171", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
|
2022-02-20 02:26:27 -05:00
|
|
|
|
2016-06-26 00:34:39 +02:00
|
|
|
return paradise;
|
|
|
|
|
}
|
2021-01-23 17:59:02 +01:00
|
|
|
|
2018-03-19 01:02:04 +01:00
|
|
|
static void *paradise_pvga1a_pc3086_init(const device_t *info)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2018-09-19 20:13:32 +02:00
|
|
|
paradise_t *paradise = paradise_init(info, 1 << 18);
|
2016-06-26 00:34:39 +02:00
|
|
|
|
|
|
|
|
if (paradise)
|
2021-03-14 20:35:01 +01:00
|
|
|
rom_init(¶dise->bios_rom, "roms/machines/pc3086/c000.bin", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
|
2022-02-20 02:26:27 -05:00
|
|
|
|
2016-06-26 00:34:39 +02:00
|
|
|
return paradise;
|
|
|
|
|
}
|
|
|
|
|
|
2018-03-19 01:02:04 +01:00
|
|
|
static void *paradise_pvga1a_standalone_init(const device_t *info)
|
2017-12-31 06:37:19 +01:00
|
|
|
{
|
|
|
|
|
paradise_t *paradise;
|
|
|
|
|
uint32_t memory = 512;
|
|
|
|
|
|
|
|
|
|
memory = device_get_config_int("memory");
|
|
|
|
|
memory <<= 10;
|
|
|
|
|
|
2018-09-19 20:13:32 +02:00
|
|
|
paradise = paradise_init(info, memory);
|
2022-02-20 02:26:27 -05:00
|
|
|
|
2017-12-31 06:37:19 +01:00
|
|
|
if (paradise)
|
2021-03-14 20:35:01 +01:00
|
|
|
rom_init(¶dise->bios_rom, "roms/video/pvga1a/BIOS.BIN", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
|
2022-02-20 02:26:27 -05:00
|
|
|
|
2017-12-31 06:37:19 +01:00
|
|
|
return paradise;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int paradise_pvga1a_standalone_available(void)
|
|
|
|
|
{
|
2021-03-14 20:35:01 +01:00
|
|
|
return rom_present("roms/video/pvga1a/BIOS.BIN");
|
2017-12-31 06:37:19 +01:00
|
|
|
}
|
|
|
|
|
|
2018-03-19 01:02:04 +01:00
|
|
|
static void *paradise_wd90c11_megapc_init(const device_t *info)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2018-09-19 20:13:32 +02:00
|
|
|
paradise_t *paradise = paradise_init(info, 0);
|
2022-02-20 02:26:27 -05:00
|
|
|
|
2016-06-26 00:34:39 +02:00
|
|
|
if (paradise)
|
|
|
|
|
rom_init_interleaved(¶dise->bios_rom,
|
2021-03-14 20:35:01 +01:00
|
|
|
"roms/machines/megapc/41651-bios lo.u18",
|
|
|
|
|
"roms/machines/megapc/211253-bios hi.u19",
|
2016-06-26 00:34:39 +02:00
|
|
|
0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
|
2022-02-20 02:26:27 -05:00
|
|
|
|
2016-06-26 00:34:39 +02:00
|
|
|
return paradise;
|
|
|
|
|
}
|
|
|
|
|
|
2018-03-19 01:02:04 +01:00
|
|
|
static void *paradise_wd90c11_standalone_init(const device_t *info)
|
2017-12-31 06:37:19 +01:00
|
|
|
{
|
2018-09-19 20:13:32 +02:00
|
|
|
paradise_t *paradise = paradise_init(info, 0);
|
2022-02-20 02:26:27 -05:00
|
|
|
|
2017-12-31 06:37:19 +01:00
|
|
|
if (paradise)
|
2021-03-14 20:35:01 +01:00
|
|
|
rom_init(¶dise->bios_rom, "roms/video/wd90c11/WD90C11.VBI", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
|
2022-02-20 02:26:27 -05:00
|
|
|
|
2017-12-31 06:37:19 +01:00
|
|
|
return paradise;
|
|
|
|
|
}
|
|
|
|
|
|
2017-10-07 00:46:54 -04:00
|
|
|
static int paradise_wd90c11_standalone_available(void)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2021-03-14 20:35:01 +01:00
|
|
|
return rom_present("roms/video/wd90c11/WD90C11.VBI");
|
2017-12-31 06:37:19 +01:00
|
|
|
}
|
|
|
|
|
|
2018-03-19 01:02:04 +01:00
|
|
|
static void *paradise_wd90c30_standalone_init(const device_t *info)
|
2017-12-31 06:37:19 +01:00
|
|
|
{
|
|
|
|
|
paradise_t *paradise;
|
|
|
|
|
uint32_t memory = 512;
|
|
|
|
|
|
|
|
|
|
memory = device_get_config_int("memory");
|
|
|
|
|
memory <<= 10;
|
|
|
|
|
|
2018-09-19 20:13:32 +02:00
|
|
|
paradise = paradise_init(info, memory);
|
2022-02-20 02:26:27 -05:00
|
|
|
|
2017-12-31 06:37:19 +01:00
|
|
|
if (paradise)
|
2021-03-14 20:35:01 +01:00
|
|
|
rom_init(¶dise->bios_rom, "roms/video/wd90c30/90C30-LR.VBI", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
|
2017-12-31 06:37:19 +01:00
|
|
|
|
|
|
|
|
return paradise;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int paradise_wd90c30_standalone_available(void)
|
|
|
|
|
{
|
2021-03-14 20:35:01 +01:00
|
|
|
return rom_present("roms/video/wd90c30/90C30-LR.VBI");
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void paradise_close(void *p)
|
|
|
|
|
{
|
|
|
|
|
paradise_t *paradise = (paradise_t *)p;
|
|
|
|
|
|
|
|
|
|
svga_close(¶dise->svga);
|
2022-02-20 02:26:27 -05:00
|
|
|
|
2016-06-26 00:34:39 +02:00
|
|
|
free(paradise);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void paradise_speed_changed(void *p)
|
|
|
|
|
{
|
|
|
|
|
paradise_t *paradise = (paradise_t *)p;
|
2022-02-20 02:26:27 -05:00
|
|
|
|
2016-06-26 00:34:39 +02:00
|
|
|
svga_recalctimings(¶dise->svga);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void paradise_force_redraw(void *p)
|
|
|
|
|
{
|
|
|
|
|
paradise_t *paradise = (paradise_t *)p;
|
|
|
|
|
|
|
|
|
|
paradise->svga.fullchange = changeframecount;
|
|
|
|
|
}
|
|
|
|
|
|
2022-04-09 20:09:14 -04:00
|
|
|
const device_t paradise_pvga1a_pc2086_device = {
|
|
|
|
|
.name = "Paradise PVGA1A (Amstrad PC2086)",
|
|
|
|
|
.internal_name = "pvga1a_pc2086",
|
|
|
|
|
.flags = 0,
|
|
|
|
|
.local = PVGA1A,
|
|
|
|
|
.init = paradise_pvga1a_pc2086_init,
|
|
|
|
|
.close = paradise_close,
|
|
|
|
|
.reset = NULL,
|
|
|
|
|
{ .available = NULL },
|
|
|
|
|
.speed_changed = paradise_speed_changed,
|
|
|
|
|
.force_redraw = paradise_force_redraw,
|
|
|
|
|
.config = NULL
|
2016-06-26 00:34:39 +02:00
|
|
|
};
|
2021-01-23 17:59:02 +01:00
|
|
|
|
2022-04-09 20:09:14 -04:00
|
|
|
const device_t paradise_pvga1a_pc3086_device = {
|
|
|
|
|
.name = "Paradise PVGA1A (Amstrad PC3086)",
|
|
|
|
|
.internal_name = "pvga1a_pc3086",
|
|
|
|
|
.flags = 0,
|
|
|
|
|
.local = PVGA1A,
|
|
|
|
|
.init = paradise_pvga1a_pc3086_init,
|
|
|
|
|
.close = paradise_close,
|
|
|
|
|
.reset = NULL,
|
|
|
|
|
{ .available = NULL },
|
|
|
|
|
.speed_changed = paradise_speed_changed,
|
|
|
|
|
.force_redraw = paradise_force_redraw,
|
|
|
|
|
.config = NULL
|
2016-06-26 00:34:39 +02:00
|
|
|
};
|
2017-12-31 06:37:19 +01:00
|
|
|
|
2022-04-09 20:09:14 -04:00
|
|
|
static const device_config_t paradise_pvga1a_config[] = {
|
|
|
|
|
{
|
|
|
|
|
.name = "memory",
|
|
|
|
|
.description = "Memory size",
|
|
|
|
|
.type = CONFIG_SELECTION,
|
|
|
|
|
.default_int = 512,
|
|
|
|
|
.selection = {
|
|
|
|
|
{
|
|
|
|
|
.description = "256 kB",
|
|
|
|
|
.value = 256
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.description = "512 kB",
|
|
|
|
|
.value = 512
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.description = ""
|
|
|
|
|
}
|
2017-12-31 06:37:19 +01:00
|
|
|
}
|
2022-04-09 20:09:14 -04:00
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.type = CONFIG_END
|
|
|
|
|
}
|
2017-12-31 06:37:19 +01:00
|
|
|
};
|
|
|
|
|
|
2022-04-09 20:09:14 -04:00
|
|
|
const device_t paradise_pvga1a_ncr3302_device = {
|
|
|
|
|
.name = "Paradise PVGA1A (NCR 3302)",
|
|
|
|
|
.internal_name = "pvga1a_ncr3302",
|
|
|
|
|
.flags = 0,
|
|
|
|
|
.local = PVGA1A,
|
|
|
|
|
.init = paradise_pvga1a_ncr3302_init,
|
|
|
|
|
.close = paradise_close,
|
|
|
|
|
.reset = NULL,
|
|
|
|
|
{ .available = NULL },
|
|
|
|
|
.speed_changed = paradise_speed_changed,
|
|
|
|
|
.force_redraw = paradise_force_redraw,
|
|
|
|
|
.config = paradise_pvga1a_config
|
2021-01-23 17:59:02 +01:00
|
|
|
};
|
|
|
|
|
|
2022-04-09 20:09:14 -04:00
|
|
|
const device_t paradise_pvga1a_device = {
|
|
|
|
|
.name = "Paradise PVGA1A",
|
|
|
|
|
.internal_name = "pvga1a",
|
|
|
|
|
.flags = DEVICE_ISA,
|
|
|
|
|
.local = PVGA1A,
|
|
|
|
|
.init = paradise_pvga1a_standalone_init,
|
|
|
|
|
.close = paradise_close,
|
|
|
|
|
.reset = NULL,
|
|
|
|
|
{ .available = paradise_pvga1a_standalone_available },
|
|
|
|
|
.speed_changed = paradise_speed_changed,
|
|
|
|
|
.force_redraw = paradise_force_redraw,
|
|
|
|
|
.config = paradise_pvga1a_config
|
2017-12-31 06:37:19 +01:00
|
|
|
};
|
2022-04-09 20:09:14 -04:00
|
|
|
|
|
|
|
|
const device_t paradise_wd90c11_megapc_device = {
|
|
|
|
|
.name = "Paradise WD90C11 (Amstrad MegaPC)",
|
|
|
|
|
.internal_name = "wd90c11_megapc",
|
|
|
|
|
.flags = 0,
|
|
|
|
|
.local = WD90C11,
|
|
|
|
|
.init = paradise_wd90c11_megapc_init,
|
|
|
|
|
.close = paradise_close,
|
|
|
|
|
.reset = NULL,
|
|
|
|
|
{ .available = NULL },
|
|
|
|
|
.speed_changed = paradise_speed_changed,
|
|
|
|
|
.force_redraw = paradise_force_redraw,
|
|
|
|
|
.config = NULL
|
2016-06-26 00:34:39 +02:00
|
|
|
};
|
2022-04-09 20:09:14 -04:00
|
|
|
|
|
|
|
|
const device_t paradise_wd90c11_device = {
|
|
|
|
|
.name = "Paradise WD90C11-LR",
|
|
|
|
|
.internal_name = "wd90c11",
|
|
|
|
|
.flags = DEVICE_ISA,
|
|
|
|
|
.local = WD90C11,
|
|
|
|
|
.init = paradise_wd90c11_standalone_init,
|
|
|
|
|
.close = paradise_close,
|
|
|
|
|
.reset = NULL,
|
|
|
|
|
{ .available = paradise_wd90c11_standalone_available },
|
|
|
|
|
.speed_changed = paradise_speed_changed,
|
|
|
|
|
.force_redraw = paradise_force_redraw,
|
|
|
|
|
.config = NULL
|
2016-06-26 00:34:39 +02:00
|
|
|
};
|
2017-12-31 06:37:19 +01:00
|
|
|
|
2022-02-26 23:31:28 -05:00
|
|
|
static const device_config_t paradise_wd90c30_config[] = {
|
|
|
|
|
// clang-format off
|
|
|
|
|
{
|
2022-04-09 20:09:14 -04:00
|
|
|
.name = "memory",
|
|
|
|
|
.description = "Memory size",
|
|
|
|
|
.type = CONFIG_SELECTION,
|
|
|
|
|
.default_int = 1024,
|
|
|
|
|
.selection = {
|
|
|
|
|
{
|
|
|
|
|
.description = "512 kB",
|
|
|
|
|
.value = 512
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.description = "1 MB",
|
|
|
|
|
.value = 1024
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.description = ""
|
|
|
|
|
}
|
2017-12-31 06:37:19 +01:00
|
|
|
}
|
2022-02-26 23:31:28 -05:00
|
|
|
},
|
2022-04-09 20:09:14 -04:00
|
|
|
{
|
|
|
|
|
.type = CONFIG_END
|
|
|
|
|
}
|
2022-02-26 23:31:28 -05:00
|
|
|
// clang-format on
|
2017-12-31 06:37:19 +01:00
|
|
|
};
|
|
|
|
|
|
2022-03-13 21:43:45 -04:00
|
|
|
const device_t paradise_wd90c30_device = {
|
|
|
|
|
.name = "Paradise WD90C30-LR",
|
|
|
|
|
.internal_name = "wd90c30",
|
|
|
|
|
.flags = DEVICE_ISA,
|
|
|
|
|
.local = WD90C30,
|
|
|
|
|
.init = paradise_wd90c30_standalone_init,
|
|
|
|
|
.close = paradise_close,
|
|
|
|
|
.reset = NULL,
|
|
|
|
|
{ .available = paradise_wd90c30_standalone_available },
|
|
|
|
|
.speed_changed = paradise_speed_changed,
|
|
|
|
|
.force_redraw = paradise_force_redraw,
|
|
|
|
|
.config = paradise_wd90c30_config
|
2017-12-31 06:37:19 +01:00
|
|
|
};
|