Added the IBM 5161 ISA expansion for PC and XT;
Cleaned up the parallel port emulation, added IRQ support, and made enabling/disabling per port;
Added the Award 430NX and the Intel Classic/PCI (Alfredo, 420TX);
Finished the 586MC1;
Added 8087 emulation;
Moved Cyrix 6x86'es to the Dev branch;
Sanitized/cleaned up memregs.c/h and intel.c/h;
Split the chipsets from machines and sanitized Port 92 emulation;
Added support for the 15bpp mode to the Compaq ATI 28800;
Moved the MR 386DX and 486 machines to the Dev branch;
Ported the new dynamic recompiler from PCem, but it remains in Dev branch until after v2.00;
Ported the new timer code from PCem;
Cleaned up the CPU table of unused stuff and better optimized its structure;
Ported the Open-XT and Open-AT from VARCem, the Open-AT is in the Dev branch;
Ported the XT MFM controller rewrite and adding of more controllers (incl. two RLL ones), from VARCem;
Added the AHA-1540A and the BusTek BT-542B;
Moved the Sumo SCSI-AT to the Dev branch;
Minor IDE, FDC, and floppy drive code clean-ups;
Made NCR 5380/53C400-based cards' BIOS address configurable;
Got rid of the legacy romset variable;
Unified (video) buffer and buffer32 into one and make the unified buffer 32-bit;
Added the Amstead PPC512 per PCem patch by John Elliott;
Switched memory mapping granularity from 16k to 4k (less than 1k not possible due to internal pages);
Rewrote the CL-GD 54xx blitter, fixes Win-OS/2 on the 54x6 among other thing;
Added the Image Manager 1024 and Professional Graphics Controller per PCem patch by John Elliott and work done on VARCem;
Added Headland HT-216, GC-205 and Video 7 VGA 1024i emulation based on PCem commit;
Implemented the fuction keys for the Toshiba T1000/T1200/T3100 enhancement;
Amstrad MegaPC does now works correctly with non-internal graphics card;
The SLiRP code no longer casts a packed struct type to a non-packed struct type;
The Xi8088 and PB410a no longer hang on 86Box when PS/2 mouse is not present;
The S3 Virge on BeOS is no longer broken (was broken by build #1591);
OS/2 2.0 build 6.167 now sees key presses again;
Xi8088 now work on CGA again;
86F images converted from either the old or new variants of the HxC MFM format now work correctly;
Hardware interrupts with a vector of 0xFF are now handled correctly;
OPTi 495SX boards no longer incorrectly have 64 MB maximum RAM when 32 MB is correct;
Fixed VNC keyboard input bugs;
Fixed AT RTC periodic interrupt - Chicago 58s / 73f / 73g / 81 MIDI play no longer hangs with the build's own VTD driver;
Fixed mouse polling with internal mice - Amstrad and Olivetti mice now work correctly;
Triones ATAPI DMA driver now correctly reads a file at the end of a CD image with a sectors number not divisible by 4;
Compaq Portable now works with all graphics cards;
Fixed various MDSI Genius bugs;
Added segment limit checks and improved page fault checks for several CPU instructions - Memphis 15xx WINSETUP and Chicago 58s WINDISK.CPL no longer issue a GPF, and some S3 drivers that used to have glitches, now work correctly;
Further improved the 808x emulation, also fixes the noticably choppy sound when using 808x CPU's, also fixes #355;
OS/2 installer no logner locks up on splash screen on PS/2 Model 70 and 80, fixes #400.
Fixed several Amstead bugs, GEM no longer crashes on the Amstrad 1640, fixes #391.
Ported John Elliott's Amstrad fixes and improvement from PCem, and fixed the default language so it's correctly Engliish, fixes #278, fixes #389.
Fixed a minor IDE timing bug, fixes #388.
Fixed Toshiba T1000 RAM issues, fixes #379.
Fixed EGA/(S)VGA overscan border handling, fixes #378;
Got rid of the now long useless IDE channel 2 auto-removal, fixes #370;
Fixed the BIOS files used by the AMSTRAD PC1512, fixes #366;
Ported the Unicode CD image file name fix from VARCem, fixes #365;
Fixed high density floppy disks on the Xi8088, fixes #359;
Fixed some bugs in the Hercules emulation, fixes #346, fixes #358;
Fixed the SCSI hard disk mode sense pages, fixes #356;
Removed the AMI Unknown 386SX because of impossibility to identify the chipset, closes #349;
Fixed bugs in the serial mouse emulation, fixes #344;
Compiled 86Box binaries now include all the required .DLL's, fixes #341;
Made some combo boxes in the Settings dialog slightly wider, fixes #276.
2019-09-20 14:02:30 +02:00
|
|
|
#include <stdint.h>
|
2020-03-29 14:24:42 +02:00
|
|
|
#include <86box/86box.h>
|
Added the IBM 5161 ISA expansion for PC and XT;
Cleaned up the parallel port emulation, added IRQ support, and made enabling/disabling per port;
Added the Award 430NX and the Intel Classic/PCI (Alfredo, 420TX);
Finished the 586MC1;
Added 8087 emulation;
Moved Cyrix 6x86'es to the Dev branch;
Sanitized/cleaned up memregs.c/h and intel.c/h;
Split the chipsets from machines and sanitized Port 92 emulation;
Added support for the 15bpp mode to the Compaq ATI 28800;
Moved the MR 386DX and 486 machines to the Dev branch;
Ported the new dynamic recompiler from PCem, but it remains in Dev branch until after v2.00;
Ported the new timer code from PCem;
Cleaned up the CPU table of unused stuff and better optimized its structure;
Ported the Open-XT and Open-AT from VARCem, the Open-AT is in the Dev branch;
Ported the XT MFM controller rewrite and adding of more controllers (incl. two RLL ones), from VARCem;
Added the AHA-1540A and the BusTek BT-542B;
Moved the Sumo SCSI-AT to the Dev branch;
Minor IDE, FDC, and floppy drive code clean-ups;
Made NCR 5380/53C400-based cards' BIOS address configurable;
Got rid of the legacy romset variable;
Unified (video) buffer and buffer32 into one and make the unified buffer 32-bit;
Added the Amstead PPC512 per PCem patch by John Elliott;
Switched memory mapping granularity from 16k to 4k (less than 1k not possible due to internal pages);
Rewrote the CL-GD 54xx blitter, fixes Win-OS/2 on the 54x6 among other thing;
Added the Image Manager 1024 and Professional Graphics Controller per PCem patch by John Elliott and work done on VARCem;
Added Headland HT-216, GC-205 and Video 7 VGA 1024i emulation based on PCem commit;
Implemented the fuction keys for the Toshiba T1000/T1200/T3100 enhancement;
Amstrad MegaPC does now works correctly with non-internal graphics card;
The SLiRP code no longer casts a packed struct type to a non-packed struct type;
The Xi8088 and PB410a no longer hang on 86Box when PS/2 mouse is not present;
The S3 Virge on BeOS is no longer broken (was broken by build #1591);
OS/2 2.0 build 6.167 now sees key presses again;
Xi8088 now work on CGA again;
86F images converted from either the old or new variants of the HxC MFM format now work correctly;
Hardware interrupts with a vector of 0xFF are now handled correctly;
OPTi 495SX boards no longer incorrectly have 64 MB maximum RAM when 32 MB is correct;
Fixed VNC keyboard input bugs;
Fixed AT RTC periodic interrupt - Chicago 58s / 73f / 73g / 81 MIDI play no longer hangs with the build's own VTD driver;
Fixed mouse polling with internal mice - Amstrad and Olivetti mice now work correctly;
Triones ATAPI DMA driver now correctly reads a file at the end of a CD image with a sectors number not divisible by 4;
Compaq Portable now works with all graphics cards;
Fixed various MDSI Genius bugs;
Added segment limit checks and improved page fault checks for several CPU instructions - Memphis 15xx WINSETUP and Chicago 58s WINDISK.CPL no longer issue a GPF, and some S3 drivers that used to have glitches, now work correctly;
Further improved the 808x emulation, also fixes the noticably choppy sound when using 808x CPU's, also fixes #355;
OS/2 installer no logner locks up on splash screen on PS/2 Model 70 and 80, fixes #400.
Fixed several Amstead bugs, GEM no longer crashes on the Amstrad 1640, fixes #391.
Ported John Elliott's Amstrad fixes and improvement from PCem, and fixed the default language so it's correctly Engliish, fixes #278, fixes #389.
Fixed a minor IDE timing bug, fixes #388.
Fixed Toshiba T1000 RAM issues, fixes #379.
Fixed EGA/(S)VGA overscan border handling, fixes #378;
Got rid of the now long useless IDE channel 2 auto-removal, fixes #370;
Fixed the BIOS files used by the AMSTRAD PC1512, fixes #366;
Ported the Unicode CD image file name fix from VARCem, fixes #365;
Fixed high density floppy disks on the Xi8088, fixes #359;
Fixed some bugs in the Hercules emulation, fixes #346, fixes #358;
Fixed the SCSI hard disk mode sense pages, fixes #356;
Removed the AMI Unknown 386SX because of impossibility to identify the chipset, closes #349;
Fixed bugs in the serial mouse emulation, fixes #344;
Compiled 86Box binaries now include all the required .DLL's, fixes #341;
Made some combo boxes in the Settings dialog slightly wider, fixes #276.
2019-09-20 14:02:30 +02:00
|
|
|
#include "cpu.h"
|
2020-03-29 14:24:42 +02:00
|
|
|
#include <86box/mem.h>
|
Added the IBM 5161 ISA expansion for PC and XT;
Cleaned up the parallel port emulation, added IRQ support, and made enabling/disabling per port;
Added the Award 430NX and the Intel Classic/PCI (Alfredo, 420TX);
Finished the 586MC1;
Added 8087 emulation;
Moved Cyrix 6x86'es to the Dev branch;
Sanitized/cleaned up memregs.c/h and intel.c/h;
Split the chipsets from machines and sanitized Port 92 emulation;
Added support for the 15bpp mode to the Compaq ATI 28800;
Moved the MR 386DX and 486 machines to the Dev branch;
Ported the new dynamic recompiler from PCem, but it remains in Dev branch until after v2.00;
Ported the new timer code from PCem;
Cleaned up the CPU table of unused stuff and better optimized its structure;
Ported the Open-XT and Open-AT from VARCem, the Open-AT is in the Dev branch;
Ported the XT MFM controller rewrite and adding of more controllers (incl. two RLL ones), from VARCem;
Added the AHA-1540A and the BusTek BT-542B;
Moved the Sumo SCSI-AT to the Dev branch;
Minor IDE, FDC, and floppy drive code clean-ups;
Made NCR 5380/53C400-based cards' BIOS address configurable;
Got rid of the legacy romset variable;
Unified (video) buffer and buffer32 into one and make the unified buffer 32-bit;
Added the Amstead PPC512 per PCem patch by John Elliott;
Switched memory mapping granularity from 16k to 4k (less than 1k not possible due to internal pages);
Rewrote the CL-GD 54xx blitter, fixes Win-OS/2 on the 54x6 among other thing;
Added the Image Manager 1024 and Professional Graphics Controller per PCem patch by John Elliott and work done on VARCem;
Added Headland HT-216, GC-205 and Video 7 VGA 1024i emulation based on PCem commit;
Implemented the fuction keys for the Toshiba T1000/T1200/T3100 enhancement;
Amstrad MegaPC does now works correctly with non-internal graphics card;
The SLiRP code no longer casts a packed struct type to a non-packed struct type;
The Xi8088 and PB410a no longer hang on 86Box when PS/2 mouse is not present;
The S3 Virge on BeOS is no longer broken (was broken by build #1591);
OS/2 2.0 build 6.167 now sees key presses again;
Xi8088 now work on CGA again;
86F images converted from either the old or new variants of the HxC MFM format now work correctly;
Hardware interrupts with a vector of 0xFF are now handled correctly;
OPTi 495SX boards no longer incorrectly have 64 MB maximum RAM when 32 MB is correct;
Fixed VNC keyboard input bugs;
Fixed AT RTC periodic interrupt - Chicago 58s / 73f / 73g / 81 MIDI play no longer hangs with the build's own VTD driver;
Fixed mouse polling with internal mice - Amstrad and Olivetti mice now work correctly;
Triones ATAPI DMA driver now correctly reads a file at the end of a CD image with a sectors number not divisible by 4;
Compaq Portable now works with all graphics cards;
Fixed various MDSI Genius bugs;
Added segment limit checks and improved page fault checks for several CPU instructions - Memphis 15xx WINSETUP and Chicago 58s WINDISK.CPL no longer issue a GPF, and some S3 drivers that used to have glitches, now work correctly;
Further improved the 808x emulation, also fixes the noticably choppy sound when using 808x CPU's, also fixes #355;
OS/2 installer no logner locks up on splash screen on PS/2 Model 70 and 80, fixes #400.
Fixed several Amstead bugs, GEM no longer crashes on the Amstrad 1640, fixes #391.
Ported John Elliott's Amstrad fixes and improvement from PCem, and fixed the default language so it's correctly Engliish, fixes #278, fixes #389.
Fixed a minor IDE timing bug, fixes #388.
Fixed Toshiba T1000 RAM issues, fixes #379.
Fixed EGA/(S)VGA overscan border handling, fixes #378;
Got rid of the now long useless IDE channel 2 auto-removal, fixes #370;
Fixed the BIOS files used by the AMSTRAD PC1512, fixes #366;
Ported the Unicode CD image file name fix from VARCem, fixes #365;
Fixed high density floppy disks on the Xi8088, fixes #359;
Fixed some bugs in the Hercules emulation, fixes #346, fixes #358;
Fixed the SCSI hard disk mode sense pages, fixes #356;
Removed the AMI Unknown 386SX because of impossibility to identify the chipset, closes #349;
Fixed bugs in the serial mouse emulation, fixes #344;
Compiled 86Box binaries now include all the required .DLL's, fixes #341;
Made some combo boxes in the Settings dialog slightly wider, fixes #276.
2019-09-20 14:02:30 +02:00
|
|
|
|
|
|
|
|
#include "x86.h"
|
|
|
|
|
#include "x86_flags.h"
|
|
|
|
|
#include "386_common.h"
|
|
|
|
|
#include "codegen.h"
|
|
|
|
|
#include "codegen_backend.h"
|
|
|
|
|
#include "codegen_ir.h"
|
|
|
|
|
#include "codegen_ops.h"
|
|
|
|
|
#include "codegen_ops_helpers.h"
|
|
|
|
|
#include "codegen_ops_shift.h"
|
|
|
|
|
|
|
|
|
|
static uint32_t shift_common_8(ir_data_t *ir, uint32_t fetchdat, uint32_t op_pc, x86seg *target_seg, int count)
|
|
|
|
|
{
|
|
|
|
|
if ((fetchdat & 0xc0) == 0xc0)
|
|
|
|
|
{
|
|
|
|
|
int dest_reg = fetchdat & 7;
|
|
|
|
|
|
|
|
|
|
switch (fetchdat & 0x38)
|
|
|
|
|
{
|
|
|
|
|
case 0x00: /*ROL*/
|
|
|
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
|
|
|
uop_ROL_IMM(ir, IREG_8(dest_reg), IREG_8(dest_reg), count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROL8);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x08: /*ROR*/
|
|
|
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
|
|
|
uop_ROR_IMM(ir, IREG_8(dest_reg), IREG_8(dest_reg), count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROR8);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x20: case 0x30: /*SHL*/
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
|
|
|
|
|
uop_SHL_IMM(ir, IREG_8(dest_reg), IREG_8(dest_reg), count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op2, count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL8);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x28: /*SHR*/
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
|
|
|
|
|
uop_SHR_IMM(ir, IREG_8(dest_reg), IREG_8(dest_reg), count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op2, count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR8);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x38: /*SAR*/
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
|
|
|
|
|
uop_SAR_IMM(ir, IREG_8(dest_reg), IREG_8(dest_reg), count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op2, count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SAR8);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
switch (fetchdat & 0x38)
|
|
|
|
|
{
|
|
|
|
|
case 0x00: /*ROL*/
|
|
|
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
|
|
|
uop_ROL_IMM(ir, IREG_temp0_B, IREG_temp0_B, count);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_B);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROL8);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_B);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x08: /*ROR*/
|
|
|
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
|
|
|
uop_ROR_IMM(ir, IREG_temp0_B, IREG_temp0_B, count);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_B);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROR8);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_B);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x20: case 0x30: /*SHL*/
|
|
|
|
|
uop_SHL_IMM(ir, IREG_temp1_B, IREG_temp0_B, count);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_B);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_B);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op2, count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL8);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_B);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x28: /*SHR*/
|
|
|
|
|
uop_SHR_IMM(ir, IREG_temp1_B, IREG_temp0_B, count);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_B);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_B);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op2, count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR8);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_B);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x38: /*SAR*/
|
|
|
|
|
uop_SAR_IMM(ir, IREG_temp1_B, IREG_temp0_B, count);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_B);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_B);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op2, count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SAR8);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_B);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
codegen_flags_changed = 1;
|
|
|
|
|
return op_pc + 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static uint32_t shift_common_16(ir_data_t *ir, uint32_t fetchdat, uint32_t op_pc, x86seg *target_seg, int count)
|
|
|
|
|
{
|
|
|
|
|
if ((fetchdat & 0xc0) == 0xc0)
|
|
|
|
|
{
|
|
|
|
|
int dest_reg = fetchdat & 7;
|
|
|
|
|
|
|
|
|
|
switch (fetchdat & 0x38)
|
|
|
|
|
{
|
|
|
|
|
case 0x00: /*ROL*/
|
|
|
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
|
|
|
uop_ROL_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROL16);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x08: /*ROR*/
|
|
|
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
|
|
|
uop_ROR_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROR16);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x20: case 0x30: /*SHL*/
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
|
|
|
|
|
uop_SHL_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op2, count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL16);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x28: /*SHR*/
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
|
|
|
|
|
uop_SHR_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op2, count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR16);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x38: /*SAR*/
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
|
|
|
|
|
uop_SAR_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op2, count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SAR16);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
switch (fetchdat & 0x38)
|
|
|
|
|
{
|
|
|
|
|
case 0x00: /*ROL*/
|
|
|
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
|
|
|
uop_ROL_IMM(ir, IREG_temp0_W, IREG_temp0_W, count);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_W);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROL16);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_W);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x08: /*ROR*/
|
|
|
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
|
|
|
uop_ROR_IMM(ir, IREG_temp0_W, IREG_temp0_W, count);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_W);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROR16);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_W);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x20: case 0x30: /*SHL*/
|
|
|
|
|
uop_SHL_IMM(ir, IREG_temp1_W, IREG_temp0_W, count);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op2, count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL16);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x28: /*SHR*/
|
|
|
|
|
uop_SHR_IMM(ir, IREG_temp1_W, IREG_temp0_W, count);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op2, count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR16);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x38: /*SAR*/
|
|
|
|
|
uop_SAR_IMM(ir, IREG_temp1_W, IREG_temp0_W, count);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op2, count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SAR16);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
codegen_flags_changed = 1;
|
|
|
|
|
return op_pc + 1;
|
|
|
|
|
}
|
|
|
|
|
static uint32_t shift_common_32(ir_data_t *ir, uint32_t fetchdat, uint32_t op_pc, x86seg *target_seg, int count)
|
|
|
|
|
{
|
|
|
|
|
if ((fetchdat & 0xc0) == 0xc0)
|
|
|
|
|
{
|
|
|
|
|
int dest_reg = fetchdat & 7;
|
|
|
|
|
|
|
|
|
|
switch (fetchdat & 0x38)
|
|
|
|
|
{
|
|
|
|
|
case 0x00: /*ROL*/
|
|
|
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
|
|
|
uop_ROL_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROL32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x08: /*ROR*/
|
|
|
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
|
|
|
uop_ROR_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROR32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x20: case 0x30: /*SHL*/
|
|
|
|
|
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
|
|
|
|
|
uop_SHL_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op2, count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x28: /*SHR*/
|
|
|
|
|
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
|
|
|
|
|
uop_SHR_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op2, count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x38: /*SAR*/
|
|
|
|
|
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
|
|
|
|
|
uop_SAR_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op2, count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SAR32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
switch (fetchdat & 0x38)
|
|
|
|
|
{
|
|
|
|
|
case 0x00: /*ROL*/
|
|
|
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
|
|
|
uop_ROL_IMM(ir, IREG_temp0, IREG_temp0, count);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROL32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_temp0);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x08: /*ROR*/
|
|
|
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
|
|
|
uop_ROR_IMM(ir, IREG_temp0, IREG_temp0, count);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROR32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_temp0);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x20: case 0x30: /*SHL*/
|
|
|
|
|
uop_SHL_IMM(ir, IREG_temp1, IREG_temp0, count);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op2, count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_temp1);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x28: /*SHR*/
|
|
|
|
|
uop_SHR_IMM(ir, IREG_temp1, IREG_temp0, count);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op2, count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_temp1);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x38: /*SAR*/
|
|
|
|
|
uop_SAR_IMM(ir, IREG_temp1, IREG_temp0, count);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op2, count);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SAR32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_temp1);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
codegen_flags_changed = 1;
|
|
|
|
|
return op_pc + 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static uint32_t shift_common_variable_32(ir_data_t *ir, uint32_t fetchdat, uint32_t op_pc, x86seg *target_seg, int count_reg)
|
|
|
|
|
{
|
|
|
|
|
if ((fetchdat & 0xc0) == 0xc0)
|
|
|
|
|
{
|
|
|
|
|
int dest_reg = fetchdat & 7;
|
|
|
|
|
|
|
|
|
|
switch (fetchdat & 0x38)
|
|
|
|
|
{
|
|
|
|
|
case 0x00: /*ROL*/
|
|
|
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
|
|
|
uop_ROL(ir, IREG_32(dest_reg), IREG_32(dest_reg), count_reg);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROL32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x08: /*ROR*/
|
|
|
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
|
|
|
uop_ROR(ir, IREG_32(dest_reg), IREG_32(dest_reg), count_reg);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROR32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x20: case 0x30: /*SHL*/
|
|
|
|
|
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
|
|
|
|
|
uop_SHL(ir, IREG_32(dest_reg), IREG_32(dest_reg), count_reg);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op2, count_reg);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x28: /*SHR*/
|
|
|
|
|
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
|
|
|
|
|
uop_SHR(ir, IREG_32(dest_reg), IREG_32(dest_reg), count_reg);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op2, count_reg);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x38: /*SAR*/
|
|
|
|
|
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
|
|
|
|
|
uop_SAR(ir, IREG_32(dest_reg), IREG_32(dest_reg), count_reg);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op2, count_reg);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SAR32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
switch (fetchdat & 0x38)
|
|
|
|
|
{
|
|
|
|
|
case 0x00: /*ROL*/
|
|
|
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
|
|
|
uop_ROL(ir, IREG_temp0, IREG_temp0, count_reg);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROL32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_temp0);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x08: /*ROR*/
|
|
|
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
|
|
|
uop_ROR(ir, IREG_temp0, IREG_temp0, count_reg);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROR32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_temp0);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x20: case 0x30: /*SHL*/
|
|
|
|
|
uop_SHL(ir, IREG_temp1, IREG_temp0, count_reg);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op2, count_reg);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_temp1);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x28: /*SHR*/
|
|
|
|
|
uop_SHR(ir, IREG_temp1, IREG_temp0, count_reg);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op2, count_reg);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_temp1);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x38: /*SAR*/
|
|
|
|
|
uop_SAR(ir, IREG_temp1, IREG_temp0, count_reg);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op2, count_reg);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SAR32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_temp1);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
codegen_flags_changed = 1;
|
|
|
|
|
return op_pc + 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
uint32_t ropC0(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
|
|
|
|
|
{
|
|
|
|
|
x86seg *target_seg = NULL;
|
|
|
|
|
uint8_t imm;
|
|
|
|
|
|
|
|
|
|
if ((fetchdat & 0x30) == 0x10) /*RCL/RCR*/
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
codegen_mark_code_present(block, cs+op_pc, 1);
|
|
|
|
|
if ((fetchdat & 0xc0) != 0xc0)
|
|
|
|
|
{
|
|
|
|
|
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
|
|
|
|
|
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
|
|
|
|
|
codegen_check_seg_write(block, ir, target_seg);
|
|
|
|
|
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
|
|
|
|
|
}
|
|
|
|
|
imm = fastreadb(cs + op_pc + 1) & 0x1f;
|
|
|
|
|
codegen_mark_code_present(block, cs+op_pc+1, 1);
|
|
|
|
|
|
|
|
|
|
if (imm)
|
|
|
|
|
return shift_common_8(ir, fetchdat, op_pc, target_seg, imm) + 1;
|
|
|
|
|
return op_pc+1;
|
|
|
|
|
}
|
|
|
|
|
uint32_t ropC1_w(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
|
|
|
|
|
{
|
|
|
|
|
x86seg *target_seg = NULL;
|
|
|
|
|
uint8_t imm;
|
|
|
|
|
|
|
|
|
|
if ((fetchdat & 0x30) == 0x10) /*RCL/RCR*/
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
codegen_mark_code_present(block, cs+op_pc, 1);
|
|
|
|
|
if ((fetchdat & 0xc0) != 0xc0)
|
|
|
|
|
{
|
|
|
|
|
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
|
|
|
|
|
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
|
|
|
|
|
codegen_check_seg_write(block, ir, target_seg);
|
|
|
|
|
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
|
|
|
|
|
}
|
|
|
|
|
imm = fastreadb(cs + op_pc + 1) & 0x1f;
|
|
|
|
|
codegen_mark_code_present(block, cs+op_pc+1, 1);
|
|
|
|
|
|
|
|
|
|
if (imm)
|
|
|
|
|
return shift_common_16(ir, fetchdat, op_pc, target_seg, imm) + 1;
|
|
|
|
|
return op_pc+1;
|
|
|
|
|
}
|
|
|
|
|
uint32_t ropC1_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
|
|
|
|
|
{
|
|
|
|
|
x86seg *target_seg = NULL;
|
|
|
|
|
|
|
|
|
|
if ((fetchdat & 0x30) == 0x10) /*RCL/RCR*/
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
codegen_mark_code_present(block, cs+op_pc, 1);
|
|
|
|
|
if ((fetchdat & 0xc0) != 0xc0)
|
|
|
|
|
{
|
|
|
|
|
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
|
|
|
|
|
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
|
|
|
|
|
codegen_check_seg_write(block, ir, target_seg);
|
|
|
|
|
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
|
|
|
|
|
}
|
|
|
|
|
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
|
|
|
|
|
{
|
|
|
|
|
uint32_t new_pc;
|
|
|
|
|
int jump_uop;
|
|
|
|
|
|
|
|
|
|
LOAD_IMMEDIATE_FROM_RAM_8(block, ir, IREG_temp2, cs + op_pc + 1);
|
|
|
|
|
uop_AND_IMM(ir, IREG_temp2, IREG_temp2, 0x1f);
|
|
|
|
|
jump_uop = uop_CMP_IMM_JZ_DEST(ir, IREG_temp2, 0);
|
|
|
|
|
|
|
|
|
|
new_pc = shift_common_variable_32(ir, fetchdat, op_pc, target_seg, IREG_temp2) + 1;
|
|
|
|
|
uop_NOP_BARRIER(ir);
|
|
|
|
|
uop_set_jump_dest(ir, jump_uop);
|
|
|
|
|
return new_pc;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
uint8_t imm = fastreadb(cs + op_pc + 1) & 0x1f;
|
|
|
|
|
codegen_mark_code_present(block, cs+op_pc+1, 1);
|
|
|
|
|
|
|
|
|
|
if (imm)
|
|
|
|
|
return shift_common_32(ir, fetchdat, op_pc, target_seg, imm) + 1;
|
|
|
|
|
}
|
|
|
|
|
return op_pc+1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
uint32_t ropD0(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
|
|
|
|
|
{
|
|
|
|
|
x86seg *target_seg = NULL;
|
|
|
|
|
|
|
|
|
|
if ((fetchdat & 0x30) == 0x10) /*RCL/RCR*/
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
codegen_mark_code_present(block, cs+op_pc, 1);
|
|
|
|
|
if ((fetchdat & 0xc0) != 0xc0)
|
|
|
|
|
{
|
|
|
|
|
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
|
|
|
|
|
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
|
|
|
|
|
codegen_check_seg_write(block, ir, target_seg);
|
|
|
|
|
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return shift_common_8(ir, fetchdat, op_pc, target_seg, 1);
|
|
|
|
|
}
|
|
|
|
|
uint32_t ropD1_w(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
|
|
|
|
|
{
|
|
|
|
|
x86seg *target_seg = NULL;
|
|
|
|
|
|
|
|
|
|
if ((fetchdat & 0x30) == 0x10) /*RCL/RCR*/
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
codegen_mark_code_present(block, cs+op_pc, 1);
|
|
|
|
|
if ((fetchdat & 0xc0) != 0xc0)
|
|
|
|
|
{
|
|
|
|
|
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
|
|
|
|
|
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
|
|
|
|
|
codegen_check_seg_write(block, ir, target_seg);
|
|
|
|
|
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return shift_common_16(ir, fetchdat, op_pc, target_seg, 1);
|
|
|
|
|
}
|
|
|
|
|
uint32_t ropD1_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
|
|
|
|
|
{
|
|
|
|
|
x86seg *target_seg = NULL;
|
|
|
|
|
|
|
|
|
|
if ((fetchdat & 0x30) == 0x10) /*RCL/RCR*/
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
codegen_mark_code_present(block, cs+op_pc, 1);
|
|
|
|
|
if ((fetchdat & 0xc0) != 0xc0)
|
|
|
|
|
{
|
|
|
|
|
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
|
|
|
|
|
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
|
|
|
|
|
codegen_check_seg_write(block, ir, target_seg);
|
|
|
|
|
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return shift_common_32(ir, fetchdat, op_pc, target_seg, 1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
uint32_t ropD2(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
|
|
|
|
|
{
|
|
|
|
|
if ((fetchdat & 0x30) == 0x10) /*RCL/RCR*/
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
if (!(CL & 0x1f) || !block->ins)
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
uop_AND_IMM(ir, IREG_temp2, REG_ECX, 0x1f);
|
|
|
|
|
uop_CMP_IMM_JZ(ir, IREG_temp2, 0, codegen_exit_rout);
|
|
|
|
|
|
|
|
|
|
codegen_mark_code_present(block, cs+op_pc, 1);
|
|
|
|
|
if ((fetchdat & 0xc0) == 0xc0)
|
|
|
|
|
{
|
|
|
|
|
int dest_reg = fetchdat & 7;
|
|
|
|
|
|
|
|
|
|
switch (fetchdat & 0x38)
|
|
|
|
|
{
|
|
|
|
|
case 0x00: /*ROL*/
|
|
|
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
|
|
|
uop_ROL(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp2);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROL8);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x08: /*ROR*/
|
|
|
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
|
|
|
uop_ROR(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp2);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROR8);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x20: case 0x30: /*SHL*/
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
|
|
|
|
|
uop_SHL(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp2);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL8);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x28: /*SHR*/
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
|
|
|
|
|
uop_SHR(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp2);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR8);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x38: /*SAR*/
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
|
|
|
|
|
uop_SAR(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp2);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SAR8);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
x86seg *target_seg;
|
|
|
|
|
|
|
|
|
|
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
|
|
|
|
|
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
|
|
|
|
|
codegen_check_seg_write(block, ir, target_seg);
|
|
|
|
|
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
|
|
|
|
|
|
|
|
|
|
switch (fetchdat & 0x38)
|
|
|
|
|
{
|
|
|
|
|
case 0x00: /*ROL*/
|
|
|
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
|
|
|
uop_ROL(ir, IREG_temp0_B, IREG_temp0_B, IREG_temp2);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_B);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROL8);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_B);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x08: /*ROR*/
|
|
|
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
|
|
|
uop_ROR(ir, IREG_temp0_B, IREG_temp0_B, IREG_temp2);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_B);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROR8);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_B);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x20: case 0x30: /*SHL*/
|
|
|
|
|
uop_SHL(ir, IREG_temp1_B, IREG_temp0_B, IREG_temp2);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_B);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_B);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL8);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_B);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x28: /*SHR*/
|
|
|
|
|
uop_SHR(ir, IREG_temp1_B, IREG_temp0_B, IREG_temp2);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_B);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_B);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR8);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_B);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x38: /*SAR*/
|
|
|
|
|
uop_SAR(ir, IREG_temp1_B, IREG_temp0_B, IREG_temp2);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_B);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_B);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SAR8);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_B);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
codegen_flags_changed = 1;
|
|
|
|
|
return op_pc + 1;
|
|
|
|
|
}
|
|
|
|
|
uint32_t ropD3_w(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
|
|
|
|
|
{
|
|
|
|
|
if ((fetchdat & 0x30) == 0x10) /*RCL/RCR*/
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
if (!(CL & 0x1f) || !block->ins)
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
uop_AND_IMM(ir, IREG_temp2, REG_ECX, 0x1f);
|
|
|
|
|
uop_CMP_IMM_JZ(ir, IREG_temp2, 0, codegen_exit_rout);
|
|
|
|
|
|
|
|
|
|
codegen_mark_code_present(block, cs+op_pc, 1);
|
|
|
|
|
if ((fetchdat & 0xc0) == 0xc0)
|
|
|
|
|
{
|
|
|
|
|
int dest_reg = fetchdat & 7;
|
|
|
|
|
|
|
|
|
|
switch (fetchdat & 0x38)
|
|
|
|
|
{
|
|
|
|
|
case 0x00: /*ROL*/
|
|
|
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
|
|
|
uop_ROL(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp2);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROL16);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x08: /*ROR*/
|
|
|
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
|
|
|
uop_ROR(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp2);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROR16);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x20: case 0x30: /*SHL*/
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
|
|
|
|
|
uop_SHL(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp2);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL16);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x28: /*SHR*/
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
|
|
|
|
|
uop_SHR(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp2);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR16);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x38: /*SAR*/
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
|
|
|
|
|
uop_SAR(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp2);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SAR16);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
x86seg *target_seg;
|
|
|
|
|
|
|
|
|
|
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
|
|
|
|
|
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
|
|
|
|
|
codegen_check_seg_write(block, ir, target_seg);
|
|
|
|
|
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
|
|
|
|
|
|
|
|
|
|
switch (fetchdat & 0x38)
|
|
|
|
|
{
|
|
|
|
|
case 0x00: /*ROL*/
|
|
|
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
|
|
|
uop_ROL(ir, IREG_temp0_W, IREG_temp0_W, IREG_temp2);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_W);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROL16);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_W);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x08: /*ROR*/
|
|
|
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
|
|
|
uop_ROR(ir, IREG_temp0_W, IREG_temp0_W, IREG_temp2);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_W);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROR16);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_W);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x20: case 0x30: /*SHL*/
|
|
|
|
|
uop_SHL(ir, IREG_temp1_W, IREG_temp0_W, IREG_temp2);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL16);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x28: /*SHR*/
|
|
|
|
|
uop_SHR(ir, IREG_temp1_W, IREG_temp0_W, IREG_temp2);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR16);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x38: /*SAR*/
|
|
|
|
|
uop_SAR(ir, IREG_temp1_W, IREG_temp0_W, IREG_temp2);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SAR16);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
codegen_flags_changed = 1;
|
|
|
|
|
return op_pc + 1;
|
|
|
|
|
}
|
|
|
|
|
uint32_t ropD3_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
|
|
|
|
|
{
|
|
|
|
|
if ((fetchdat & 0x30) == 0x10) /*RCL/RCR*/
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
if (!(CL & 0x1f) || !block->ins)
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
uop_AND_IMM(ir, IREG_temp2, REG_ECX, 0x1f);
|
|
|
|
|
uop_CMP_IMM_JZ(ir, IREG_temp2, 0, codegen_exit_rout);
|
|
|
|
|
|
|
|
|
|
codegen_mark_code_present(block, cs+op_pc, 1);
|
|
|
|
|
if ((fetchdat & 0xc0) == 0xc0)
|
|
|
|
|
{
|
|
|
|
|
int dest_reg = fetchdat & 7;
|
|
|
|
|
|
|
|
|
|
switch (fetchdat & 0x38)
|
|
|
|
|
{
|
|
|
|
|
case 0x00: /*ROL*/
|
|
|
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
|
|
|
uop_ROL(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp2);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROL32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x08: /*ROR*/
|
|
|
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
|
|
|
uop_ROR(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp2);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROR32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x20: case 0x30: /*SHL*/
|
|
|
|
|
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
|
|
|
|
|
uop_SHL(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp2);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x28: /*SHR*/
|
|
|
|
|
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
|
|
|
|
|
uop_SHR(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp2);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x38: /*SAR*/
|
|
|
|
|
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
|
|
|
|
|
uop_SAR(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp2);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SAR32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
x86seg *target_seg;
|
|
|
|
|
|
|
|
|
|
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
|
|
|
|
|
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
|
|
|
|
|
codegen_check_seg_write(block, ir, target_seg);
|
|
|
|
|
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
|
|
|
|
|
|
|
|
|
|
switch (fetchdat & 0x38)
|
|
|
|
|
{
|
|
|
|
|
case 0x00: /*ROL*/
|
|
|
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
|
|
|
uop_ROL(ir, IREG_temp0, IREG_temp0, IREG_temp2);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROL32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_temp0);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x08: /*ROR*/
|
|
|
|
|
uop_CALL_FUNC(ir, flags_rebuild);
|
|
|
|
|
uop_ROR(ir, IREG_temp0, IREG_temp0, IREG_temp2);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROR32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_temp0);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x20: case 0x30: /*SHL*/
|
|
|
|
|
uop_SHL(ir, IREG_temp1, IREG_temp0, IREG_temp2);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_temp1);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x28: /*SHR*/
|
|
|
|
|
uop_SHR(ir, IREG_temp1, IREG_temp0, IREG_temp2);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_temp1);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x38: /*SAR*/
|
|
|
|
|
uop_SAR(ir, IREG_temp1, IREG_temp0, IREG_temp2);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
|
|
|
|
|
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SAR32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_temp1);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
codegen_flags_changed = 1;
|
|
|
|
|
return op_pc + 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
uint32_t ropSHLD_16_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
|
|
|
|
|
{
|
|
|
|
|
x86seg *target_seg = NULL;
|
|
|
|
|
int src_reg = (fetchdat >> 3) & 7;
|
|
|
|
|
uint8_t imm;
|
|
|
|
|
|
|
|
|
|
codegen_mark_code_present(block, cs+op_pc, 1);
|
|
|
|
|
if ((fetchdat & 0xc0) != 0xc0)
|
|
|
|
|
{
|
|
|
|
|
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
|
|
|
|
|
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
|
|
|
|
|
}
|
|
|
|
|
imm = fastreadb(cs + op_pc + 1) & 0x1f;
|
|
|
|
|
codegen_mark_code_present(block, cs+op_pc+1, 1);
|
|
|
|
|
|
|
|
|
|
if (!imm)
|
|
|
|
|
return op_pc+2;
|
|
|
|
|
|
|
|
|
|
if ((fetchdat & 0xc0) == 0xc0)
|
|
|
|
|
{
|
|
|
|
|
int dest_reg = fetchdat & 7;
|
|
|
|
|
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
|
|
|
|
|
uop_SHL_IMM(ir, IREG_temp0_W, IREG_16(dest_reg), imm);
|
|
|
|
|
uop_SHR_IMM(ir, IREG_temp1_W, IREG_16(src_reg), 16 - imm);
|
|
|
|
|
uop_OR(ir, IREG_16(dest_reg), IREG_temp0_W, IREG_temp1_W);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op2, imm);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL16);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
codegen_check_seg_write(block, ir, target_seg);
|
|
|
|
|
uop_MEM_LOAD_REG(ir, IREG_temp2_W, ireg_seg_base(target_seg), IREG_eaaddr);
|
|
|
|
|
|
|
|
|
|
uop_SHL_IMM(ir, IREG_temp0_W, IREG_temp2, imm);
|
|
|
|
|
uop_SHR_IMM(ir, IREG_temp1_W, IREG_16(src_reg), 16 - imm);
|
|
|
|
|
uop_OR(ir, IREG_temp0_W, IREG_temp0_W, IREG_temp1_W);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_W);
|
|
|
|
|
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_op1, IREG_temp2_W);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_W);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op2, imm);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL16);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return op_pc+2;
|
|
|
|
|
}
|
|
|
|
|
uint32_t ropSHLD_32_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
|
|
|
|
|
{
|
|
|
|
|
x86seg *target_seg = NULL;
|
|
|
|
|
int src_reg = (fetchdat >> 3) & 7;
|
|
|
|
|
uint8_t imm;
|
|
|
|
|
|
|
|
|
|
codegen_mark_code_present(block, cs+op_pc, 1);
|
|
|
|
|
if ((fetchdat & 0xc0) != 0xc0)
|
|
|
|
|
{
|
|
|
|
|
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
|
|
|
|
|
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
|
|
|
|
|
}
|
|
|
|
|
imm = fastreadb(cs + op_pc + 1) & 0x1f;
|
|
|
|
|
codegen_mark_code_present(block, cs+op_pc+1, 1);
|
|
|
|
|
|
|
|
|
|
if (!imm)
|
|
|
|
|
return op_pc+2;
|
|
|
|
|
|
|
|
|
|
if ((fetchdat & 0xc0) == 0xc0)
|
|
|
|
|
{
|
|
|
|
|
int dest_reg = fetchdat & 7;
|
|
|
|
|
|
|
|
|
|
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
|
|
|
|
|
uop_SHL_IMM(ir, IREG_temp0, IREG_32(dest_reg), imm);
|
|
|
|
|
uop_SHR_IMM(ir, IREG_temp1, IREG_32(src_reg), 32 - imm);
|
|
|
|
|
uop_OR(ir, IREG_32(dest_reg), IREG_temp0, IREG_temp1);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op2, imm);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
codegen_check_seg_write(block, ir, target_seg);
|
|
|
|
|
uop_MEM_LOAD_REG(ir, IREG_temp2, ireg_seg_base(target_seg), IREG_eaaddr);
|
|
|
|
|
|
|
|
|
|
uop_SHL_IMM(ir, IREG_temp0, IREG_temp2, imm);
|
|
|
|
|
uop_SHR_IMM(ir, IREG_temp1, IREG_32(src_reg), 32 - imm);
|
|
|
|
|
uop_OR(ir, IREG_temp0, IREG_temp0, IREG_temp1);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0);
|
|
|
|
|
|
|
|
|
|
uop_MOV(ir, IREG_flags_op1, IREG_temp2);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_temp0);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op2, imm);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL32);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return op_pc+2;
|
|
|
|
|
}
|
|
|
|
|
uint32_t ropSHRD_16_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
|
|
|
|
|
{
|
|
|
|
|
x86seg *target_seg = NULL;
|
|
|
|
|
int src_reg = (fetchdat >> 3) & 7;
|
|
|
|
|
uint8_t imm;
|
|
|
|
|
|
|
|
|
|
codegen_mark_code_present(block, cs+op_pc, 1);
|
|
|
|
|
if ((fetchdat & 0xc0) != 0xc0)
|
|
|
|
|
{
|
|
|
|
|
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
|
|
|
|
|
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
|
|
|
|
|
}
|
|
|
|
|
imm = fastreadb(cs + op_pc + 1) & 0x1f;
|
|
|
|
|
codegen_mark_code_present(block, cs+op_pc+1, 1);
|
|
|
|
|
|
|
|
|
|
if (!imm)
|
|
|
|
|
return op_pc+2;
|
|
|
|
|
|
|
|
|
|
if ((fetchdat & 0xc0) == 0xc0)
|
|
|
|
|
{
|
|
|
|
|
int dest_reg = fetchdat & 7;
|
|
|
|
|
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
|
|
|
|
|
uop_SHR_IMM(ir, IREG_temp0_W, IREG_16(dest_reg), imm);
|
|
|
|
|
uop_SHL_IMM(ir, IREG_temp1_W, IREG_16(src_reg), 16 - imm);
|
|
|
|
|
uop_OR(ir, IREG_16(dest_reg), IREG_temp0_W, IREG_temp1_W);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op2, imm);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR16);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
codegen_check_seg_write(block, ir, target_seg);
|
|
|
|
|
uop_MEM_LOAD_REG(ir, IREG_temp2_W, ireg_seg_base(target_seg), IREG_eaaddr);
|
|
|
|
|
|
|
|
|
|
uop_SHR_IMM(ir, IREG_temp0_W, IREG_temp2, imm);
|
|
|
|
|
uop_SHL_IMM(ir, IREG_temp1_W, IREG_16(src_reg), 16 - imm);
|
|
|
|
|
uop_OR(ir, IREG_temp0_W, IREG_temp0_W, IREG_temp1_W);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_W);
|
|
|
|
|
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_op1, IREG_temp2_W);
|
|
|
|
|
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_W);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op2, imm);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR16);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return op_pc+2;
|
|
|
|
|
}
|
|
|
|
|
uint32_t ropSHRD_32_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
|
|
|
|
|
{
|
|
|
|
|
x86seg *target_seg = NULL;
|
|
|
|
|
int src_reg = (fetchdat >> 3) & 7;
|
|
|
|
|
uint8_t imm;
|
|
|
|
|
|
|
|
|
|
codegen_mark_code_present(block, cs+op_pc, 1);
|
|
|
|
|
if ((fetchdat & 0xc0) != 0xc0)
|
|
|
|
|
{
|
|
|
|
|
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
|
|
|
|
|
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
|
|
|
|
|
}
|
|
|
|
|
imm = fastreadb(cs + op_pc + 1) & 0x1f;
|
|
|
|
|
codegen_mark_code_present(block, cs+op_pc+1, 1);
|
|
|
|
|
|
|
|
|
|
if (!imm)
|
|
|
|
|
return op_pc+2;
|
|
|
|
|
|
|
|
|
|
if ((fetchdat & 0xc0) == 0xc0)
|
|
|
|
|
{
|
|
|
|
|
int dest_reg = fetchdat & 7;
|
|
|
|
|
|
|
|
|
|
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
|
|
|
|
|
uop_SHR_IMM(ir, IREG_temp0, IREG_32(dest_reg), imm);
|
|
|
|
|
uop_SHL_IMM(ir, IREG_temp1, IREG_32(src_reg), 32 - imm);
|
|
|
|
|
uop_OR(ir, IREG_32(dest_reg), IREG_temp0, IREG_temp1);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op2, imm);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR32);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
codegen_check_seg_write(block, ir, target_seg);
|
|
|
|
|
uop_MEM_LOAD_REG(ir, IREG_temp2, ireg_seg_base(target_seg), IREG_eaaddr);
|
|
|
|
|
|
|
|
|
|
uop_SHR_IMM(ir, IREG_temp0, IREG_temp2, imm);
|
|
|
|
|
uop_SHL_IMM(ir, IREG_temp1, IREG_32(src_reg), 32 - imm);
|
|
|
|
|
uop_OR(ir, IREG_temp0, IREG_temp0, IREG_temp1);
|
|
|
|
|
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0);
|
|
|
|
|
|
|
|
|
|
uop_MOV(ir, IREG_flags_op1, IREG_temp2);
|
|
|
|
|
uop_MOV(ir, IREG_flags_res, IREG_temp0);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op2, imm);
|
|
|
|
|
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR32);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return op_pc+2;
|
|
|
|
|
}
|