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724c5699caaa6e2668b8cfe61782fc5b46e1a19d
86Box/src/x86_ops_mov_ctrl.h

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7.3 KiB
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Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
static int opMOV_r_CRx_a16(uint32_t fetchdat)
{
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
{
pclog("Can't load from CRx\n");
x86gpf(NULL, 0);
return 1;
}
fetch_ea_16(fetchdat);
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
switch (cpu_reg)
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
{
case 0:
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
cpu_state.regs[cpu_rm].l = cr0;
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
if (is486)
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
cpu_state.regs[cpu_rm].l |= 0x10; /*ET hardwired on 486*/
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
break;
case 2:
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
cpu_state.regs[cpu_rm].l = cr2;
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
break;
case 3:
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
cpu_state.regs[cpu_rm].l = cr3;
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
break;
case 4:
if (cpu_hasCR4)
{
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
cpu_state.regs[cpu_rm].l = cr4;
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
break;
}
default:
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
pclog("Bad read of CR%i %i\n",rmdat&7,cpu_reg);
Rewrote the disc sector poller again for simplified code and more accuracy; Floppy formats are now accurately timed and also more accurately implemented; Applied all mainline PCem commits.
2016-08-20 03:40:12 +02:00
cpu_state.pc = cpu_state.oldpc;
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
x86illegal();
break;
}
CLOCK_CYCLES(6);
return 0;
}
static int opMOV_r_CRx_a32(uint32_t fetchdat)
{
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
{
pclog("Can't load from CRx\n");
x86gpf(NULL, 0);
return 1;
}
fetch_ea_32(fetchdat);
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
switch (cpu_reg)
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
{
case 0:
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
cpu_state.regs[cpu_rm].l = cr0;
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
if (is486)
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
cpu_state.regs[cpu_rm].l |= 0x10; /*ET hardwired on 486*/
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
break;
case 2:
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
cpu_state.regs[cpu_rm].l = cr2;
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
break;
case 3:
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
cpu_state.regs[cpu_rm].l = cr3;
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
break;
case 4:
if (cpu_hasCR4)
{
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
cpu_state.regs[cpu_rm].l = cr4;
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
break;
}
default:
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
pclog("Bad read of CR%i %i\n",rmdat&7,cpu_reg);
Rewrote the disc sector poller again for simplified code and more accuracy; Floppy formats are now accurately timed and also more accurately implemented; Applied all mainline PCem commits.
2016-08-20 03:40:12 +02:00
cpu_state.pc = cpu_state.oldpc;
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
x86illegal();
break;
}
CLOCK_CYCLES(6);
return 0;
}
static int opMOV_r_DRx_a16(uint32_t fetchdat)
{
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
{
pclog("Can't load from DRx\n");
x86gpf(NULL, 0);
return 1;
}
fetch_ea_16(fetchdat);
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
cpu_state.regs[cpu_rm].l = dr[cpu_reg];
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
CLOCK_CYCLES(6);
return 0;
}
static int opMOV_r_DRx_a32(uint32_t fetchdat)
{
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
{
pclog("Can't load from DRx\n");
x86gpf(NULL, 0);
return 1;
}
fetch_ea_32(fetchdat);
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
cpu_state.regs[cpu_rm].l = dr[cpu_reg];
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
CLOCK_CYCLES(6);
return 0;
}
static int opMOV_CRx_r_a16(uint32_t fetchdat)
{
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
{
pclog("Can't load CRx\n");
x86gpf(NULL,0);
return 1;
}
fetch_ea_16(fetchdat);
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
switch (cpu_reg)
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
{
case 0:
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000001)
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
flushmmucache();
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
cr0 = cpu_state.regs[cpu_rm].l;
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
if (cpu_16bitbus)
cr0 |= 0x10;
if (!(cr0 & 0x80000000))
mmu_perm=4;
break;
case 2:
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
cr2 = cpu_state.regs[cpu_rm].l;
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
break;
case 3:
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
cr3 = cpu_state.regs[cpu_rm].l;
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
flushmmucache();
break;
case 4:
if (cpu_hasCR4)
{
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
cr4 = cpu_state.regs[cpu_rm].l & cpu_CR4_mask;
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
break;
}
default:
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
pclog("Bad load CR%i\n", cpu_reg);
Rewrote the disc sector poller again for simplified code and more accuracy; Floppy formats are now accurately timed and also more accurately implemented; Applied all mainline PCem commits.
2016-08-20 03:40:12 +02:00
cpu_state.pc = cpu_state.oldpc;
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
x86illegal();
break;
}
CLOCK_CYCLES(10);
return 0;
}
static int opMOV_CRx_r_a32(uint32_t fetchdat)
{
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
{
pclog("Can't load CRx\n");
x86gpf(NULL,0);
return 1;
}
fetch_ea_32(fetchdat);
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
switch (cpu_reg)
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
{
case 0:
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
if ((cpu_state.regs[cpu_rm].l ^ cr0) & 0x80000001)
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
flushmmucache();
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
cr0 = cpu_state.regs[cpu_rm].l;
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
if (cpu_16bitbus)
cr0 |= 0x10;
if (!(cr0 & 0x80000000))
mmu_perm=4;
break;
case 2:
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
cr2 = cpu_state.regs[cpu_rm].l;
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
break;
case 3:
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
cr3 = cpu_state.regs[cpu_rm].l;
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
flushmmucache();
break;
case 4:
if (cpu_hasCR4)
{
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
cr4 = cpu_state.regs[cpu_rm].l & cpu_CR4_mask;
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
break;
}
default:
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
pclog("Bad load CR%i\n", cpu_reg);
Rewrote the disc sector poller again for simplified code and more accuracy; Floppy formats are now accurately timed and also more accurately implemented; Applied all mainline PCem commits.
2016-08-20 03:40:12 +02:00
cpu_state.pc = cpu_state.oldpc;
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
x86illegal();
break;
}
CLOCK_CYCLES(10);
return 0;
}
static int opMOV_DRx_r_a16(uint32_t fetchdat)
{
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
{
pclog("Can't load DRx\n");
x86gpf(NULL, 0);
return 1;
}
fetch_ea_16(fetchdat);
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
dr[cpu_reg] = cpu_state.regs[cpu_rm].l;
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
CLOCK_CYCLES(6);
return 0;
}
static int opMOV_DRx_r_a32(uint32_t fetchdat)
{
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
{
pclog("Can't load DRx\n");
x86gpf(NULL, 0);
return 1;
}
fetch_ea_16(fetchdat);
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
dr[cpu_reg] = cpu_state.regs[cpu_rm].l;
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
CLOCK_CYCLES(6);
return 0;
}
static int opMOV_r_TRx_a16(uint32_t fetchdat)
{
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
{
pclog("Can't load from TRx\n");
x86gpf(NULL, 0);
return 1;
}
fetch_ea_16(fetchdat);
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
cpu_state.regs[cpu_rm].l = 0;
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
CLOCK_CYCLES(6);
return 0;
}
static int opMOV_r_TRx_a32(uint32_t fetchdat)
{
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
{
pclog("Can't load from TRx\n");
x86gpf(NULL, 0);
return 1;
}
fetch_ea_32(fetchdat);
Applied both mainline PCem commits; Fixed the RTL8029AS again (one of my "fixes" broke it); RTL8029AS PCI register 4 is now written to; Added incomplete (and currently commented out) emulation of the AWE64 PCI; Replaced sector-based floppy emulation with more accurate code.
2016-08-15 01:34:46 +02:00
cpu_state.regs[cpu_rm].l = 0;
Initial submission of the PCem-Experimental source code.
2016-06-26 00:34:39 +02:00
CLOCK_CYCLES(6);
return 0;
}
static int opMOV_TRx_r_a16(uint32_t fetchdat)
{
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
{
pclog("Can't load TRx\n");
x86gpf(NULL, 0);
return 1;
}
fetch_ea_16(fetchdat);
CLOCK_CYCLES(6);
return 0;
}
static int opMOV_TRx_r_a32(uint32_t fetchdat)
{
if ((CPL || (eflags&VM_FLAG)) && (cr0&1))
{
pclog("Can't load TRx\n");
x86gpf(NULL, 0);
return 1;
}
fetch_ea_16(fetchdat);
CLOCK_CYCLES(6);
return 0;
}
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