2017-08-21 02:15:21 +02:00
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/*um8669f :
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aa to 108 unlocks
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next 108 write is register select (Cx?)
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data read/write to 109
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55 to 108 locks
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C1
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bit 7 - enable PnP registers
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PnP registers :
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07 - device :
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0 = FDC
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1 = COM1
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2 = COM2
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3 = LPT1
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5 = Game port
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30 - enable
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60/61 - addr
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70 - IRQ
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74 - DMA*/
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2017-09-25 04:31:20 -04:00
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#include <stdio.h>
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#include <stdint.h>
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#include <string.h>
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#include <wchar.h>
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2017-10-17 01:59:09 -04:00
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#include "86box.h"
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2018-01-17 18:43:36 +01:00
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#include "device.h"
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2017-08-21 02:15:21 +02:00
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#include "io.h"
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2017-11-05 01:57:04 -05:00
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#include "pci.h"
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2017-08-21 02:15:21 +02:00
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#include "lpt.h"
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#include "serial.h"
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2017-09-04 01:52:29 -04:00
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#include "floppy/fdd.h"
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#include "floppy/fdc.h"
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#include "sio.h"
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2017-08-21 02:15:21 +02:00
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2017-08-24 01:14:39 -04:00
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2017-08-21 02:15:21 +02:00
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typedef struct um8669f_t
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{
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int locked;
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int cur_reg_108;
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uint8_t regs_108[256];
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int cur_reg;
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int cur_device;
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struct
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{
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int enable;
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uint16_t addr;
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int irq;
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int dma;
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} dev[8];
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2018-01-17 18:43:36 +01:00
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fdc_t *fdc;
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2017-08-21 02:15:21 +02:00
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} um8669f_t;
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2017-08-24 01:14:39 -04:00
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2017-08-21 02:15:21 +02:00
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static um8669f_t um8669f_global;
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2017-08-24 01:14:39 -04:00
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2017-08-21 02:15:21 +02:00
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#define DEV_FDC 0
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#define DEV_COM1 1
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#define DEV_COM2 2
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#define DEV_LPT1 3
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#define DEV_GAME 5
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#define REG_DEVICE 0x07
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#define REG_ENABLE 0x30
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#define REG_ADDRHI 0x60
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#define REG_ADDRLO 0x61
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#define REG_IRQ 0x70
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#define REG_DMA 0x74
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2017-08-24 01:14:39 -04:00
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2017-08-21 02:15:21 +02:00
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void um8669f_pnp_write(uint16_t port, uint8_t val, void *p)
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{
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um8669f_t *um8669f = (um8669f_t *)p;
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uint8_t valxor = 0;
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if (port == 0x279)
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um8669f->cur_reg = val;
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else
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{
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if (um8669f->cur_reg == REG_DEVICE)
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um8669f->cur_device = val & 7;
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else
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{
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/* pclog("Write UM8669F %02x [%02x] %02x\n", um8669f->cur_reg, um8669f->cur_device, val); */
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switch (um8669f->cur_reg)
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{
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case REG_ENABLE:
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valxor = um8669f->dev[um8669f->cur_device].enable ^ val;
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um8669f->dev[um8669f->cur_device].enable = val;
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break;
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case REG_ADDRLO:
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valxor = (um8669f->dev[um8669f->cur_device].addr & 0xff) ^ val;
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um8669f->dev[um8669f->cur_device].addr = (um8669f->dev[um8669f->cur_device].addr & 0xff00) | val;
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break;
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case REG_ADDRHI:
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valxor = ((um8669f->dev[um8669f->cur_device].addr >> 8) & 0xff) ^ val;
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um8669f->dev[um8669f->cur_device].addr = (um8669f->dev[um8669f->cur_device].addr & 0x00ff) | (val << 8);
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break;
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case REG_IRQ:
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valxor = um8669f->dev[um8669f->cur_device].irq ^ val;
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um8669f->dev[um8669f->cur_device].irq = val;
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break;
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case REG_DMA:
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valxor = um8669f->dev[um8669f->cur_device].dma ^ val;
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um8669f->dev[um8669f->cur_device].dma = val;
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break;
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default:
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valxor = 0;
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break;
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}
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/* pclog("UM8669F: Write %02X to [%02X][%02X]...\n", val, um8669f->cur_device, um8669f->cur_reg); */
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switch (um8669f->cur_device)
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{
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case DEV_FDC:
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if ((um8669f->cur_reg == REG_ENABLE) && valxor)
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{
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2018-01-17 18:43:36 +01:00
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fdc_remove(um8669f_global.fdc);
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2017-08-21 02:15:21 +02:00
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if (um8669f->dev[DEV_FDC].enable & 1)
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2018-01-17 18:43:36 +01:00
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fdc_set_base(um8669f_global.fdc, 0x03f0);
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2017-08-21 02:15:21 +02:00
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}
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break;
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case DEV_COM1:
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if (valxor)
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{
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serial_remove(1);
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if (um8669f->dev[DEV_COM1].enable & 1)
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serial_setup(1, um8669f->dev[DEV_COM1].addr, um8669f->dev[DEV_COM1].irq);
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}
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break;
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case DEV_COM2:
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if (valxor)
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{
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serial_remove(2);
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if (um8669f->dev[DEV_COM2].enable & 1)
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serial_setup(2, um8669f->dev[DEV_COM2].addr, um8669f->dev[DEV_COM2].irq);
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}
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break;
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case DEV_LPT1:
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if (valxor)
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{
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lpt1_remove();
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if (um8669f->dev[DEV_LPT1].enable & 1)
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lpt1_init(um8669f->dev[DEV_LPT1].addr);
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}
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break;
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}
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}
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}
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}
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2017-08-24 01:14:39 -04:00
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2017-08-21 02:15:21 +02:00
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uint8_t um8669f_pnp_read(uint16_t port, void *p)
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{
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um8669f_t *um8669f = (um8669f_t *)p;
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/* pclog("Read UM8669F %02x\n", um8669f->cur_reg); */
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switch (um8669f->cur_reg)
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{
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case REG_DEVICE:
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return um8669f->cur_device;
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case REG_ENABLE:
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return um8669f->dev[um8669f->cur_device].enable;
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case REG_ADDRLO:
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return um8669f->dev[um8669f->cur_device].addr & 0xff;
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case REG_ADDRHI:
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return um8669f->dev[um8669f->cur_device].addr >> 8;
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case REG_IRQ:
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return um8669f->dev[um8669f->cur_device].irq;
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case REG_DMA:
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return um8669f->dev[um8669f->cur_device].dma;
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}
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return 0xff;
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}
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2017-08-24 01:14:39 -04:00
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2017-08-21 02:15:21 +02:00
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void um8669f_write(uint16_t port, uint8_t val, void *p)
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{
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um8669f_t *um8669f = (um8669f_t *)p;
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if (um8669f->locked)
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{
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if (port == 0x108 && val == 0xaa)
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um8669f->locked = 0;
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}
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else
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{
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if (port == 0x108)
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{
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if (val == 0x55)
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um8669f->locked = 1;
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else
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um8669f->cur_reg_108 = val;
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}
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else
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{
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/* pclog("Write UM8669f register %02x %02x %04x:%04x %i\n", um8669f_curreg, val, CS,cpu_state.pc, ins); */
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um8669f->regs_108[um8669f->cur_reg_108] = val;
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io_removehandler(0x0279, 0x0001, NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, um8669f);
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io_removehandler(0x0a79, 0x0001, NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, um8669f);
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io_removehandler(0x03e3, 0x0001, um8669f_pnp_read, NULL, NULL, NULL, NULL, NULL, um8669f);
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if (um8669f->regs_108[0xc1] & 0x80)
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{
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io_sethandler(0x0279, 0x0001, NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, um8669f);
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io_sethandler(0x0a79, 0x0001, NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, um8669f);
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io_sethandler(0x03e3, 0x0001, um8669f_pnp_read, NULL, NULL, NULL, NULL, NULL, um8669f);
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}
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}
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}
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}
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2017-08-24 01:14:39 -04:00
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2017-08-21 02:15:21 +02:00
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uint8_t um8669f_read(uint16_t port, void *p)
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{
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um8669f_t *um8669f = (um8669f_t *)p;
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/* pclog("um8669f_read : port=%04x reg %02X locked=%i %02x\n", port, um8669f_curreg, um8669f_locked, um8669f_regs[um8669f_curreg]); */
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if (um8669f->locked)
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return 0xff;
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if (port == 0x108)
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return um8669f->cur_reg_108; /*???*/
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else
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return um8669f->regs_108[um8669f->cur_reg_108];
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}
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2017-08-24 01:14:39 -04:00
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2017-08-21 02:15:21 +02:00
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void um8669f_reset(void)
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{
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2018-01-20 13:56:42 +01:00
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fdc_t *temp_fdc = um8669f_global.fdc;
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2018-01-17 18:43:36 +01:00
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fdc_reset(um8669f_global.fdc);
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2017-08-21 02:15:21 +02:00
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serial_remove(1);
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serial_setup(1, SERIAL1_ADDR, SERIAL1_IRQ);
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serial_remove(2);
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serial_setup(2, SERIAL2_ADDR, SERIAL2_IRQ);
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lpt2_remove();
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lpt1_remove();
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lpt1_init(0x378);
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memset(&um8669f_global, 0, sizeof(um8669f_t));
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2018-01-20 13:56:42 +01:00
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um8669f_global.fdc = temp_fdc;
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2017-08-21 02:15:21 +02:00
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um8669f_global.locked = 1;
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io_removehandler(0x0279, 0x0001, NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, &um8669f_global);
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io_removehandler(0x0a79, 0x0001, NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, &um8669f_global);
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io_removehandler(0x03e3, 0x0001, um8669f_pnp_read, NULL, NULL, NULL, NULL, NULL, &um8669f_global);
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um8669f_global.dev[DEV_FDC].enable = 1;
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um8669f_global.dev[DEV_FDC].addr = 0x03f0;
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um8669f_global.dev[DEV_FDC].irq = 6;
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um8669f_global.dev[DEV_FDC].dma = 2;
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um8669f_global.dev[DEV_COM1].enable = 1;
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um8669f_global.dev[DEV_COM1].addr = 0x03f8;
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um8669f_global.dev[DEV_COM1].irq = 4;
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um8669f_global.dev[DEV_COM2].enable = 1;
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um8669f_global.dev[DEV_COM2].addr = 0x02f8;
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um8669f_global.dev[DEV_COM2].irq = 3;
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um8669f_global.dev[DEV_LPT1].enable = 1;
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um8669f_global.dev[DEV_LPT1].addr = 0x0378;
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um8669f_global.dev[DEV_LPT1].irq = 7;
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}
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2017-08-24 01:14:39 -04:00
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void um8669f_init(void)
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2017-08-21 02:15:21 +02:00
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{
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2018-01-17 18:43:36 +01:00
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um8669f_global.fdc = device_add(&fdc_at_device);
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2017-08-21 02:15:21 +02:00
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io_sethandler(0x0108, 0x0002, um8669f_read, NULL, NULL, um8669f_write, NULL, NULL, &um8669f_global);
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um8669f_reset();
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pci_reset_handler.super_io_reset = um8669f_reset;
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}
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