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86Box/src/cpu/x86_ops_arith.h

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clang format in cpu
2022-11-19 10:40:32 -05:00
#define OP_ARITH(name, operation, setflags, flagops, gettempc) \
static int op##name##_b_rmw_a16(uint32_t fetchdat) \
{ \
uint8_t dst; \
uint8_t src; \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
fetch_ea_16(fetchdat); \
if (cpu_mod == 3) { \
dst = getr8(cpu_rm); \
src = getr8(cpu_reg); \
setflags##8 flagops; \
setr8(cpu_rm, operation); \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 0); \
} else { \
SEG_CHECK_WRITE(cpu_state.ea_seg); \
dst = geteab(); \
if (cpu_state.abrt) \
return 1; \
src = getr8(cpu_reg); \
seteab(operation); \
if (cpu_state.abrt) \
return 1; \
setflags##8 flagops; \
CLOCK_CYCLES(timing_mr); \
PREFETCH_RUN(timing_mr, 2, rmdat, 1, 0, 1, 0, 0); \
} \
return 0; \
} \
static int op##name##_b_rmw_a32(uint32_t fetchdat) \
{ \
uint8_t dst; \
uint8_t src; \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
fetch_ea_32(fetchdat); \
if (cpu_mod == 3) { \
dst = getr8(cpu_rm); \
src = getr8(cpu_reg); \
setflags##8 flagops; \
setr8(cpu_rm, operation); \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 1); \
} else { \
SEG_CHECK_WRITE(cpu_state.ea_seg); \
dst = geteab(); \
if (cpu_state.abrt) \
return 1; \
src = getr8(cpu_reg); \
seteab(operation); \
if (cpu_state.abrt) \
return 1; \
setflags##8 flagops; \
CLOCK_CYCLES(timing_mr); \
PREFETCH_RUN(timing_mr, 2, rmdat, 1, 0, 1, 0, 1); \
} \
return 0; \
} \
\
static int op##name##_w_rmw_a16(uint32_t fetchdat) \
{ \
uint16_t dst; \
uint16_t src; \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
fetch_ea_16(fetchdat); \
if (cpu_mod == 3) { \
dst = cpu_state.regs[cpu_rm].w; \
src = cpu_state.regs[cpu_reg].w; \
setflags##16 flagops; \
cpu_state.regs[cpu_rm].w = operation; \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 0); \
} else { \
SEG_CHECK_WRITE(cpu_state.ea_seg); \
dst = geteaw(); \
if (cpu_state.abrt) \
return 1; \
src = cpu_state.regs[cpu_reg].w; \
seteaw(operation); \
if (cpu_state.abrt) \
return 1; \
setflags##16 flagops; \
CLOCK_CYCLES(timing_mr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 1, 0, 1, 0, 0); \
} \
return 0; \
} \
static int op##name##_w_rmw_a32(uint32_t fetchdat) \
{ \
uint16_t dst; \
uint16_t src; \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
fetch_ea_32(fetchdat); \
if (cpu_mod == 3) { \
dst = cpu_state.regs[cpu_rm].w; \
src = cpu_state.regs[cpu_reg].w; \
setflags##16 flagops; \
cpu_state.regs[cpu_rm].w = operation; \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 1); \
} else { \
SEG_CHECK_WRITE(cpu_state.ea_seg); \
dst = geteaw(); \
if (cpu_state.abrt) \
return 1; \
src = cpu_state.regs[cpu_reg].w; \
seteaw(operation); \
if (cpu_state.abrt) \
return 1; \
setflags##16 flagops; \
CLOCK_CYCLES(timing_mr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 1, 0, 1, 0, 1); \
} \
return 0; \
} \
\
static int op##name##_l_rmw_a16(uint32_t fetchdat) \
{ \
uint32_t dst; \
uint32_t src; \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
fetch_ea_16(fetchdat); \
if (cpu_mod == 3) { \
dst = cpu_state.regs[cpu_rm].l; \
src = cpu_state.regs[cpu_reg].l; \
setflags##32 flagops; \
cpu_state.regs[cpu_rm].l = operation; \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 0); \
} else { \
SEG_CHECK_WRITE(cpu_state.ea_seg); \
dst = geteal(); \
if (cpu_state.abrt) \
return 1; \
src = cpu_state.regs[cpu_reg].l; \
seteal(operation); \
if (cpu_state.abrt) \
return 1; \
setflags##32 flagops; \
CLOCK_CYCLES(timing_mr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 1, 0, 1, 0); \
} \
return 0; \
} \
static int op##name##_l_rmw_a32(uint32_t fetchdat) \
{ \
uint32_t dst; \
uint32_t src; \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
fetch_ea_32(fetchdat); \
if (cpu_mod == 3) { \
dst = cpu_state.regs[cpu_rm].l; \
src = cpu_state.regs[cpu_reg].l; \
setflags##32 flagops; \
cpu_state.regs[cpu_rm].l = operation; \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 1); \
} else { \
SEG_CHECK_WRITE(cpu_state.ea_seg); \
dst = geteal(); \
if (cpu_state.abrt) \
return 1; \
src = cpu_state.regs[cpu_reg].l; \
seteal(operation); \
if (cpu_state.abrt) \
return 1; \
setflags##32 flagops; \
CLOCK_CYCLES(timing_mr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 1, 0, 1, 1); \
} \
return 0; \
} \
\
static int op##name##_b_rm_a16(uint32_t fetchdat) \
{ \
uint8_t dst, src; \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
fetch_ea_16(fetchdat); \
if (cpu_mod != 3) \
SEG_CHECK_READ(cpu_state.ea_seg); \
dst = getr8(cpu_reg); \
src = geteab(); \
if (cpu_state.abrt) \
return 1; \
setflags##8 flagops; \
setr8(cpu_reg, operation); \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 0); \
return 0; \
} \
static int op##name##_b_rm_a32(uint32_t fetchdat) \
{ \
uint8_t dst, src; \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
fetch_ea_32(fetchdat); \
if (cpu_mod != 3) \
SEG_CHECK_READ(cpu_state.ea_seg); \
dst = getr8(cpu_reg); \
src = geteab(); \
if (cpu_state.abrt) \
return 1; \
setflags##8 flagops; \
setr8(cpu_reg, operation); \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 1); \
return 0; \
} \
\
static int op##name##_w_rm_a16(uint32_t fetchdat) \
{ \
uint16_t dst, src; \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
fetch_ea_16(fetchdat); \
if (cpu_mod != 3) \
SEG_CHECK_READ(cpu_state.ea_seg); \
dst = cpu_state.regs[cpu_reg].w; \
src = geteaw(); \
if (cpu_state.abrt) \
return 1; \
setflags##16 flagops; \
cpu_state.regs[cpu_reg].w = operation; \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 0); \
return 0; \
} \
static int op##name##_w_rm_a32(uint32_t fetchdat) \
{ \
uint16_t dst, src; \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
fetch_ea_32(fetchdat); \
if (cpu_mod != 3) \
SEG_CHECK_READ(cpu_state.ea_seg); \
dst = cpu_state.regs[cpu_reg].w; \
src = geteaw(); \
if (cpu_state.abrt) \
return 1; \
setflags##16 flagops; \
cpu_state.regs[cpu_reg].w = operation; \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 1); \
return 0; \
} \
\
static int op##name##_l_rm_a16(uint32_t fetchdat) \
{ \
uint32_t dst, src; \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
fetch_ea_16(fetchdat); \
if (cpu_mod != 3) \
SEG_CHECK_READ(cpu_state.ea_seg); \
dst = cpu_state.regs[cpu_reg].l; \
src = geteal(); \
if (cpu_state.abrt) \
return 1; \
setflags##32 flagops; \
cpu_state.regs[cpu_reg].l = operation; \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml); \
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, 0, 0); \
return 0; \
} \
static int op##name##_l_rm_a32(uint32_t fetchdat) \
{ \
uint32_t dst, src; \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
fetch_ea_32(fetchdat); \
if (cpu_mod != 3) \
SEG_CHECK_READ(cpu_state.ea_seg); \
dst = cpu_state.regs[cpu_reg].l; \
src = geteal(); \
if (cpu_state.abrt) \
return 1; \
setflags##32 flagops; \
cpu_state.regs[cpu_reg].l = operation; \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml); \
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, 0, 1); \
return 0; \
} \
\
static int op##name##_AL_imm(uint32_t fetchdat) \
{ \
uint8_t dst = AL; \
uint8_t src = getbytef(); \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
setflags##8 flagops; \
AL = operation; \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 2, -1, 0, 0, 0, 0, 0); \
return 0; \
} \
\
static int op##name##_AX_imm(uint32_t fetchdat) \
{ \
uint16_t dst = AX; \
uint16_t src = getwordf(); \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
setflags##16 flagops; \
AX = operation; \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 3, -1, 0, 0, 0, 0, 0); \
return 0; \
} \
\
static int op##name##_EAX_imm(uint32_t fetchdat) \
{ \
uint32_t dst = EAX; \
uint32_t src = getlong(); \
if (cpu_state.abrt) \
return 1; \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
setflags##32 flagops; \
EAX = operation; \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 5, -1, 0, 0, 0, 0, 0); \
return 0; \
}
OP_ARITH(ADD, dst + src, setadd, (dst, src), 0)
OP_ARITH(ADC, dst + src + tempc, setadc, (dst, src), 1)
OP_ARITH(SUB, dst - src, setsub, (dst, src), 0)
Added the IBM 5161 ISA expansion for PC and XT; Cleaned up the parallel port emulation, added IRQ support, and made enabling/disabling per port; Added the Award 430NX and the Intel Classic/PCI (Alfredo, 420TX); Finished the 586MC1; Added 8087 emulation; Moved Cyrix 6x86'es to the Dev branch; Sanitized/cleaned up memregs.c/h and intel.c/h; Split the chipsets from machines and sanitized Port 92 emulation; Added support for the 15bpp mode to the Compaq ATI 28800; Moved the MR 386DX and 486 machines to the Dev branch; Ported the new dynamic recompiler from PCem, but it remains in Dev branch until after v2.00; Ported the new timer code from PCem; Cleaned up the CPU table of unused stuff and better optimized its structure; Ported the Open-XT and Open-AT from VARCem, the Open-AT is in the Dev branch; Ported the XT MFM controller rewrite and adding of more controllers (incl. two RLL ones), from VARCem; Added the AHA-1540A and the BusTek BT-542B; Moved the Sumo SCSI-AT to the Dev branch; Minor IDE, FDC, and floppy drive code clean-ups; Made NCR 5380/53C400-based cards' BIOS address configurable; Got rid of the legacy romset variable; Unified (video) buffer and buffer32 into one and make the unified buffer 32-bit; Added the Amstead PPC512 per PCem patch by John Elliott; Switched memory mapping granularity from 16k to 4k (less than 1k not possible due to internal pages); Rewrote the CL-GD 54xx blitter, fixes Win-OS/2 on the 54x6 among other thing; Added the Image Manager 1024 and Professional Graphics Controller per PCem patch by John Elliott and work done on VARCem; Added Headland HT-216, GC-205 and Video 7 VGA 1024i emulation based on PCem commit; Implemented the fuction keys for the Toshiba T1000/T1200/T3100 enhancement; Amstrad MegaPC does now works correctly with non-internal graphics card; The SLiRP code no longer casts a packed struct type to a non-packed struct type; The Xi8088 and PB410a no longer hang on 86Box when PS/2 mouse is not present; The S3 Virge on BeOS is no longer broken (was broken by build #1591); OS/2 2.0 build 6.167 now sees key presses again; Xi8088 now work on CGA again; 86F images converted from either the old or new variants of the HxC MFM format now work correctly; Hardware interrupts with a vector of 0xFF are now handled correctly; OPTi 495SX boards no longer incorrectly have 64 MB maximum RAM when 32 MB is correct; Fixed VNC keyboard input bugs; Fixed AT RTC periodic interrupt - Chicago 58s / 73f / 73g / 81 MIDI play no longer hangs with the build's own VTD driver; Fixed mouse polling with internal mice - Amstrad and Olivetti mice now work correctly; Triones ATAPI DMA driver now correctly reads a file at the end of a CD image with a sectors number not divisible by 4; Compaq Portable now works with all graphics cards; Fixed various MDSI Genius bugs; Added segment limit checks and improved page fault checks for several CPU instructions - Memphis 15xx WINSETUP and Chicago 58s WINDISK.CPL no longer issue a GPF, and some S3 drivers that used to have glitches, now work correctly; Further improved the 808x emulation, also fixes the noticably choppy sound when using 808x CPU's, also fixes #355; OS/2 installer no logner locks up on splash screen on PS/2 Model 70 and 80, fixes #400. Fixed several Amstead bugs, GEM no longer crashes on the Amstrad 1640, fixes #391. Ported John Elliott's Amstrad fixes and improvement from PCem, and fixed the default language so it's correctly Engliish, fixes #278, fixes #389. Fixed a minor IDE timing bug, fixes #388. Fixed Toshiba T1000 RAM issues, fixes #379. Fixed EGA/(S)VGA overscan border handling, fixes #378; Got rid of the now long useless IDE channel 2 auto-removal, fixes #370; Fixed the BIOS files used by the AMSTRAD PC1512, fixes #366; Ported the Unicode CD image file name fix from VARCem, fixes #365; Fixed high density floppy disks on the Xi8088, fixes #359; Fixed some bugs in the Hercules emulation, fixes #346, fixes #358; Fixed the SCSI hard disk mode sense pages, fixes #356; Removed the AMI Unknown 386SX because of impossibility to identify the chipset, closes #349; Fixed bugs in the serial mouse emulation, fixes #344; Compiled 86Box binaries now include all the required .DLL's, fixes #341; Made some combo boxes in the Settings dialog slightly wider, fixes #276.
2019-09-20 14:02:30 +02:00
OP_ARITH(SBB, dst - (src + tempc), setsbc, (dst, src), 1)
clang format in cpu
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OP_ARITH(OR, dst | src, setznp, (dst | src), 0)
OP_ARITH(AND, dst &src, setznp, (dst & src), 0)
OP_ARITH(XOR, dst ^ src, setznp, (dst ^ src), 0)
static int
opCMP_b_rmw_a16(uint32_t fetchdat)
{
uint8_t dst;
sonarlinting and formatting in src/cpu
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clang format in cpu
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fetch_ea_16(fetchdat);
if (cpu_mod != 3)
SEG_CHECK_READ(cpu_state.ea_seg);
dst = geteab();
if (cpu_state.abrt)
return 1;
setsub8(dst, getr8(cpu_reg));
if (is486) {
CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
} else {
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
}
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 0);
return 0;
}
static int
opCMP_b_rmw_a32(uint32_t fetchdat)
{
uint8_t dst;
sonarlinting and formatting in src/cpu
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clang format in cpu
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fetch_ea_32(fetchdat);
if (cpu_mod != 3)
SEG_CHECK_READ(cpu_state.ea_seg);
dst = geteab();
if (cpu_state.abrt)
return 1;
setsub8(dst, getr8(cpu_reg));
if (is486) {
CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
} else {
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
}
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 1);
return 0;
}
static int
opCMP_w_rmw_a16(uint32_t fetchdat)
{
uint16_t dst;
sonarlinting and formatting in src/cpu
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clang format in cpu
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fetch_ea_16(fetchdat);
if (cpu_mod != 3)
SEG_CHECK_READ(cpu_state.ea_seg);
dst = geteaw();
if (cpu_state.abrt)
return 1;
setsub16(dst, cpu_state.regs[cpu_reg].w);
if (is486) {
CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
} else {
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
}
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 0);
return 0;
}
static int
opCMP_w_rmw_a32(uint32_t fetchdat)
{
uint16_t dst;
sonarlinting and formatting in src/cpu
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clang format in cpu
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fetch_ea_32(fetchdat);
if (cpu_mod != 3)
SEG_CHECK_READ(cpu_state.ea_seg);
dst = geteaw();
if (cpu_state.abrt)
return 1;
setsub16(dst, cpu_state.regs[cpu_reg].w);
if (is486) {
CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
} else {
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
}
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 1);
return 0;
}
static int
opCMP_l_rmw_a16(uint32_t fetchdat)
{
uint32_t dst;
sonarlinting and formatting in src/cpu
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clang format in cpu
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fetch_ea_16(fetchdat);
if (cpu_mod != 3)
SEG_CHECK_READ(cpu_state.ea_seg);
dst = geteal();
if (cpu_state.abrt)
return 1;
setsub32(dst, cpu_state.regs[cpu_reg].l);
if (is486) {
CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
} else {
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
}
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, 0, 0);
return 0;
}
static int
opCMP_l_rmw_a32(uint32_t fetchdat)
{
uint32_t dst;
sonarlinting and formatting in src/cpu
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clang format in cpu
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fetch_ea_32(fetchdat);
if (cpu_mod != 3)
SEG_CHECK_READ(cpu_state.ea_seg);
dst = geteal();
if (cpu_state.abrt)
return 1;
setsub32(dst, cpu_state.regs[cpu_reg].l);
if (is486) {
CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
} else {
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
}
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, 0, 1);
return 0;
}
static int
opCMP_b_rm_a16(uint32_t fetchdat)
{
uint8_t src;
sonarlinting and formatting in src/cpu
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clang format in cpu
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fetch_ea_16(fetchdat);
if (cpu_mod != 3)
SEG_CHECK_READ(cpu_state.ea_seg);
src = geteab();
if (cpu_state.abrt)
return 1;
setsub8(getr8(cpu_reg), src);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 0);
return 0;
}
static int
opCMP_b_rm_a32(uint32_t fetchdat)
{
uint8_t src;
sonarlinting and formatting in src/cpu
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clang format in cpu
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fetch_ea_32(fetchdat);
if (cpu_mod != 3)
SEG_CHECK_READ(cpu_state.ea_seg);
src = geteab();
if (cpu_state.abrt)
return 1;
setsub8(getr8(cpu_reg), src);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 1);
return 0;
}
static int
opCMP_w_rm_a16(uint32_t fetchdat)
{
uint16_t src;
sonarlinting and formatting in src/cpu
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clang format in cpu
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fetch_ea_16(fetchdat);
if (cpu_mod != 3)
SEG_CHECK_READ(cpu_state.ea_seg);
src = geteaw();
if (cpu_state.abrt)
return 1;
setsub16(cpu_state.regs[cpu_reg].w, src);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 0);
return 0;
}
static int
opCMP_w_rm_a32(uint32_t fetchdat)
{
uint16_t src;
sonarlinting and formatting in src/cpu
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clang format in cpu
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fetch_ea_32(fetchdat);
if (cpu_mod != 3)
SEG_CHECK_READ(cpu_state.ea_seg);
src = geteaw();
if (cpu_state.abrt)
return 1;
setsub16(cpu_state.regs[cpu_reg].w, src);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 1);
return 0;
}
static int
opCMP_l_rm_a16(uint32_t fetchdat)
{
uint32_t src;
sonarlinting and formatting in src/cpu
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clang format in cpu
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fetch_ea_16(fetchdat);
if (cpu_mod != 3)
SEG_CHECK_READ(cpu_state.ea_seg);
src = geteal();
if (cpu_state.abrt)
return 1;
setsub32(cpu_state.regs[cpu_reg].l, src);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, 0, 0);
return 0;
}
static int
opCMP_l_rm_a32(uint32_t fetchdat)
{
uint32_t src;
sonarlinting and formatting in src/cpu
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clang format in cpu
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fetch_ea_32(fetchdat);
if (cpu_mod != 3)
SEG_CHECK_READ(cpu_state.ea_seg);
src = geteal();
if (cpu_state.abrt)
return 1;
setsub32(cpu_state.regs[cpu_reg].l, src);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, 0, 1);
return 0;
}
static int
opCMP_AL_imm(uint32_t fetchdat)
{
uint8_t src = getbytef();
sonarlinting and formatting in src/cpu
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clang format in cpu
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setsub8(AL, src);
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, -1, 0, 0, 0, 0, 0);
return 0;
}
static int
opCMP_AX_imm(uint32_t fetchdat)
{
uint16_t src = getwordf();
sonarlinting and formatting in src/cpu
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clang format in cpu
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setsub16(AX, src);
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 3, -1, 0, 0, 0, 0, 0);
return 0;
}
static int
opCMP_EAX_imm(uint32_t fetchdat)
{
uint32_t src = getlong();
sonarlinting and formatting in src/cpu
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clang format in cpu
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if (cpu_state.abrt)
return 1;
setsub32(EAX, src);
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 5, -1, 0, 0, 0, 0, 0);
return 0;
}
static int
opTEST_b_a16(uint32_t fetchdat)
{
sonarlinting and formatting in src/cpu
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uint8_t temp;
uint8_t temp2;
clang format in cpu
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fetch_ea_16(fetchdat);
if (cpu_mod != 3)
SEG_CHECK_READ(cpu_state.ea_seg);
temp = geteab();
if (cpu_state.abrt)
return 1;
temp2 = getr8(cpu_reg);
setznp8(temp & temp2);
if (is486) {
CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
} else {
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
}
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 0);
return 0;
}
static int
opTEST_b_a32(uint32_t fetchdat)
{
sonarlinting and formatting in src/cpu
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uint8_t temp;
uint8_t temp2;
clang format in cpu
2022-11-19 10:40:32 -05:00
fetch_ea_32(fetchdat);
if (cpu_mod != 3)
SEG_CHECK_READ(cpu_state.ea_seg);
temp = geteab();
if (cpu_state.abrt)
return 1;
temp2 = getr8(cpu_reg);
setznp8(temp & temp2);
if (is486) {
CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
} else {
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
}
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 1);
return 0;
}
static int
opTEST_w_a16(uint32_t fetchdat)
{
sonarlinting and formatting in src/cpu
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uint16_t temp;
uint16_t temp2;
clang format in cpu
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fetch_ea_16(fetchdat);
if (cpu_mod != 3)
SEG_CHECK_READ(cpu_state.ea_seg);
temp = geteaw();
if (cpu_state.abrt)
return 1;
temp2 = cpu_state.regs[cpu_reg].w;
setznp16(temp & temp2);
if (is486) {
CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
} else {
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
}
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 0);
return 0;
}
static int
opTEST_w_a32(uint32_t fetchdat)
{
sonarlinting and formatting in src/cpu
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uint16_t temp;
uint16_t temp2;
clang format in cpu
2022-11-19 10:40:32 -05:00
fetch_ea_32(fetchdat);
if (cpu_mod != 3)
SEG_CHECK_READ(cpu_state.ea_seg);
temp = geteaw();
if (cpu_state.abrt)
return 1;
temp2 = cpu_state.regs[cpu_reg].w;
setznp16(temp & temp2);
if (is486) {
CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
} else {
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
}
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 1);
return 0;
}
static int
opTEST_l_a16(uint32_t fetchdat)
{
sonarlinting and formatting in src/cpu
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uint32_t temp;
uint16_t temp2;
clang format in cpu
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fetch_ea_16(fetchdat);
if (cpu_mod != 3)
SEG_CHECK_READ(cpu_state.ea_seg);
temp = geteal();
if (cpu_state.abrt)
return 1;
temp2 = cpu_state.regs[cpu_reg].l;
setznp32(temp & temp2);
if (is486) {
CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
} else {
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
}
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, 0, 0);
return 0;
}
static int
opTEST_l_a32(uint32_t fetchdat)
{
sonarlinting and formatting in src/cpu
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uint32_t temp;
uint16_t temp2;
clang format in cpu
2022-11-19 10:40:32 -05:00
fetch_ea_32(fetchdat);
if (cpu_mod != 3)
SEG_CHECK_READ(cpu_state.ea_seg);
temp = geteal();
if (cpu_state.abrt)
return 1;
temp2 = cpu_state.regs[cpu_reg].l;
setznp32(temp & temp2);
if (is486) {
CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
} else {
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
}
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, 0, 1);
return 0;
}
static int
opTEST_AL(uint32_t fetchdat)
{
uint8_t temp = getbytef();
setznp8(AL & temp);
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, -1, 0, 0, 0, 0, 0);
return 0;
}
static int
opTEST_AX(uint32_t fetchdat)
{
uint16_t temp = getwordf();
setznp16(AX & temp);
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 3, -1, 0, 0, 0, 0, 0);
return 0;
}
static int
opTEST_EAX(uint32_t fetchdat)
{
uint32_t temp = getlong();
if (cpu_state.abrt)
return 1;
setznp32(EAX & temp);
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 5, -1, 0, 0, 0, 0, 0);
return 0;
}
#define ARITH_MULTI(ea_width, flag_width) \
dst = getea##ea_width(); \
if (cpu_state.abrt) \
return 1; \
switch (rmdat & 0x38) { \
case 0x00: /*ADD ea, #*/ \
setea##ea_width(dst + src); \
if (cpu_state.abrt) \
return 1; \
setadd##flag_width(dst, src); \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
break; \
case 0x08: /*OR ea, #*/ \
dst |= src; \
setea##ea_width(dst); \
if (cpu_state.abrt) \
return 1; \
setznp##flag_width(dst); \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
break; \
case 0x10: /*ADC ea, #*/ \
tempc = CF_SET() ? 1 : 0; \
setea##ea_width(dst + src + tempc); \
if (cpu_state.abrt) \
return 1; \
setadc##flag_width(dst, src); \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
break; \
case 0x18: /*SBB ea, #*/ \
tempc = CF_SET() ? 1 : 0; \
setea##ea_width(dst - (src + tempc)); \
if (cpu_state.abrt) \
return 1; \
setsbc##flag_width(dst, src); \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
break; \
case 0x20: /*AND ea, #*/ \
dst &= src; \
setea##ea_width(dst); \
if (cpu_state.abrt) \
return 1; \
setznp##flag_width(dst); \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
break; \
case 0x28: /*SUB ea, #*/ \
setea##ea_width(dst - src); \
if (cpu_state.abrt) \
return 1; \
setsub##flag_width(dst, src); \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
break; \
case 0x30: /*XOR ea, #*/ \
dst ^= src; \
setea##ea_width(dst); \
if (cpu_state.abrt) \
return 1; \
setznp##flag_width(dst); \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
break; \
case 0x38: /*CMP ea, #*/ \
setsub##flag_width(dst, src); \
if (is486) { \
CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2); \
} else { \
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 7); \
} \
break; \
}
static int
op80_a16(uint32_t fetchdat)
{
sonarlinting and formatting in src/cpu
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uint8_t src;
uint8_t dst;
clang format in cpu
2022-11-19 10:40:32 -05:00
fetch_ea_16(fetchdat);
if (cpu_mod != 3)
SEG_CHECK_WRITE(cpu_state.ea_seg);
src = getbyte();
if (cpu_state.abrt)
return 1;
ARITH_MULTI(b, 8);
if ((rmdat & 0x38) == 0x38) {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 0);
} else {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, 0);
}
return 0;
}
static int
op80_a32(uint32_t fetchdat)
{
sonarlinting and formatting in src/cpu
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uint8_t src;
uint8_t dst;
clang format in cpu
2022-11-19 10:40:32 -05:00
fetch_ea_32(fetchdat);
if (cpu_mod != 3)
SEG_CHECK_WRITE(cpu_state.ea_seg);
src = getbyte();
if (cpu_state.abrt)
return 1;
ARITH_MULTI(b, 8);
if ((rmdat & 0x38) == 0x38) {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 1);
} else {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, 1);
}
return 0;
}
static int
op81_w_a16(uint32_t fetchdat)
{
sonarlinting and formatting in src/cpu
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uint16_t src;
uint16_t dst;
clang format in cpu
2022-11-19 10:40:32 -05:00
fetch_ea_16(fetchdat);
if (cpu_mod != 3)
SEG_CHECK_WRITE(cpu_state.ea_seg);
src = getword();
if (cpu_state.abrt)
return 1;
ARITH_MULTI(w, 16);
if ((rmdat & 0x38) == 0x38) {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 4, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 0);
} else {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 4, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, 0);
}
return 0;
}
static int
op81_w_a32(uint32_t fetchdat)
{
sonarlinting and formatting in src/cpu
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uint16_t src;
uint16_t dst;
clang format in cpu
2022-11-19 10:40:32 -05:00
fetch_ea_32(fetchdat);
if (cpu_mod != 3)
SEG_CHECK_WRITE(cpu_state.ea_seg);
src = getword();
if (cpu_state.abrt)
return 1;
ARITH_MULTI(w, 16);
if ((rmdat & 0x38) == 0x38) {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 4, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 1);
} else {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 4, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, 1);
}
return 0;
}
static int
op81_l_a16(uint32_t fetchdat)
{
sonarlinting and formatting in src/cpu
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uint32_t src;
uint32_t dst;
clang format in cpu
2022-11-19 10:40:32 -05:00
fetch_ea_16(fetchdat);
if (cpu_mod != 3)
SEG_CHECK_WRITE(cpu_state.ea_seg);
src = getlong();
if (cpu_state.abrt)
return 1;
ARITH_MULTI(l, 32);
if ((rmdat & 0x38) == 0x38) {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 6, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, 0, 0);
} else {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 6, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0);
}
return 0;
}
static int
op81_l_a32(uint32_t fetchdat)
{
sonarlinting and formatting in src/cpu
2023-08-10 15:43:16 -04:00
uint32_t src;
uint32_t dst;
clang format in cpu
2022-11-19 10:40:32 -05:00
fetch_ea_32(fetchdat);
if (cpu_mod != 3)
SEG_CHECK_WRITE(cpu_state.ea_seg);
src = getlong();
if (cpu_state.abrt)
return 1;
ARITH_MULTI(l, 32);
if ((rmdat & 0x38) == 0x38) {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 6, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, 0, 1);
} else {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 6, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 1);
}
return 0;
}
static int
op83_w_a16(uint32_t fetchdat)
{
sonarlinting and formatting in src/cpu
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uint16_t src;
uint16_t dst;
clang format in cpu
2022-11-19 10:40:32 -05:00
fetch_ea_16(fetchdat);
if (cpu_mod != 3)
SEG_CHECK_WRITE(cpu_state.ea_seg);
src = getbyte();
if (cpu_state.abrt)
return 1;
if (src & 0x80)
src |= 0xff00;
ARITH_MULTI(w, 16);
if ((rmdat & 0x38) == 0x38) {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 0);
} else {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, 0);
}
return 0;
}
static int
op83_w_a32(uint32_t fetchdat)
{
sonarlinting and formatting in src/cpu
2023-08-10 15:43:16 -04:00
uint16_t src;
uint16_t dst;
clang format in cpu
2022-11-19 10:40:32 -05:00
fetch_ea_32(fetchdat);
if (cpu_mod != 3)
SEG_CHECK_WRITE(cpu_state.ea_seg);
src = getbyte();
if (cpu_state.abrt)
return 1;
if (src & 0x80)
src |= 0xff00;
ARITH_MULTI(w, 16);
if ((rmdat & 0x38) == 0x38) {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 1);
} else {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, 1);
}
return 0;
}
static int
op83_l_a16(uint32_t fetchdat)
{
sonarlinting and formatting in src/cpu
2023-08-10 15:43:16 -04:00
uint32_t src;
uint16_t dst;
clang format in cpu
2022-11-19 10:40:32 -05:00
fetch_ea_16(fetchdat);
if (cpu_mod != 3)
SEG_CHECK_WRITE(cpu_state.ea_seg);
src = getbyte();
if (cpu_state.abrt)
return 1;
if (src & 0x80)
src |= 0xffffff00;
ARITH_MULTI(l, 32);
if ((rmdat & 0x38) == 0x38) {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, 0, 0);
} else {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0);
}
return 0;
}
static int
op83_l_a32(uint32_t fetchdat)
{
sonarlinting and formatting in src/cpu
2023-08-10 15:43:16 -04:00
uint32_t src;
uint32_t dst;
clang format in cpu
2022-11-19 10:40:32 -05:00
fetch_ea_32(fetchdat);
if (cpu_mod != 3)
SEG_CHECK_WRITE(cpu_state.ea_seg);
src = getbyte();
if (cpu_state.abrt)
return 1;
if (src & 0x80)
src |= 0xffffff00;
ARITH_MULTI(l, 32);
if ((rmdat & 0x38) == 0x38) {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, 0, 1);
} else {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 1);
}
return 0;
Added the IBM 5161 ISA expansion for PC and XT; Cleaned up the parallel port emulation, added IRQ support, and made enabling/disabling per port; Added the Award 430NX and the Intel Classic/PCI (Alfredo, 420TX); Finished the 586MC1; Added 8087 emulation; Moved Cyrix 6x86'es to the Dev branch; Sanitized/cleaned up memregs.c/h and intel.c/h; Split the chipsets from machines and sanitized Port 92 emulation; Added support for the 15bpp mode to the Compaq ATI 28800; Moved the MR 386DX and 486 machines to the Dev branch; Ported the new dynamic recompiler from PCem, but it remains in Dev branch until after v2.00; Ported the new timer code from PCem; Cleaned up the CPU table of unused stuff and better optimized its structure; Ported the Open-XT and Open-AT from VARCem, the Open-AT is in the Dev branch; Ported the XT MFM controller rewrite and adding of more controllers (incl. two RLL ones), from VARCem; Added the AHA-1540A and the BusTek BT-542B; Moved the Sumo SCSI-AT to the Dev branch; Minor IDE, FDC, and floppy drive code clean-ups; Made NCR 5380/53C400-based cards' BIOS address configurable; Got rid of the legacy romset variable; Unified (video) buffer and buffer32 into one and make the unified buffer 32-bit; Added the Amstead PPC512 per PCem patch by John Elliott; Switched memory mapping granularity from 16k to 4k (less than 1k not possible due to internal pages); Rewrote the CL-GD 54xx blitter, fixes Win-OS/2 on the 54x6 among other thing; Added the Image Manager 1024 and Professional Graphics Controller per PCem patch by John Elliott and work done on VARCem; Added Headland HT-216, GC-205 and Video 7 VGA 1024i emulation based on PCem commit; Implemented the fuction keys for the Toshiba T1000/T1200/T3100 enhancement; Amstrad MegaPC does now works correctly with non-internal graphics card; The SLiRP code no longer casts a packed struct type to a non-packed struct type; The Xi8088 and PB410a no longer hang on 86Box when PS/2 mouse is not present; The S3 Virge on BeOS is no longer broken (was broken by build #1591); OS/2 2.0 build 6.167 now sees key presses again; Xi8088 now work on CGA again; 86F images converted from either the old or new variants of the HxC MFM format now work correctly; Hardware interrupts with a vector of 0xFF are now handled correctly; OPTi 495SX boards no longer incorrectly have 64 MB maximum RAM when 32 MB is correct; Fixed VNC keyboard input bugs; Fixed AT RTC periodic interrupt - Chicago 58s / 73f / 73g / 81 MIDI play no longer hangs with the build's own VTD driver; Fixed mouse polling with internal mice - Amstrad and Olivetti mice now work correctly; Triones ATAPI DMA driver now correctly reads a file at the end of a CD image with a sectors number not divisible by 4; Compaq Portable now works with all graphics cards; Fixed various MDSI Genius bugs; Added segment limit checks and improved page fault checks for several CPU instructions - Memphis 15xx WINSETUP and Chicago 58s WINDISK.CPL no longer issue a GPF, and some S3 drivers that used to have glitches, now work correctly; Further improved the 808x emulation, also fixes the noticably choppy sound when using 808x CPU's, also fixes #355; OS/2 installer no logner locks up on splash screen on PS/2 Model 70 and 80, fixes #400. Fixed several Amstead bugs, GEM no longer crashes on the Amstrad 1640, fixes #391. Ported John Elliott's Amstrad fixes and improvement from PCem, and fixed the default language so it's correctly Engliish, fixes #278, fixes #389. Fixed a minor IDE timing bug, fixes #388. Fixed Toshiba T1000 RAM issues, fixes #379. Fixed EGA/(S)VGA overscan border handling, fixes #378; Got rid of the now long useless IDE channel 2 auto-removal, fixes #370; Fixed the BIOS files used by the AMSTRAD PC1512, fixes #366; Ported the Unicode CD image file name fix from VARCem, fixes #365; Fixed high density floppy disks on the Xi8088, fixes #359; Fixed some bugs in the Hercules emulation, fixes #346, fixes #358; Fixed the SCSI hard disk mode sense pages, fixes #356; Removed the AMI Unknown 386SX because of impossibility to identify the chipset, closes #349; Fixed bugs in the serial mouse emulation, fixes #344; Compiled 86Box binaries now include all the required .DLL's, fixes #341; Made some combo boxes in the Settings dialog slightly wider, fixes #276.
2019-09-20 14:02:30 +02:00
}
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