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86Box/src/include/86box/pci.h

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Ported PCI clean-ups from VARCem.
2018-10-21 20:27:57 +02:00
/*
Random header cleanups I noticed while porting things
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* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
Ported PCI clean-ups from VARCem.
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*
Random header cleanups I noticed while porting things
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* This file is part of the 86Box distribution.
Ported PCI clean-ups from VARCem.
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*
Random header cleanups I noticed while porting things
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* Definitions for the PCI handler module.
Ported PCI clean-ups from VARCem.
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*
Remove version tree-wide
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*
Ported PCI clean-ups from VARCem.
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*
Random header cleanups I noticed while porting things
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* Authors: Miran Grca, <mgrca8@gmail.com>
Ported PCI clean-ups from VARCem.
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*
PCI and IRQ rework, pci.c rewritten from ground up, fixes numerous issues such as the bridge being added when the number of normal PCI devices equals the number of normal PCI slots, Windows 95 PCI operation on Intel 430NX, sharing of PCI IRQ's with non-PCI level-triggered devices, having both configuration mechanisms operating at the same time (ALi M1435), etc., and makes the code much more readable.
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* Copyright 2023 Miran Grca.
Ported PCI clean-ups from VARCem.
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*/
#ifndef EMU_PCI_H
clang-format in src/include/86box/
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#define EMU_PCI_H
PCI turbo reset control and PCI initialization functions now reset the ELCR registers, the PIC, and the PCI IRQ statuses, fixes PCI cards being stuck unable to issue IRQ's after soft and hard resets.
2017-06-21 19:42:36 +02:00
PCI and IRQ rework, pci.c rewritten from ground up, fixes numerous issues such as the bridge being added when the number of normal PCI devices equals the number of normal PCI slots, Windows 95 PCI operation on Intel 430NX, sharing of PCI IRQ's with non-PCI level-triggered devices, having both configuration mechanisms operating at the same time (ALi M1435), etc., and makes the code much more readable.
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#define PCI_REG_VENDOR_ID_L 0x00
#define PCI_REG_VENDOR_ID_H 0x01
#define PCI_REG_DEVICE_ID_L 0x02
#define PCI_REG_DEVICE_ID_H 0x03
#define PCI_REG_COMMAND_L 0x04
#define PCI_REG_COMMAND_H 0x05
#define PCI_REG_STATUS_L 0x06
#define PCI_REG_STATUS_H 0x07
#define PCI_REG_REVISION 0x08
#define PCI_REG_PROG_IF 0x09
#define PCI_REG_SUBCLASS 0x0a
#define PCI_REG_CLASS 0x0b
#define PCI_REG_CACHELINE_SIZE 0x0c
#define PCI_REG_LATENCY_TIMER 0x0d
#define PCI_REG_HEADER_TYPE 0x0e
#define PCI_REG_BIST 0x0f
#define PCI_COMMAND_L_IO 0x01
#define PCI_COMMAND_L_MEM 0x02
#define PCI_COMMAND_L_BM 0x04
#define PCI_COMMAND_L_SPECIAL 0x08
#define PCI_COMMAND_L_MEM_WIEN 0x10
#define PCI_COMMAND_L_VGASNOOP 0x20
#define PCI_COMMAND_L_PARITY 0x40
#define PCI_COMMAND_H_SERR 0x01
#define PCI_COMMAND_H_FAST_B2B 0x02
#define PCI_COMMAND_H_INT_DIS 0x04
#define PCI_STATUS_L_INT 0x08
#define PCI_STATUS_L_CAPAB 0x10
#define PCI_STATUS_L_66MHZ 0x20
#define PCI_STATUS_L_FAST_B2B 0x80
#define PCI_STATUS_H_MDPERR 0x01 /* Master Data Parity Error */
#define PCI_STATUS_H_DEVSEL 0x06
#define PCI_STATUS_H_STA 0x08 /* Signaled Target Abort */
#define PCI_STATUS_H_RTA 0x10 /* Received Target Abort */
#define PCI_STATUS_H_RMA 0x20 /* Received Master Abort */
#define PCI_STATUS_H_SSE 0x40 /* Signaled System Error */
#define PCI_STATUS_H_DPERR 0x80 /* Detected Parity Error */
#define PCI_DEVSEL_FAST 0x00
#define PCI_DEVSEL_MEDIUM 0x02
#define PCI_DEVSEL_SLOW 0x04
#define FLAG_MECHANISM_1 0x00000001
#define FLAG_MECHANISM_2 0x00000002
#define FLAG_MECHANISM_SWITCH 0x00000004
#define FLAG_CONFIG_IO_ON 0x00000008
#define FLAG_CONFIG_DEV0_IO_ON 0x00000010
#define FLAG_CONFIG_M1_IO_ON 0x00000020
#define FLAG_NO_IRQ_STEERING 0x00000040
#define FLAG_NO_BRIDGES 0x00000080
#define FLAG_MECHANISM_MASK FLAG_MECHANISM_1 | FLAG_MECHANISM_2
#define FLAG_MASK 0x0000007f
#define PCI_INTA 1
#define PCI_INTB 2
#define PCI_INTC 3
#define PCI_INTD 4
#define PCI_MIRQ0 0
#define PCI_MIRQ1 1
#define PCI_MIRQ2 2
#define PCI_MIRQ3 3
#define PCI_MIRQ4 4
#define PCI_MIRQ5 5
#define PCI_MIRQ6 6
#define PCI_MIRQ7 7
#define PCI_IRQ_DISABLED -1
#define PCI_ADD_STRICT 0x40
#define PCI_ADD_MASK (PCI_ADD_STRICT - 1)
#define PCI_ADD_VFIO 0x80
#define PCI_ADD_VFIO_MASK (PCI_ADD_VFIO - 1)
#define PCI_CARD_VFIO PCI_ADD_VFIO
#define PCI_BUS_INVALID 0xff
#define PCI_IGNORE_NO_SLOT 0xff
/* The number of an invalid PCI card. */
#define PCI_CARD_INVALID 0xef
/* PCI cards (currently 32). */
#define PCI_CARDS_NUM 0x20
#define PCI_CARD_MAX (PCI_CARDS_NUM - 1)
/* The number of PCI card INT pins - always at 4 per the PCI specification. */
#define PCI_INT_PINS_NUM 4
/* The base for MIRQ lines accepted by pci_irq(). */
#define PCI_MIRQ_BASE PCI_CARDS_NUM
/* PCI MIRQ lines (currently 8, this many are needed by the ALi M1543(C). */
#define PCI_MIRQS_NUM 8
#define PCI_MIRQ_MAX (PCI_MIRQS_NUM - 1)
/* The base for direct IRQ lines accepted by pci_irq(). */
#define PCI_DIRQ_BASE 0xf0
/* PCI direct IRQ lines (currently 16 because we only emulate the legacy PIC). */
#define PCI_DIRQS_NUM 16
#define PCI_DIRQ_MAX (PCI_DIRQS_NUM - 1)
/* PCI IRQ routings (currently 16, this many are needed by the OPTi 822). */
#define PCI_IRQS_NUM 16
#define PCI_IRQ_MAX (PCI_IRQS_NUM - 1)
/* Legacy flags. */
#define PCI_REG_COMMAND PCI_REG_COMMAND_L
#define PCI_COMMAND_IO PCI_COMMAND_L_IO
#define PCI_COMMAND_MEM PCI_COMMAND_L_MEM
#define PCI_CONFIG_TYPE_1 FLAG_MECHANISM_1
#define PCI_CONFIG_TYPE_2 FLAG_MECHANISM_2
#define PCI_CAN_SWITCH_TYPE FLAG_MECHANISM_SWITCH
#define PCI_ALWAYS_EXPOSE_DEV0 FLAG_CONFIG_DEV0_IO_ON
#define PCI_NO_IRQ_STEERING FLAG_NO_IRQ_STEERING
#define PCI_NO_BRIDGES FLAG_NO_BRIDGES
#define PCI_CONFIG_TYPE_MASK FLAG_MECHANISM_MASK
#define bar_t pci_bar_t
#define trc_init pci_trc_init
#define pci_register_slot(card, type, inta, intb, intc, intd) \
pci_register_bus_slot(0, card, type, inta, intb, intc, intd)
#define pci_set_mirq(mirq, level, irq_state) \
pci_irq(PCI_MIRQ_BASE | mirq, 0, level, 1, irq_state)
#define pci_set_irq(slot, pci_int, irq_state) \
pci_irq(slot, pci_int, 0, 1, irq_state)
#define pci_clear_mirq(mirq, level, irq_state) \
pci_irq(PCI_MIRQ_BASE | mirq, 0, level, 0, irq_state)
#define pci_clear_irq(slot, pci_int, irq_state) \
pci_irq(slot, pci_int, 0, 0, irq_state)
Merged various SMC FDC67C6xx Super I/O chips into one file, re-added the UMC88xx 486 chipsets (and four machines for it) based on work by tiseno100 and my own work, various other fixes, and added quite a few machines (including the AOpen AP5VM which now works), also added the remaining ALi M6117 machine (Protech SBC with Award BIOS), and made the Intel Advanced/ATX's on-board S3 Trio64V+ work, as well as the on-board S3 Trio64/V2 of the two Compaq Presarios.
2021-08-21 18:19:10 +02:00
Ported PCI clean-ups from VARCem.
2018-10-21 20:27:57 +02:00
enum {
Next round of sonarlint cleanups
2023-06-26 12:47:04 -04:00
PCI_CARD_NORTHBRIDGE = 0,
PCI and IRQ rework, pci.c rewritten from ground up, fixes numerous issues such as the bridge being added when the number of normal PCI devices equals the number of normal PCI slots, Windows 95 PCI operation on Intel 430NX, sharing of PCI IRQ's with non-PCI level-triggered devices, having both configuration mechanisms operating at the same time (ALi M1435), etc., and makes the code much more readable.
2023-08-07 03:04:52 +02:00
PCI_CARD_NORTHBRIDGE_SEC = 1,
PCI_CARD_AGPBRIDGE = 2,
PCI_CARD_SOUTHBRIDGE = 3,
PCI_CARD_SOUTHBRIDGE_IDE = 4,
PCI_CARD_SOUTHBRIDGE_PMU = 5,
PCI_CARD_SOUTHBRIDGE_USB = 6,
Next round of sonarlint cleanups
2023-06-26 12:47:04 -04:00
PCI_CARD_AGP = 0x0f,
PCI_CARD_NORMAL = 0x10,
PCI_CARD_VIDEO = 0x11,
PCI and IRQ rework, pci.c rewritten from ground up, fixes numerous issues such as the bridge being added when the number of normal PCI devices equals the number of normal PCI slots, Windows 95 PCI operation on Intel 430NX, sharing of PCI IRQ's with non-PCI level-triggered devices, having both configuration mechanisms operating at the same time (ALi M1435), etc., and makes the code much more readable.
2023-08-07 03:04:52 +02:00
PCI_CARD_HANGUL = 0x12,
PCI_CARD_IDE = 0x13,
PCI_CARD_SCSI = 0x14,
PCI_CARD_SOUND = 0x15,
PCI_CARD_MODEM = 0x16,
PCI_CARD_NETWORK = 0x17,
PCI_CARD_UART = 0x18,
PCI_CARD_USB = 0x19,
PCI_CARD_BRIDGE = 0x1a
Extensively reworked the PCI bus emulation, fixes quite a few bugs, including incorrect IRQ routing for the last two slots on the Intel Advanced/ATX.
2017-08-30 04:49:20 +02:00
};
Current WIP code.
2020-02-29 19:12:23 +01:00
enum {
Next round of sonarlint cleanups
2023-06-26 12:47:04 -04:00
PCI_ADD_NORTHBRIDGE = 0,
PCI and IRQ rework, pci.c rewritten from ground up, fixes numerous issues such as the bridge being added when the number of normal PCI devices equals the number of normal PCI slots, Windows 95 PCI operation on Intel 430NX, sharing of PCI IRQ's with non-PCI level-triggered devices, having both configuration mechanisms operating at the same time (ALi M1435), etc., and makes the code much more readable.
2023-08-07 03:04:52 +02:00
PCI_ADD_NORTHBRIDGE_SEC = 1,
PCI_ADD_AGPBRIDGE = 2,
PCI_ADD_SOUTHBRIDGE = 3,
PCI_ADD_SOUTHBRIDGE_IDE = 4,
PCI_ADD_SOUTHBRIDGE_PMU = 5,
PCI_ADD_SOUTHBRIDGE_USB = 6,
Next round of sonarlint cleanups
2023-06-26 12:47:04 -04:00
PCI_ADD_AGP = 0x0f,
PCI_ADD_NORMAL = 0x10,
PCI_ADD_VIDEO = 0x11,
PCI and IRQ rework, pci.c rewritten from ground up, fixes numerous issues such as the bridge being added when the number of normal PCI devices equals the number of normal PCI slots, Windows 95 PCI operation on Intel 430NX, sharing of PCI IRQ's with non-PCI level-triggered devices, having both configuration mechanisms operating at the same time (ALi M1435), etc., and makes the code much more readable.
2023-08-07 03:04:52 +02:00
PCI_ADD_HANGUL = 0x12,
PCI_ADD_IDE = 0x13,
PCI_ADD_SCSI = 0x14,
PCI_ADD_SOUND = 0x15,
PCI_ADD_MODEM = 0x16,
PCI_ADD_NETWORK = 0x17,
PCI_ADD_UART = 0x18,
PCI_ADD_USB = 0x19,
PCI_ADD_BRIDGE = 0x1a
Current WIP code.
2020-02-29 19:12:23 +01:00
};
Extensively reworked the PCI bus emulation, fixes quite a few bugs, including incorrect IRQ routing for the last two slots on the Intel Advanced/ATX.
2017-08-30 04:49:20 +02:00
typedef union {
uint32_t addr;
Rewritten the PCI Type 2 access handling.
2023-07-06 19:55:59 +02:00
uint8_t addr_regs[4];
PCI and IRQ rework, pci.c rewritten from ground up, fixes numerous issues such as the bridge being added when the number of normal PCI devices equals the number of normal PCI slots, Windows 95 PCI operation on Intel 430NX, sharing of PCI IRQ's with non-PCI level-triggered devices, having both configuration mechanisms operating at the same time (ALi M1435), etc., and makes the code much more readable.
2023-08-07 03:04:52 +02:00
} pci_bar_t;
extern int pci_burst_time;
extern int agp_burst_time;
extern int pci_nonburst_time;
extern int agp_nonburst_time;
Major commit, cleaning a lot of old stuff. IBM.H is gone, video stuff re-organized. Keyboard stuff reorganized. Machines that have their own video, mouse and/or keyboard now have all this in their machine file. Fixed and other cleanups here and there.
2017-11-05 01:57:04 -05:00
PCI and IRQ rework, pci.c rewritten from ground up, fixes numerous issues such as the bridge being added when the number of normal PCI devices equals the number of normal PCI slots, Windows 95 PCI operation on Intel 430NX, sharing of PCI IRQ's with non-PCI level-triggered devices, having both configuration mechanisms operating at the same time (ALi M1435), etc., and makes the code much more readable.
2023-08-07 03:04:52 +02:00
extern int pci_flags;
Rewritten the PCI Type 2 access handling.
2023-07-06 19:55:59 +02:00
PCI and IRQ rework, pci.c rewritten from ground up, fixes numerous issues such as the bridge being added when the number of normal PCI devices equals the number of normal PCI slots, Windows 95 PCI operation on Intel 430NX, sharing of PCI IRQ's with non-PCI level-triggered devices, having both configuration mechanisms operating at the same time (ALi M1435), etc., and makes the code much more readable.
2023-08-07 03:04:52 +02:00
extern uint32_t pci_base;
extern uint32_t pci_size;
Rewritten the PCI Type 2 access handling.
2023-07-06 19:55:59 +02:00
PCI and IRQ rework, pci.c rewritten from ground up, fixes numerous issues such as the bridge being added when the number of normal PCI devices equals the number of normal PCI slots, Windows 95 PCI operation on Intel 430NX, sharing of PCI IRQ's with non-PCI level-triggered devices, having both configuration mechanisms operating at the same time (ALi M1435), etc., and makes the code much more readable.
2023-08-07 03:04:52 +02:00
extern void pci_set_irq_routing(int pci_int, int irq);
extern void pci_set_irq_level(int pci_int, int level);
extern void pci_enable_mirq(int mirq);
extern void pci_set_mirq_routing(int mirq, int irq);
Rewritten the PCI Type 2 access handling.
2023-07-06 19:55:59 +02:00
PCI and IRQ rework, pci.c rewritten from ground up, fixes numerous issues such as the bridge being added when the number of normal PCI devices equals the number of normal PCI slots, Windows 95 PCI operation on Intel 430NX, sharing of PCI IRQ's with non-PCI level-triggered devices, having both configuration mechanisms operating at the same time (ALi M1435), etc., and makes the code much more readable.
2023-08-07 03:04:52 +02:00
/* PCI raise IRQ: the first parameter is slot if < PCI_MIRQ_BASE, MIRQ if >= PCI_MIRQ_BASE
and < PCI_DIRQ_BASE, and direct IRQ line if >= PCI_DIRQ_BASE (RichardG's
hack that may no longer be needed). */
extern void pci_irq(uint8_t slot, uint8_t pci_int, int level, int set, uint8_t *irq_state);
Rewritten the PCI Type 2 access handling.
2023-07-06 19:55:59 +02:00
PCI and IRQ rework, pci.c rewritten from ground up, fixes numerous issues such as the bridge being added when the number of normal PCI devices equals the number of normal PCI slots, Windows 95 PCI operation on Intel 430NX, sharing of PCI IRQ's with non-PCI level-triggered devices, having both configuration mechanisms operating at the same time (ALi M1435), etc., and makes the code much more readable.
2023-08-07 03:04:52 +02:00
extern uint8_t pci_get_int(uint8_t slot, uint8_t pci_int);
Rewritten the PCI Type 2 access handling.
2023-07-06 19:55:59 +02:00
PCI and IRQ rework, pci.c rewritten from ground up, fixes numerous issues such as the bridge being added when the number of normal PCI devices equals the number of normal PCI slots, Windows 95 PCI operation on Intel 430NX, sharing of PCI IRQ's with non-PCI level-triggered devices, having both configuration mechanisms operating at the same time (ALi M1435), etc., and makes the code much more readable.
2023-08-07 03:04:52 +02:00
/* Relocate a PCI device to a new slot, required for the configurable
IDSEL's of ALi M1543(c). */
extern void pci_relocate_slot(int type, int new_slot);
Rewritten the PCI Type 2 access handling.
2023-07-06 19:55:59 +02:00
PCI and IRQ rework, pci.c rewritten from ground up, fixes numerous issues such as the bridge being added when the number of normal PCI devices equals the number of normal PCI slots, Windows 95 PCI operation on Intel 430NX, sharing of PCI IRQ's with non-PCI level-triggered devices, having both configuration mechanisms operating at the same time (ALi M1435), etc., and makes the code much more readable.
2023-08-07 03:04:52 +02:00
/* Write PCI enable/disable key, split for the ALi M1435. */
extern void pci_key_write(uint8_t val);
Ported PCI clean-ups from VARCem.
2018-10-21 20:27:57 +02:00
PCI and IRQ rework, pci.c rewritten from ground up, fixes numerous issues such as the bridge being added when the number of normal PCI devices equals the number of normal PCI slots, Windows 95 PCI operation on Intel 430NX, sharing of PCI IRQ's with non-PCI level-triggered devices, having both configuration mechanisms operating at the same time (ALi M1435), etc., and makes the code much more readable.
2023-08-07 03:04:52 +02:00
/* Set PMC (ie. change PCI configuration mechanism), 0 = #2, 1 = #1. */
extern void pci_set_pmc(uint8_t pmc);
Ported PCI clean-ups from VARCem.
2018-10-21 20:27:57 +02:00
PCI and IRQ rework, pci.c rewritten from ground up, fixes numerous issues such as the bridge being added when the number of normal PCI devices equals the number of normal PCI slots, Windows 95 PCI operation on Intel 430NX, sharing of PCI IRQ's with non-PCI level-triggered devices, having both configuration mechanisms operating at the same time (ALi M1435), etc., and makes the code much more readable.
2023-08-07 03:04:52 +02:00
extern void pci_pic_reset(void);
extern void pci_reset(void);
Ported PCI clean-ups from VARCem.
2018-10-21 20:27:57 +02:00
PCI and IRQ rework, pci.c rewritten from ground up, fixes numerous issues such as the bridge being added when the number of normal PCI devices equals the number of normal PCI slots, Windows 95 PCI operation on Intel 430NX, sharing of PCI IRQ's with non-PCI level-triggered devices, having both configuration mechanisms operating at the same time (ALi M1435), etc., and makes the code much more readable.
2023-08-07 03:04:52 +02:00
/* Needed for the io.c handling of configuration mechanism #2 ports C000-CFFF. */
extern void pci_write(uint16_t port, uint8_t val, void *priv);
extern void pci_writew(uint16_t port, uint16_t val, void *priv);
extern void pci_writel(uint16_t port, uint32_t val, void *priv);
extern uint8_t pci_read(uint16_t port, void *priv);
extern uint16_t pci_readw(uint16_t port, void *priv);
extern uint32_t pci_readl(uint16_t port, void *priv);
Ported PCI clean-ups from VARCem.
2018-10-21 20:27:57 +02:00
PCI and IRQ rework, pci.c rewritten from ground up, fixes numerous issues such as the bridge being added when the number of normal PCI devices equals the number of normal PCI slots, Windows 95 PCI operation on Intel 430NX, sharing of PCI IRQ's with non-PCI level-triggered devices, having both configuration mechanisms operating at the same time (ALi M1435), etc., and makes the code much more readable.
2023-08-07 03:04:52 +02:00
extern uint8_t pci_register_bus(void);
extern void pci_remap_bus(uint8_t bus_index, uint8_t bus_number);
extern void pci_register_bus_slot(int bus, int card, int type, int inta, int intb, int intc, int intd);
Ported PCI clean-ups from VARCem.
2018-10-21 20:27:57 +02:00
PCI and IRQ rework, pci.c rewritten from ground up, fixes numerous issues such as the bridge being added when the number of normal PCI devices equals the number of normal PCI slots, Windows 95 PCI operation on Intel 430NX, sharing of PCI IRQ's with non-PCI level-triggered devices, having both configuration mechanisms operating at the same time (ALi M1435), etc., and makes the code much more readable.
2023-08-07 03:04:52 +02:00
/* Add a PCI card. */
extern void pci_add_card(uint8_t add_type, uint8_t (*read)(int func, int addr, void *priv),
void (*write)(int func, int addr, uint8_t val, void *priv), void *priv, uint8_t *slot);
Ported PCI clean-ups from VARCem.
2018-10-21 20:27:57 +02:00
PCI and IRQ rework, pci.c rewritten from ground up, fixes numerous issues such as the bridge being added when the number of normal PCI devices equals the number of normal PCI slots, Windows 95 PCI operation on Intel 430NX, sharing of PCI IRQ's with non-PCI level-triggered devices, having both configuration mechanisms operating at the same time (ALi M1435), etc., and makes the code much more readable.
2023-08-07 03:04:52 +02:00
/* Add an instance of the PCI bridge. */
Moved Voodoo initialization to the very end to minimize the likelihood of SCSI adapters ending up on the bridge.
2023-08-10 01:37:33 +02:00
extern void pci_add_bridge(uint8_t agp, uint8_t (*read)(int func, int addr, void *priv),
void (*write)(int func, int addr, uint8_t val, void *priv), void *priv,
uint8_t *slot);
Ported PCI clean-ups from VARCem.
2018-10-21 20:27:57 +02:00
PCI and IRQ rework, pci.c rewritten from ground up, fixes numerous issues such as the bridge being added when the number of normal PCI devices equals the number of normal PCI slots, Windows 95 PCI operation on Intel 430NX, sharing of PCI IRQ's with non-PCI level-triggered devices, having both configuration mechanisms operating at the same time (ALi M1435), etc., and makes the code much more readable.
2023-08-07 03:04:52 +02:00
/* Register the cards that have been added into slots. */
extern void pci_register_cards(void);
Ported PCI clean-ups from VARCem.
2018-10-21 20:27:57 +02:00
PCI and IRQ rework, pci.c rewritten from ground up, fixes numerous issues such as the bridge being added when the number of normal PCI devices equals the number of normal PCI slots, Windows 95 PCI operation on Intel 430NX, sharing of PCI IRQ's with non-PCI level-triggered devices, having both configuration mechanisms operating at the same time (ALi M1435), etc., and makes the code much more readable.
2023-08-07 03:04:52 +02:00
extern void pci_init(int flags);
Fixed the emulator.
2021-12-19 23:41:23 +01:00
PCI and IRQ rework, pci.c rewritten from ground up, fixes numerous issues such as the bridge being added when the number of normal PCI devices equals the number of normal PCI slots, Windows 95 PCI operation on Intel 430NX, sharing of PCI IRQ's with non-PCI level-triggered devices, having both configuration mechanisms operating at the same time (ALi M1435), etc., and makes the code much more readable.
2023-08-07 03:04:52 +02:00
/* PCI bridge stuff. */
extern void pci_bridge_set_ctl(void *priv, uint8_t ctl);
Ported PCI clean-ups from VARCem.
2018-10-21 20:27:57 +02:00
PCI/AGP bridge support, part 1
2020-09-19 00:56:12 -03:00
#ifdef EMU_DEVICE_H
extern const device_t dec21150_device;
Current WIP ALi work.
2021-07-04 18:16:35 +02:00
extern const device_t ali5243_agp_device;
Finished the ALADDiN-PRO II, implemented the Contaq/Cypress 82C596(A) and 82C597 chipsets, added the ASUS P5A, Gigabyte GA-5AX, PC CHIPS M729, and Green-B, removed the "Virtual PC 2007" device as it turns out it was actually SMBus all along, did some fixes to the ALi SMBUS, fixed start LM75 SMBus address and enabled it by default, and added a ASUS P5A-specific version of the Winbond W83781D hardware monitor.
2021-07-12 05:56:06 +02:00
extern const device_t ali5247_agp_device;
PCI/AGP bridge support, part 1
2020-09-19 00:56:12 -03:00
extern const device_t i440lx_agp_device;
extern const device_t i440bx_agp_device;
extern const device_t i440gx_agp_device;
PCI/AGP bridge support, part 2: now with VIA
2020-09-19 01:29:35 -03:00
extern const device_t via_vp3_agp_device;
extern const device_t via_mvp3_agp_device;
extern const device_t via_apro_agp_device;
Apollo ProMedia Implementation Needed for excessive 686A/B development
2020-10-20 20:45:12 +03:00
extern const device_t via_vt8601_agp_device;
PCI/AGP bridge support, part 1
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#endif
clang-format in src/include/86box/
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#endif /*EMU_PCI_H*/
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