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86Box/src/device/hwm_gl518sm.c

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/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the Genesys Logic GL518SM hardware monitoring chip.
*
*
*
* Author: RichardG, <richardg867@gmail.com>
*
* Copyright 2020 RichardG.
*/
#include <math.h>
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#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#define HAVE_STDARG_H
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/i2c.h>
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#include <86box/hwm.h>
#define CLAMP(a, min, max) (((a) < (min)) ? (min) : (((a) > (max)) ? (max) : (a)))
/* Formulas and factors derived from Linux's gl518sm.c driver. */
#define GL518SM_RPMDIV(r, d) (CLAMP((r), 1, 960000) * (d))
#define GL518SM_RPM_TO_REG(r, d) ((r) ? CLAMP((480000 + GL518SM_RPMDIV(r, d) / 2) / GL518SM_RPMDIV(r, d), 1, 255) : 0)
#define GL518SM_VOLTAGE_TO_REG(v) ((uint8_t) round((v) / 19.0))
#define GL518SM_VDD_TO_REG(v) ((uint8_t) (((v) * 4) / 95.0))
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typedef struct {
uint32_t local;
hwm_values_t *values;
uint16_t regs[32];
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uint8_t addr_register: 5;
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uint8_t i2c_addr: 7, i2c_state: 2, i2c_enabled: 1;
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} gl518sm_t;
static uint8_t gl518sm_i2c_start(void *bus, uint8_t addr, uint8_t read, void *priv);
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static uint8_t gl518sm_i2c_read(void *bus, uint8_t addr, void *priv);
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static uint16_t gl518sm_read(gl518sm_t *dev, uint8_t reg);
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static uint8_t gl518sm_i2c_write(void *bus, uint8_t addr, uint8_t data, void *priv);
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static uint8_t gl518sm_write(gl518sm_t *dev, uint8_t reg, uint16_t val);
static void gl518sm_reset(gl518sm_t *dev);
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#ifdef ENABLE_GL518SM_LOG
int gl518sm_do_log = ENABLE_GL518SM_LOG;
static void
gl518sm_log(const char *fmt, ...)
{
va_list ap;
if (gl518sm_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define gl518sm_log(fmt, ...)
#endif
static void
gl518sm_remap(gl518sm_t *dev, uint8_t addr)
{
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gl518sm_log("GL518SM: remapping to SMBus %02Xh\n", addr);
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if (dev->i2c_enabled)
i2c_removehandler(i2c_smbus, dev->i2c_addr, 1, gl518sm_i2c_start, gl518sm_i2c_read, gl518sm_i2c_write, NULL, dev);
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if (addr < 0x80)
i2c_sethandler(i2c_smbus, addr, 1, gl518sm_i2c_start, gl518sm_i2c_read, gl518sm_i2c_write, NULL, dev);
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dev->i2c_addr = addr & 0x7f;
dev->i2c_enabled = !(addr & 0x80);
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}
static uint8_t
gl518sm_i2c_start(void *bus, uint8_t addr, uint8_t read, void *priv)
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{
gl518sm_t *dev = (gl518sm_t *) priv;
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dev->i2c_state = 0;
return 1;
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}
static uint8_t
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gl518sm_i2c_read(void *bus, uint8_t addr, void *priv)
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{
gl518sm_t *dev = (gl518sm_t *) priv;
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uint16_t read = gl518sm_read(dev, dev->addr_register);
uint8_t ret = 0;
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if (dev->i2c_state == 0)
dev->i2c_state = 1;
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if ((dev->i2c_state == 1) && (dev->addr_register >= 0x07) && (dev->addr_register <= 0x0c)) { /* two-byte registers: read MSB first */
dev->i2c_state = 2;
ret = read >> 8;
} else {
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ret = read;
dev->addr_register++;
}
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return ret;
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}
static uint16_t
gl518sm_read(gl518sm_t *dev, uint8_t reg)
{
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uint16_t ret;
reg &= 0x1f;
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switch (reg) {
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case 0x04: /* temperature */
ret = (dev->values->temperatures[0] + 119) & 0xff;
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break;
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case 0x07: /* fan speeds */
ret = GL518SM_RPM_TO_REG(dev->values->fans[0], 1 << ((dev->regs[0x0f] >> 6) & 0x3)) << 8;
ret |= GL518SM_RPM_TO_REG(dev->values->fans[1], 1 << ((dev->regs[0x0f] >> 4) & 0x3));
break;
case 0x0d: /* VIN3 */
ret = GL518SM_VOLTAGE_TO_REG(dev->values->voltages[2]);
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break;
case 0x13: /* VIN2 */
ret = GL518SM_VOLTAGE_TO_REG(dev->values->voltages[1]);
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break;
case 0x14: /* VIN1 */
ret = GL518SM_VOLTAGE_TO_REG(dev->values->voltages[0]);
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break;
case 0x15: /* VDD */
ret = GL518SM_VDD_TO_REG(dev->values->voltages[3]);
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break;
default: /* other registers */
ret = dev->regs[reg];
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break;
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}
gl518sm_log("GL518SM: read(%02X) = %04X\n", reg, ret);
return ret;
}
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static uint8_t
gl518sm_i2c_write(void *bus, uint8_t addr, uint8_t data, void *priv)
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{
gl518sm_t *dev = (gl518sm_t *) priv;
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switch (dev->i2c_state++) {
case 0:
dev->addr_register = data;
break;
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case 1:
gl518sm_write(dev, dev->addr_register, (gl518sm_read(dev, dev->addr_register) & 0xff00) | data);
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break;
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case 2:
gl518sm_write(dev, dev->addr_register, (gl518sm_read(dev, dev->addr_register) << 8) | data);
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break;
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default:
dev->i2c_state = 3;
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return 0;
}
return 1;
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}
static uint8_t
gl518sm_write(gl518sm_t *dev, uint8_t reg, uint16_t val)
{
gl518sm_log("GL518SM: write(%02X, %04X)\n", reg, val);
switch (reg) {
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case 0x00: case 0x01: case 0x04: case 0x07: case 0x0d: case 0x12: case 0x13: case 0x14: case 0x15:
/* read-only registers */
return 0;
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case 0x0a:
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dev->regs[0x13] = val & 0xff;
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break;
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case 0x03:
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dev->regs[reg] = val & 0xfc;
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if (val & 0x80) /* Init */
gl518sm_reset(dev);
break;
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case 0x0f:
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dev->regs[reg] = val & 0xf8;
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break;
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case 0x11:
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dev->regs[reg] = val & 0x7f;
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break;
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default:
dev->regs[reg] = val;
break;
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}
return 1;
}
static void
gl518sm_reset(gl518sm_t *dev)
{
memset(dev->regs, 0, sizeof(dev->regs));
dev->regs[0x00] = 0x80;
dev->regs[0x01] = 0x80; /* revision 0x80 can read all voltages */
dev->regs[0x05] = 0xc7;
dev->regs[0x06] = 0xc2;
dev->regs[0x08] = 0x6464;
dev->regs[0x09] = 0xdac5;
dev->regs[0x0a] = 0xdac5;
dev->regs[0x0b] = 0xdac5;
dev->regs[0x0c] = 0xdac5;
dev->regs[0x0f] = 0x00;
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gl518sm_remap(dev, dev->i2c_addr | (dev->i2c_enabled ? 0x00 : 0x80));
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}
static void
gl518sm_close(void *priv)
{
gl518sm_t *dev = (gl518sm_t *) priv;
gl518sm_remap(dev, 0);
free(dev);
}
static void *
gl518sm_init(const device_t *info)
{
gl518sm_t *dev = (gl518sm_t *) malloc(sizeof(gl518sm_t));
memset(dev, 0, sizeof(gl518sm_t));
dev->local = info->local;
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/* Set default values. */
hwm_values_t defaults = {
{ /* fan speeds */
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3000, /* usually Chassis */
3000 /* usually CPU */
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}, { /* temperatures */
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30 /* usually CPU */
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}, { /* voltages */
hwm_get_vcore(), /* Vcore */
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RESISTOR_DIVIDER(12000, 150, 47), /* +12V (15K/4.7K divider suggested in the datasheet) */
3300, /* +3.3V */
5000 /* +5V */
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}
};
hwm_values = defaults;
dev->values = &hwm_values;
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gl518sm_reset(dev);
gl518sm_remap(dev, dev->local & 0x7f);
return dev;
}
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/* GL518SM on SMBus address 2Ch */
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const device_t gl518sm_2c_device = {
"Genesys Logic GL518SM Hardware Monitor",
DEVICE_ISA,
0x2c,
gl518sm_init, gl518sm_close, NULL,
WARNING: CONFIGS MIGHT PARTIALLY BREAK WHERE DEVICE NAMES HAVE CHANGED. Changes to device_t struct to accomodate the upcoming PCI IRQ arbitration rewrite; Added device.c/h API to obtain name from the device_t struct; Significant changes to win/win_settings.c to clean up the code a bit and fix bugs; Ported all the CPU and AudioPCI commits from PCem; Added an API call to allow ACPI soft power off to gracefully stop the emulator; Removed the Siemens PCD-2L from the Dev branch because it now works; Removed the Socket 5 HP Vectra from the Dev branch because it now works; Fixed the Compaq Presario and the Micronics Spitfire; Give the IBM PC330 its own list of 486 CPU so it can have DX2's with CPUID 0x470; SMM fixes; Rewrote the SYSENTER, SYSEXIT, SYSCALL, and SYSRET instructions; Changed IDE reset period to match the specification, fixes #929; The keyboard input and output ports are now forced in front of the queue when read, fixes a number of bugs, including the AMI Apollo hanging on soft reset; Added the Intel AN430TX but Dev branched because it does not work; The network code no longer drops packets if the emulated network card has failed to receive them (eg. when the buffer is full); Changes to PCI card adding and renamed some PCI slot types, also added proper AGP bridge slot types; USB UHCI emulation is no longer a stub (still doesn't fully work, but at least Windows XP chk with Debug no longer ASSERT's on it); Fixed NVR on the the SMC FDC37C932QF and APM variants; A number of fixes to Intel 4x0 chipsets, including fixing every register of the 440LX and 440EX; Some ACPI changes.
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{ NULL }, NULL, NULL,
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NULL
};
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/* GL518SM on SMBus address 2Dh */
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const device_t gl518sm_2d_device = {
"Genesys Logic GL518SM Hardware Monitor",
DEVICE_ISA,
0x2d,
gl518sm_init, gl518sm_close, NULL,
WARNING: CONFIGS MIGHT PARTIALLY BREAK WHERE DEVICE NAMES HAVE CHANGED. Changes to device_t struct to accomodate the upcoming PCI IRQ arbitration rewrite; Added device.c/h API to obtain name from the device_t struct; Significant changes to win/win_settings.c to clean up the code a bit and fix bugs; Ported all the CPU and AudioPCI commits from PCem; Added an API call to allow ACPI soft power off to gracefully stop the emulator; Removed the Siemens PCD-2L from the Dev branch because it now works; Removed the Socket 5 HP Vectra from the Dev branch because it now works; Fixed the Compaq Presario and the Micronics Spitfire; Give the IBM PC330 its own list of 486 CPU so it can have DX2's with CPUID 0x470; SMM fixes; Rewrote the SYSENTER, SYSEXIT, SYSCALL, and SYSRET instructions; Changed IDE reset period to match the specification, fixes #929; The keyboard input and output ports are now forced in front of the queue when read, fixes a number of bugs, including the AMI Apollo hanging on soft reset; Added the Intel AN430TX but Dev branched because it does not work; The network code no longer drops packets if the emulated network card has failed to receive them (eg. when the buffer is full); Changes to PCI card adding and renamed some PCI slot types, also added proper AGP bridge slot types; USB UHCI emulation is no longer a stub (still doesn't fully work, but at least Windows XP chk with Debug no longer ASSERT's on it); Fixed NVR on the the SMC FDC37C932QF and APM variants; A number of fixes to Intel 4x0 chipsets, including fixing every register of the 440LX and 440EX; Some ACPI changes.
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{ NULL }, NULL, NULL,
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NULL
};