2023-08-22 13:33:49 -04:00
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#define OP_XCHG_AX_(reg) \
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static uint32_t \
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ropXCHG_AX_##reg(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
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{ \
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int ax_reg, host_reg, temp_reg; \
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\
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ax_reg = LOAD_REG_W(REG_AX); \
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host_reg = LOAD_REG_W(REG_##reg); \
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temp_reg = COPY_REG(host_reg); \
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STORE_REG_TARGET_W_RELEASE(ax_reg, REG_##reg); \
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STORE_REG_TARGET_W_RELEASE(temp_reg, REG_AX); \
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\
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return op_pc; \
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2022-11-19 09:49:14 -05:00
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}
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2020-06-13 10:53:11 +02:00
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OP_XCHG_AX_(BX)
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OP_XCHG_AX_(CX)
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OP_XCHG_AX_(DX)
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OP_XCHG_AX_(SI)
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OP_XCHG_AX_(DI)
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OP_XCHG_AX_(SP)
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OP_XCHG_AX_(BP)
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2023-08-22 13:33:49 -04:00
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#define OP_XCHG_EAX_(reg) \
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static uint32_t \
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ropXCHG_EAX_##reg(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
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{ \
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int eax_reg, host_reg, temp_reg; \
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\
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eax_reg = LOAD_REG_L(REG_EAX); \
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host_reg = LOAD_REG_L(REG_##reg); \
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temp_reg = COPY_REG(host_reg); \
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STORE_REG_TARGET_L_RELEASE(eax_reg, REG_##reg); \
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STORE_REG_TARGET_L_RELEASE(temp_reg, REG_EAX); \
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\
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return op_pc; \
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2022-11-19 09:49:14 -05:00
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}
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2020-06-13 10:53:11 +02:00
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OP_XCHG_EAX_(EBX)
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OP_XCHG_EAX_(ECX)
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OP_XCHG_EAX_(EDX)
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OP_XCHG_EAX_(ESI)
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OP_XCHG_EAX_(EDI)
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OP_XCHG_EAX_(ESP)
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OP_XCHG_EAX_(EBP)
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2022-11-19 09:49:14 -05:00
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static uint32_t
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ropXCHG_b(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
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2020-06-13 10:53:11 +02:00
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{
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2023-06-01 18:32:25 -04:00
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int src_reg;
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int dst_reg;
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int temp_reg;
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2020-06-13 10:53:11 +02:00
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2022-11-19 09:49:14 -05:00
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if ((fetchdat & 0xc0) != 0xc0)
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return 0;
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2020-06-13 10:53:11 +02:00
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2022-11-19 09:49:14 -05:00
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dst_reg = LOAD_REG_B(fetchdat & 7);
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src_reg = LOAD_REG_B((fetchdat >> 3) & 7);
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temp_reg = COPY_REG(src_reg);
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STORE_REG_TARGET_B_RELEASE(dst_reg, (fetchdat >> 3) & 7);
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STORE_REG_TARGET_B_RELEASE(temp_reg, fetchdat & 7);
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2022-02-20 02:26:27 -05:00
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2022-11-19 09:49:14 -05:00
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return op_pc + 1;
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2020-06-13 10:53:11 +02:00
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}
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2022-11-19 09:49:14 -05:00
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static uint32_t
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ropXCHG_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
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2020-06-13 10:53:11 +02:00
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{
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2023-06-01 18:32:25 -04:00
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int src_reg;
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int dst_reg;
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int temp_reg;
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2020-06-13 10:53:11 +02:00
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2022-11-19 09:49:14 -05:00
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if ((fetchdat & 0xc0) != 0xc0)
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return 0;
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2020-06-13 10:53:11 +02:00
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2022-11-19 09:49:14 -05:00
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dst_reg = LOAD_REG_W(fetchdat & 7);
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src_reg = LOAD_REG_W((fetchdat >> 3) & 7);
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temp_reg = COPY_REG(src_reg);
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STORE_REG_TARGET_W_RELEASE(dst_reg, (fetchdat >> 3) & 7);
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STORE_REG_TARGET_W_RELEASE(temp_reg, fetchdat & 7);
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2022-02-20 02:26:27 -05:00
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2022-11-19 09:49:14 -05:00
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return op_pc + 1;
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2020-06-13 10:53:11 +02:00
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}
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2022-11-19 09:49:14 -05:00
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static uint32_t
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ropXCHG_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
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2020-06-13 10:53:11 +02:00
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{
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2023-06-01 18:32:25 -04:00
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int src_reg;
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int dst_reg;
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int temp_reg;
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2020-06-13 10:53:11 +02:00
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2022-11-19 09:49:14 -05:00
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if ((fetchdat & 0xc0) != 0xc0)
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return 0;
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2020-06-13 10:53:11 +02:00
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2022-11-19 09:49:14 -05:00
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dst_reg = LOAD_REG_L(fetchdat & 7);
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src_reg = LOAD_REG_L((fetchdat >> 3) & 7);
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temp_reg = COPY_REG(src_reg);
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STORE_REG_TARGET_L_RELEASE(dst_reg, (fetchdat >> 3) & 7);
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STORE_REG_TARGET_L_RELEASE(temp_reg, fetchdat & 7);
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2022-02-20 02:26:27 -05:00
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2022-11-19 09:49:14 -05:00
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return op_pc + 1;
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2020-06-13 10:53:11 +02:00
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}
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