2020-06-14 21:59:45 +02:00
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/*
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2023-01-06 15:36:05 -05:00
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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2020-06-14 21:59:45 +02:00
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*
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2023-01-06 15:36:05 -05:00
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* This file is part of the 86Box distribution.
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2020-06-14 21:59:45 +02:00
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*
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2023-01-06 15:36:05 -05:00
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* Emulation of the NatSemi PC87332 Super I/O chip.
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2020-06-14 21:59:45 +02:00
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*
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*
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*
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2023-01-06 15:36:05 -05:00
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* Authors: Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2020 Miran Grca.
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2020-06-14 21:59:45 +02:00
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#include <86box/86box.h>
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#include <86box/io.h>
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#include <86box/timer.h>
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#include <86box/device.h>
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#include <86box/lpt.h>
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#include <86box/mem.h>
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#include <86box/nvr.h>
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#include <86box/pci.h>
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#include <86box/rom.h>
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#include <86box/serial.h>
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#include <86box/hdc.h>
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#include <86box/hdc_ide.h>
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#include <86box/fdd.h>
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#include <86box/fdc.h>
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#include <86box/sio.h>
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2023-06-28 13:46:28 -04:00
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typedef struct pc87332_t {
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uint8_t tries;
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uint8_t has_ide;
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uint8_t fdc_on;
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uint8_t regs[15];
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2022-09-18 17:17:00 -04:00
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int cur_reg;
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fdc_t *fdc;
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2020-06-14 21:59:45 +02:00
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serial_t *uart[2];
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} pc87332_t;
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static void
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lpt1_handler(pc87332_t *dev)
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{
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2022-09-18 17:17:00 -04:00
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int temp;
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2022-03-09 21:57:51 -05:00
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uint16_t lpt_port = LPT1_ADDR;
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2022-09-18 17:17:00 -04:00
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uint8_t lpt_irq = LPT2_IRQ;
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2020-06-14 21:59:45 +02:00
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temp = dev->regs[0x01] & 3;
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switch (temp) {
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2022-09-18 17:17:00 -04:00
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case 0:
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lpt_port = LPT1_ADDR;
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lpt_irq = (dev->regs[0x02] & 0x08) ? LPT1_IRQ : LPT2_IRQ;
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break;
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case 1:
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lpt_port = LPT_MDA_ADDR;
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lpt_irq = LPT_MDA_IRQ;
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break;
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case 2:
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lpt_port = LPT2_ADDR;
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lpt_irq = LPT2_IRQ;
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break;
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case 3:
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lpt_port = 0x000;
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lpt_irq = 0xff;
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break;
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2023-06-28 13:46:28 -04:00
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default:
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break;
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2020-06-14 21:59:45 +02:00
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}
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if (lpt_port)
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2022-09-18 17:17:00 -04:00
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lpt1_init(lpt_port);
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2020-06-14 21:59:45 +02:00
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lpt1_irq(lpt_irq);
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}
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static void
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serial_handler(pc87332_t *dev, int uart)
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{
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int temp;
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temp = (dev->regs[1] >> (2 << uart)) & 3;
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switch (temp) {
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2022-09-18 17:17:00 -04:00
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case 0:
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serial_setup(dev->uart[uart], COM1_ADDR, 4);
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break;
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case 1:
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serial_setup(dev->uart[uart], COM2_ADDR, 3);
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break;
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case 2:
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switch ((dev->regs[1] >> 6) & 3) {
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case 0:
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serial_setup(dev->uart[uart], COM3_ADDR, COM3_IRQ);
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break;
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case 1:
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serial_setup(dev->uart[uart], 0x338, COM3_IRQ);
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break;
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case 2:
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serial_setup(dev->uart[uart], COM4_ADDR, COM3_IRQ);
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break;
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case 3:
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serial_setup(dev->uart[uart], 0x220, COM3_IRQ);
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break;
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2023-06-28 13:46:28 -04:00
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default:
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break;
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2022-09-18 17:17:00 -04:00
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}
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break;
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case 3:
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switch ((dev->regs[1] >> 6) & 3) {
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case 0:
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serial_setup(dev->uart[uart], COM4_ADDR, COM4_IRQ);
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break;
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case 1:
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serial_setup(dev->uart[uart], 0x238, COM4_IRQ);
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break;
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case 2:
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serial_setup(dev->uart[uart], 0x2e0, COM4_IRQ);
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break;
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case 3:
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serial_setup(dev->uart[uart], 0x228, COM4_IRQ);
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break;
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2023-06-28 13:46:28 -04:00
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default:
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break;
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2022-09-18 17:17:00 -04:00
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}
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break;
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2023-06-28 13:46:28 -04:00
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default:
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break;
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2020-06-14 21:59:45 +02:00
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}
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}
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2021-04-06 07:17:38 +02:00
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static void
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ide_handler(pc87332_t *dev)
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{
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/* TODO: Make an ide_disable(channel) and ide_enable(channel) so we can simplify this. */
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if (dev->has_ide == 2) {
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2022-09-18 17:17:00 -04:00
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ide_sec_disable();
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ide_set_base(1, (dev->regs[0x00] & 0x80) ? 0x170 : 0x1f0);
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ide_set_side(1, (dev->regs[0x00] & 0x80) ? 0x376 : 0x3f6);
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if (dev->regs[0x00] & 0x40)
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ide_sec_enable();
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2021-04-06 07:17:38 +02:00
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} else if (dev->has_ide == 1) {
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2022-09-18 17:17:00 -04:00
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ide_pri_disable();
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ide_set_base(0, (dev->regs[0x00] & 0x80) ? 0x170 : 0x1f0);
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ide_set_side(0, (dev->regs[0x00] & 0x80) ? 0x376 : 0x3f6);
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if (dev->regs[0x00] & 0x40)
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ide_pri_enable();
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2021-04-06 07:17:38 +02:00
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}
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}
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2020-06-14 21:59:45 +02:00
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static void
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pc87332_write(uint16_t port, uint8_t val, void *priv)
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{
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pc87332_t *dev = (pc87332_t *) priv;
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2023-05-29 01:30:51 -04:00
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uint8_t index;
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uint8_t valxor;
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2020-06-14 21:59:45 +02:00
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index = (port & 1) ? 0 : 1;
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if (index) {
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2022-09-18 17:17:00 -04:00
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dev->cur_reg = val & 0x1f;
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dev->tries = 0;
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return;
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2020-06-14 21:59:45 +02:00
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} else {
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2022-09-18 17:17:00 -04:00
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if (dev->tries) {
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valxor = val ^ dev->regs[dev->cur_reg];
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dev->tries = 0;
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if ((dev->cur_reg <= 14) && (dev->cur_reg != 8))
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dev->regs[dev->cur_reg] = val;
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else
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return;
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} else {
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dev->tries++;
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return;
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}
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2020-06-14 21:59:45 +02:00
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}
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2022-09-18 17:17:00 -04:00
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switch (dev->cur_reg) {
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case 0:
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if (valxor & 1) {
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lpt1_remove();
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if ((val & 1) && !(dev->regs[2] & 1))
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lpt1_handler(dev);
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}
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if (valxor & 2) {
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serial_remove(dev->uart[0]);
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if ((val & 2) && !(dev->regs[2] & 1))
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serial_handler(dev, 0);
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}
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if (valxor & 4) {
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serial_remove(dev->uart[1]);
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if ((val & 4) && !(dev->regs[2] & 1))
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serial_handler(dev, 1);
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}
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if (valxor & 0x28) {
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fdc_remove(dev->fdc);
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if ((val & 8) && !(dev->regs[2] & 1))
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fdc_set_base(dev->fdc, (val & 0x20) ? FDC_SECONDARY_ADDR : FDC_PRIMARY_ADDR);
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}
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if (dev->has_ide && (valxor & 0xc0))
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ide_handler(dev);
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break;
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case 1:
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if (valxor & 3) {
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lpt1_remove();
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if ((dev->regs[0] & 1) && !(dev->regs[2] & 1))
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lpt1_handler(dev);
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}
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if (valxor & 0xcc) {
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serial_remove(dev->uart[0]);
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if ((dev->regs[0] & 2) && !(dev->regs[2] & 1))
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serial_handler(dev, 0);
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}
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if (valxor & 0xf0) {
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serial_remove(dev->uart[1]);
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if ((dev->regs[0] & 4) && !(dev->regs[2] & 1))
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serial_handler(dev, 1);
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}
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break;
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case 2:
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if (valxor & 1) {
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lpt1_remove();
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serial_remove(dev->uart[0]);
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serial_remove(dev->uart[1]);
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fdc_remove(dev->fdc);
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if (!(val & 1)) {
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if (dev->regs[0] & 1)
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lpt1_handler(dev);
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if (dev->regs[0] & 2)
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serial_handler(dev, 0);
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if (dev->regs[0] & 4)
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serial_handler(dev, 1);
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if (dev->regs[0] & 8)
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fdc_set_base(dev->fdc, (dev->regs[0] & 0x20) ? FDC_SECONDARY_ADDR : FDC_PRIMARY_ADDR);
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}
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}
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if (valxor & 8) {
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lpt1_remove();
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if ((dev->regs[0] & 1) && !(dev->regs[2] & 1))
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lpt1_handler(dev);
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}
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break;
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2023-06-28 13:46:28 -04:00
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default:
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break;
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2020-06-14 21:59:45 +02:00
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}
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}
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uint8_t
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pc87332_read(uint16_t port, void *priv)
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{
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pc87332_t *dev = (pc87332_t *) priv;
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2023-05-29 01:30:51 -04:00
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uint8_t ret = 0xff;
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uint8_t index;
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2020-06-14 21:59:45 +02:00
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index = (port & 1) ? 0 : 1;
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dev->tries = 0;
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if (index)
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2022-09-18 17:17:00 -04:00
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ret = dev->cur_reg & 0x1f;
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2020-06-14 21:59:45 +02:00
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else {
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2022-09-18 17:17:00 -04:00
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if (dev->cur_reg == 8)
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ret = 0x10;
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else if (dev->cur_reg < 14)
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ret = dev->regs[dev->cur_reg];
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2020-06-14 21:59:45 +02:00
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}
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return ret;
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}
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void
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pc87332_reset(pc87332_t *dev)
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{
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memset(dev->regs, 0, 15);
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2021-04-29 07:36:16 +02:00
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dev->regs[0x00] = dev->fdc_on ? 0x4f : 0x07;
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2021-04-06 07:17:38 +02:00
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if (dev->has_ide == 2)
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2022-09-18 17:17:00 -04:00
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dev->regs[0x00] |= 0x80;
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2020-06-14 21:59:45 +02:00
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dev->regs[0x01] = 0x10;
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dev->regs[0x03] = 0x01;
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dev->regs[0x05] = 0x0D;
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dev->regs[0x08] = 0x70;
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/*
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2022-09-18 17:17:00 -04:00
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0 = 360 rpm @ 500 kbps for 3.5"
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2023-01-06 15:36:29 -05:00
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1 = Default, 300 rpm @ 500, 300, 250, 1000 kbps for 3.5"
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2020-06-14 21:59:45 +02:00
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*/
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lpt1_remove();
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lpt1_handler(dev);
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serial_remove(dev->uart[0]);
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serial_remove(dev->uart[1]);
|
|
|
|
|
serial_handler(dev, 0);
|
|
|
|
|
serial_handler(dev, 1);
|
|
|
|
|
fdc_reset(dev->fdc);
|
2021-04-29 07:36:16 +02:00
|
|
|
if (!dev->fdc_on)
|
2022-09-18 17:17:00 -04:00
|
|
|
fdc_remove(dev->fdc);
|
2021-04-06 07:17:38 +02:00
|
|
|
|
|
|
|
|
if (dev->has_ide)
|
2022-09-18 17:17:00 -04:00
|
|
|
ide_handler(dev);
|
2020-06-14 21:59:45 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
pc87332_close(void *priv)
|
|
|
|
|
{
|
|
|
|
|
pc87332_t *dev = (pc87332_t *) priv;
|
|
|
|
|
|
|
|
|
|
free(dev);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void *
|
|
|
|
|
pc87332_init(const device_t *info)
|
|
|
|
|
{
|
|
|
|
|
pc87332_t *dev = (pc87332_t *) malloc(sizeof(pc87332_t));
|
|
|
|
|
memset(dev, 0, sizeof(pc87332_t));
|
|
|
|
|
|
|
|
|
|
dev->fdc = device_add(&fdc_at_nsc_device);
|
|
|
|
|
|
|
|
|
|
dev->uart[0] = device_add_inst(&ns16550_device, 1);
|
|
|
|
|
dev->uart[1] = device_add_inst(&ns16550_device, 2);
|
|
|
|
|
|
2021-04-06 07:17:38 +02:00
|
|
|
dev->has_ide = (info->local >> 8) & 0xff;
|
2022-09-18 17:17:00 -04:00
|
|
|
dev->fdc_on = (info->local >> 16) & 0xff;
|
2020-06-14 21:59:45 +02:00
|
|
|
pc87332_reset(dev);
|
|
|
|
|
|
2023-05-29 01:30:51 -04:00
|
|
|
if ((info->local & 0xff) == 0x01) {
|
2022-09-18 17:17:00 -04:00
|
|
|
io_sethandler(0x398, 0x0002,
|
|
|
|
|
pc87332_read, NULL, NULL, pc87332_write, NULL, NULL, dev);
|
2020-06-30 15:49:47 +02:00
|
|
|
} else {
|
2022-09-18 17:17:00 -04:00
|
|
|
io_sethandler(0x02e, 0x0002,
|
|
|
|
|
pc87332_read, NULL, NULL, pc87332_write, NULL, NULL, dev);
|
2020-06-30 15:49:47 +02:00
|
|
|
}
|
2020-06-14 21:59:45 +02:00
|
|
|
|
|
|
|
|
return dev;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
const device_t pc87332_device = {
|
2022-09-18 17:17:00 -04:00
|
|
|
.name = "National Semiconductor PC87332 Super I/O",
|
2022-03-13 09:57:57 -04:00
|
|
|
.internal_name = "pc87332",
|
2022-09-18 17:17:00 -04:00
|
|
|
.flags = 0,
|
|
|
|
|
.local = 0x00,
|
|
|
|
|
.init = pc87332_init,
|
|
|
|
|
.close = pc87332_close,
|
|
|
|
|
.reset = NULL,
|
2022-03-13 09:57:57 -04:00
|
|
|
{ .available = NULL },
|
|
|
|
|
.speed_changed = NULL,
|
2022-09-18 17:17:00 -04:00
|
|
|
.force_redraw = NULL,
|
|
|
|
|
.config = NULL
|
2021-04-06 07:17:38 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
const device_t pc87332_398_device = {
|
2022-09-18 17:17:00 -04:00
|
|
|
.name = "National Semiconductor PC87332 Super I/O (Port 398h)",
|
2022-03-13 09:57:57 -04:00
|
|
|
.internal_name = "pc87332_398",
|
2022-09-18 17:17:00 -04:00
|
|
|
.flags = 0,
|
|
|
|
|
.local = 0x01,
|
|
|
|
|
.init = pc87332_init,
|
|
|
|
|
.close = pc87332_close,
|
|
|
|
|
.reset = NULL,
|
2022-03-13 09:57:57 -04:00
|
|
|
{ .available = NULL },
|
|
|
|
|
.speed_changed = NULL,
|
2022-09-18 17:17:00 -04:00
|
|
|
.force_redraw = NULL,
|
|
|
|
|
.config = NULL
|
2020-06-14 21:59:45 +02:00
|
|
|
};
|
2020-06-30 15:49:47 +02:00
|
|
|
|
2021-04-06 07:17:38 +02:00
|
|
|
const device_t pc87332_398_ide_device = {
|
2022-09-18 17:17:00 -04:00
|
|
|
.name = "National Semiconductor PC87332 Super I/O (Port 398h) (With IDE)",
|
2022-03-13 09:57:57 -04:00
|
|
|
.internal_name = "pc87332_398_ide",
|
2022-09-18 17:17:00 -04:00
|
|
|
.flags = 0,
|
|
|
|
|
.local = 0x101,
|
|
|
|
|
.init = pc87332_init,
|
|
|
|
|
.close = pc87332_close,
|
|
|
|
|
.reset = NULL,
|
2022-03-13 09:57:57 -04:00
|
|
|
{ .available = NULL },
|
|
|
|
|
.speed_changed = NULL,
|
2022-09-18 17:17:00 -04:00
|
|
|
.force_redraw = NULL,
|
|
|
|
|
.config = NULL
|
2020-06-30 15:49:47 +02:00
|
|
|
};
|
2021-04-29 07:36:16 +02:00
|
|
|
|
2021-07-04 17:40:39 +02:00
|
|
|
const device_t pc87332_398_ide_sec_device = {
|
2022-09-18 17:17:00 -04:00
|
|
|
.name = "National Semiconductor PC87332 Super I/O (Port 398h) (With Secondary IDE)",
|
2022-03-13 09:57:57 -04:00
|
|
|
.internal_name = "pc87332_398_ide_sec",
|
2022-09-18 17:17:00 -04:00
|
|
|
.flags = 0,
|
|
|
|
|
.local = 0x201,
|
|
|
|
|
.init = pc87332_init,
|
|
|
|
|
.close = pc87332_close,
|
|
|
|
|
.reset = NULL,
|
2022-03-13 09:57:57 -04:00
|
|
|
{ .available = NULL },
|
|
|
|
|
.speed_changed = NULL,
|
2022-09-18 17:17:00 -04:00
|
|
|
.force_redraw = NULL,
|
|
|
|
|
.config = NULL
|
2021-07-04 17:40:39 +02:00
|
|
|
};
|
|
|
|
|
|
2021-04-29 07:36:16 +02:00
|
|
|
const device_t pc87332_398_ide_fdcon_device = {
|
2022-09-18 17:17:00 -04:00
|
|
|
.name = "National Semiconductor PC87332 Super I/O (Port 398h) (With IDE and FDC on)",
|
2022-03-13 09:57:57 -04:00
|
|
|
.internal_name = "pc87332_398_ide_fdcon",
|
2022-09-18 17:17:00 -04:00
|
|
|
.flags = 0,
|
|
|
|
|
.local = 0x10101,
|
|
|
|
|
.init = pc87332_init,
|
|
|
|
|
.close = pc87332_close,
|
|
|
|
|
.reset = NULL,
|
2022-03-13 09:57:57 -04:00
|
|
|
{ .available = NULL },
|
|
|
|
|
.speed_changed = NULL,
|
2022-09-18 17:17:00 -04:00
|
|
|
.force_redraw = NULL,
|
|
|
|
|
.config = NULL
|
2021-04-29 07:36:16 +02:00
|
|
|
};
|