2021-07-04 17:40:39 +02:00
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/*
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2022-11-13 16:37:58 -05:00
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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2021-07-04 17:40:39 +02:00
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*
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2022-11-13 16:37:58 -05:00
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* This file is part of the 86Box distribution.
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2021-07-04 17:40:39 +02:00
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*
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2022-11-13 16:37:58 -05:00
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* Implementation of Socket 4 machines.
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2021-07-04 17:40:39 +02:00
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*
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2023-08-14 21:51:47 +02:00
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* Authors: Miran Grca, <mgrca8@gmail.com>
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2021-07-04 17:40:39 +02:00
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*
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2025-08-13 23:43:51 +02:00
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* Copyright 2016-2025 Miran Grca.
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2021-07-04 17:40:39 +02:00
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#include <86box/86box.h>
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#include <86box/mem.h>
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#include <86box/io.h>
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#include <86box/rom.h>
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#include <86box/pci.h>
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#include <86box/device.h>
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#include <86box/chipset.h>
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#include <86box/fdc_ext.h>
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#include <86box/hdc.h>
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#include <86box/hdc_ide.h>
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#include <86box/timer.h>
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#include <86box/fdd.h>
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#include <86box/fdc.h>
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#include <86box/keyboard.h>
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#include <86box/flash.h>
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#include <86box/nvr.h>
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#include <86box/scsi_ncr53c8xx.h>
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#include <86box/sio.h>
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2022-07-27 15:17:53 -04:00
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#include <86box/timer.h>
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2021-07-04 17:40:39 +02:00
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#include <86box/video.h>
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#include <86box/machine.h>
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2025-08-13 23:43:51 +02:00
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/* i430LX */
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2025-06-28 20:48:50 +02:00
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static const device_config_t v12p_config[] = {
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// clang-format off
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{
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2025-07-14 16:28:02 +03:00
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.name = "bios",
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.description = "BIOS Version",
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2025-06-28 20:48:50 +02:00
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.type = CONFIG_BIOS,
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2025-07-14 16:28:02 +03:00
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.default_string = "v12p",
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2025-06-28 20:48:50 +02:00
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.default_int = 0,
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.file_filter = "",
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.spinner = { 0 }, /*W1*/
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.bios = {
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2025-07-14 16:28:02 +03:00
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{ .name = "Acer BIOS V1.2 - Revision R1.4", .internal_name = "v12p_r14", .bios_type = BIOS_NORMAL,
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2025-06-28 20:48:50 +02:00
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.files_no = 1, .local = 0, .size = 131072, .files = { "roms/machines/v12p/v12p_14.bin", "" } },
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2025-07-14 16:28:02 +03:00
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{ .name = "Acer BIOS V1.2 - Revision R1.6", .internal_name = "v12p", .bios_type = BIOS_NORMAL,
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2025-06-28 20:48:50 +02:00
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.files_no = 1, .local = 0, .size = 131072, .files = { "roms/machines/v12p/v12p_16.bin", "" } },
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2025-07-14 16:28:02 +03:00
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{ .files_no = 0 }
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2025-06-28 20:48:50 +02:00
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},
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},
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{ .name = "", .description = "", .type = CONFIG_END }
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// clang-format on
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};
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const device_t v12p_device = {
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.name = "Acer V12P",
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2025-07-14 16:28:02 +03:00
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.internal_name = "v12p_device",
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2025-06-28 20:48:50 +02:00
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.flags = 0,
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.local = 0,
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.init = NULL,
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.close = NULL,
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.reset = NULL,
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.available = NULL,
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.speed_changed = NULL,
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.force_redraw = NULL,
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2025-07-14 16:28:02 +03:00
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.config = v12p_config
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2025-06-28 20:48:50 +02:00
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};
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2025-08-13 23:43:51 +02:00
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int
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machine_at_v12p_init(const machine_t *model)
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2021-07-04 17:40:39 +02:00
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{
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2025-08-13 23:43:51 +02:00
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int ret = 0;
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const char* fn;
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/* No ROMs available */
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if (!device_available(model->device))
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return ret;
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device_context(model->device);
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fn = device_get_bios_file(machine_get_device(machine), device_get_config_bios("bios"), 0);
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ret = bios_load_linear(fn, 0x000e0000, 131072, 0);
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device_context_restore();
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machine_at_common_init(model);
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device_add(&ide_isa_device);
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pci_init(PCI_CONFIG_TYPE_2 | PCI_NO_IRQ_STEERING);
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pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
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pci_register_slot(0x01, PCI_CARD_SCSI, 1, 4, 3, 2);
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pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 2, 1, 4, 3);
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pci_register_slot(0x03, PCI_CARD_NORMAL, 3, 2, 1, 4);
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pci_register_slot(0x04, PCI_CARD_NORMAL, 4, 0, 0, 0);
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pci_register_slot(0x05, PCI_CARD_NORMAL, 0, 0, 0, 0);
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device_add(&i430lx_device);
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device_add(&kbc_ps2_acer_pci_device);
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device_add(&sio_zb_device);
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device_add_params(&pc87310_device, (void *) (PC87310_ALI));
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device_add(&amd_am28f010_flash_device);
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return ret;
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}
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int
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machine_at_ambradp60_init(const machine_t *model)
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{
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int ret;
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ret = bios_load_linear_combined("roms/machines/ambradp60/1004AF1P.BIO",
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"roms/machines/ambradp60/1004AF1P.BI1",
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0x1c000, 128);
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if (bios_only || !ret)
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return ret;
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2025-04-02 18:46:35 +02:00
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machine_at_common_init_ex(model, 2);
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2025-04-02 18:45:27 +02:00
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device_add(&amstrad_megapc_nvr_device);
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2025-08-13 23:43:51 +02:00
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device_add(&ide_pci_device);
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2021-07-04 17:40:39 +02:00
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2025-08-13 23:43:51 +02:00
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pci_init(PCI_CONFIG_TYPE_2);
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2021-07-04 17:40:39 +02:00
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pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
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2023-01-06 15:36:05 -05:00
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pci_register_slot(0x01, PCI_CARD_IDE, 0, 0, 0, 0);
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pci_register_slot(0x06, PCI_CARD_NORMAL, 3, 2, 1, 4);
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pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 1, 3, 4);
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pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 3, 2, 4);
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2021-07-04 17:40:39 +02:00
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pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
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2025-07-27 15:23:43 +02:00
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device_add(&kbc_ps2_phoenix_device);
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2021-07-04 17:40:39 +02:00
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device_add(&sio_zb_device);
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2025-08-13 23:43:51 +02:00
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device_add_params(&fdc37c6xx_device, (void *) (FDC37C665 | FDC37C6XX_IDE_PRI));
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2021-07-04 17:40:39 +02:00
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device_add(&intel_flash_bxt_ami_device);
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2025-08-13 23:43:51 +02:00
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device_add(&i430lx_device);
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2021-07-04 17:40:39 +02:00
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2025-08-13 23:43:51 +02:00
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return ret;
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2021-07-04 17:40:39 +02:00
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}
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2021-08-21 18:19:10 +02:00
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int
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2021-11-14 14:28:22 -03:00
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machine_at_excaliburpci_init(const machine_t *model)
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2021-08-21 18:19:10 +02:00
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{
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int ret;
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2021-11-14 14:28:22 -03:00
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ret = bios_load_linear_inverted("roms/machines/excaliburpci/S701P.ROM",
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2022-07-27 15:17:53 -04:00
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0x000e0000, 131072, 0);
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2021-08-21 18:19:10 +02:00
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if (bios_only || !ret)
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2022-07-27 15:17:53 -04:00
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return ret;
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2021-08-21 18:19:10 +02:00
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machine_at_common_init(model);
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pci_init(PCI_CONFIG_TYPE_2);
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pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
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2023-01-06 15:36:05 -05:00
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pci_register_slot(0x03, PCI_CARD_IDE, 0, 0, 0, 0);
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pci_register_slot(0x0F, PCI_CARD_NORMAL, 1, 2, 3, 4);
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pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 3, 4, 1);
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pci_register_slot(0x0D, PCI_CARD_NORMAL, 3, 4, 1, 2);
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2021-08-21 18:19:10 +02:00
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pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
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2025-08-11 16:36:30 +02:00
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device_add_params(&fdc37c6xx_device, (void *) FDC37C665);
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2025-07-27 15:23:43 +02:00
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device_add(&kbc_ps2_ami_pci_device);
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2021-08-21 18:19:10 +02:00
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device_add(&ide_cmd640_pci_legacy_only_device);
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device_add(&i430lx_device);
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device_add(&sio_zb_device);
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device_add(&intel_flash_bxt_ami_device);
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return ret;
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}
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2021-07-04 17:40:39 +02:00
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int
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machine_at_p5mp3_init(const machine_t *model)
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{
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int ret;
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ret = bios_load_linear("roms/machines/p5mp3/0205.bin",
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2022-07-27 15:17:53 -04:00
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0x000e0000, 131072, 0);
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2021-07-04 17:40:39 +02:00
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if (bios_only || !ret)
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2022-07-27 15:17:53 -04:00
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return ret;
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2021-07-04 17:40:39 +02:00
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machine_at_common_init(model);
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pci_init(PCI_CONFIG_TYPE_2 | PCI_NO_IRQ_STEERING);
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pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
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2023-01-06 15:36:05 -05:00
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pci_register_slot(0x05, PCI_CARD_NORMAL, 1, 2, 3, 4); /* 05 = Slot 1 */
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pci_register_slot(0x04, PCI_CARD_NORMAL, 2, 3, 4, 1); /* 04 = Slot 2 */
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pci_register_slot(0x03, PCI_CARD_NORMAL, 3, 4, 1, 2); /* 03 = Slot 3 */
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2021-07-04 17:40:39 +02:00
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pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
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device_add(&fdc_at_device);
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2025-07-27 15:23:43 +02:00
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device_add(&kbc_ps2_pci_device);
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2021-07-04 17:40:39 +02:00
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2025-08-13 23:43:51 +02:00
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device_add(&i430lx_device);
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2021-07-04 17:40:39 +02:00
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device_add(&sio_zb_device);
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device_add(&catalyst_flash_device);
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return ret;
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}
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int
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machine_at_dellxp60_init(const machine_t *model)
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{
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int ret;
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ret = bios_load_linear_inverted("roms/machines/dellxp60/XP60-A08.ROM",
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2022-07-27 15:17:53 -04:00
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0x000e0000, 131072, 0);
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2022-02-20 02:26:27 -05:00
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2021-07-04 17:40:39 +02:00
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if (bios_only || !ret)
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2022-07-27 15:17:53 -04:00
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return ret;
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2021-07-04 17:40:39 +02:00
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2025-05-24 06:17:16 +02:00
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machine_at_common_init_ex(model, 2);
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device_add(&amstrad_megapc_nvr_device);
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2024-01-30 15:45:09 +03:00
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device_add(&ide_pci_device);
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2021-07-04 17:40:39 +02:00
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pci_init(PCI_CONFIG_TYPE_2);
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pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
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/* Not: 00, 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F. */
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/* Yes: 01, 10, 11, 12, 13, 14. */
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2023-01-06 15:36:05 -05:00
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pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 3, 2, 4);
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pci_register_slot(0x04, PCI_CARD_NORMAL, 4, 4, 3, 3);
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pci_register_slot(0x05, PCI_CARD_NORMAL, 1, 4, 3, 2);
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pci_register_slot(0x06, PCI_CARD_NORMAL, 2, 1, 3, 4);
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2021-07-04 17:40:39 +02:00
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pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
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device_add(&i430lx_device);
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2025-07-27 15:23:43 +02:00
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device_add(&kbc_ps2_phoenix_device);
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2021-07-04 17:40:39 +02:00
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device_add(&sio_zb_device);
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2025-08-11 16:36:30 +02:00
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device_add_params(&fdc37c6xx_device, (void *) FDC37C665);
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2021-07-04 17:40:39 +02:00
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device_add(&intel_flash_bxt_ami_device);
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return ret;
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}
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int
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machine_at_opti560l_init(const machine_t *model)
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{
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int ret;
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ret = bios_load_linear_inverted("roms/machines/opti560l/560L_A06.ROM",
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2022-07-27 15:17:53 -04:00
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0x000e0000, 131072, 0);
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2021-07-04 17:40:39 +02:00
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if (bios_only || !ret)
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2022-07-27 15:17:53 -04:00
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return ret;
|
2021-07-04 17:40:39 +02:00
|
|
|
|
2025-05-24 06:17:16 +02:00
|
|
|
machine_at_common_init_ex(model, 2);
|
|
|
|
|
|
|
|
|
|
device_add(&amstrad_megapc_nvr_device);
|
|
|
|
|
device_add(&ide_pci_device);
|
2021-07-04 17:40:39 +02:00
|
|
|
|
|
|
|
|
pci_init(PCI_CONFIG_TYPE_2);
|
|
|
|
|
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
|
2023-01-06 15:36:05 -05:00
|
|
|
pci_register_slot(0x03, PCI_CARD_NORMAL, 4, 4, 3, 3);
|
|
|
|
|
pci_register_slot(0x07, PCI_CARD_NORMAL, 1, 4, 3, 2);
|
|
|
|
|
pci_register_slot(0x08, PCI_CARD_NORMAL, 2, 1, 3, 4);
|
2021-07-04 17:40:39 +02:00
|
|
|
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
|
|
|
|
|
device_add(&i430lx_device);
|
2025-07-27 15:23:43 +02:00
|
|
|
device_add(&kbc_ps2_phoenix_device);
|
2021-07-04 17:40:39 +02:00
|
|
|
device_add(&sio_zb_device);
|
2025-08-11 16:36:30 +02:00
|
|
|
device_add_params(&i82091aa_device, (void *) I82091AA_022);
|
2021-07-04 17:40:39 +02:00
|
|
|
device_add(&intel_flash_bxt_ami_device);
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2025-08-13 23:43:51 +02:00
|
|
|
void
|
|
|
|
|
machine_at_award_common_init(const machine_t *model)
|
|
|
|
|
{
|
|
|
|
|
machine_at_common_init(model);
|
|
|
|
|
|
|
|
|
|
pci_init(PCI_CONFIG_TYPE_2 | PCI_NO_IRQ_STEERING);
|
|
|
|
|
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
|
|
|
|
|
pci_register_slot(0x03, PCI_CARD_NORMAL, 1, 2, 3, 4); /* 03 = Slot 1 */
|
|
|
|
|
pci_register_slot(0x04, PCI_CARD_NORMAL, 2, 3, 4, 1); /* 04 = Slot 2 */
|
|
|
|
|
pci_register_slot(0x05, PCI_CARD_NORMAL, 3, 4, 1, 2); /* 05 = Slot 3 */
|
|
|
|
|
pci_register_slot(0x06, PCI_CARD_NORMAL, 4, 1, 2, 3); /* 06 = Slot 4 */
|
|
|
|
|
pci_register_slot(0x07, PCI_CARD_SCSI, 1, 2, 3, 4); /* 07 = SCSI */
|
|
|
|
|
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
|
|
|
|
|
|
|
|
|
|
if (fdc_current[0] == FDC_INTERNAL)
|
|
|
|
|
device_add(&fdc_at_device);
|
|
|
|
|
|
|
|
|
|
device_add(&kbc_at_ami_device);
|
|
|
|
|
device_add(&sio_zb_device);
|
|
|
|
|
device_add(&intel_flash_bxt_device);
|
|
|
|
|
}
|
|
|
|
|
|
2021-07-04 17:40:39 +02:00
|
|
|
int
|
2025-08-13 23:43:51 +02:00
|
|
|
machine_at_586is_init(const machine_t *model)
|
2021-07-04 17:40:39 +02:00
|
|
|
{
|
|
|
|
|
int ret;
|
|
|
|
|
|
2025-08-13 23:43:51 +02:00
|
|
|
ret = bios_load_linear("roms/machines/586is/IS.34",
|
|
|
|
|
0x000e0000, 131072, 0);
|
2021-07-04 17:40:39 +02:00
|
|
|
|
|
|
|
|
if (bios_only || !ret)
|
2022-07-27 15:17:53 -04:00
|
|
|
return ret;
|
2021-07-04 17:40:39 +02:00
|
|
|
|
2025-08-13 23:43:51 +02:00
|
|
|
machine_at_award_common_init(model);
|
2021-07-04 17:40:39 +02:00
|
|
|
|
|
|
|
|
device_add(&i430lx_device);
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int
|
|
|
|
|
machine_at_valuepointp60_init(const machine_t *model)
|
|
|
|
|
{
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
ret = bios_load_linear_combined("roms/machines/valuepointp60/1006AV0M.BIO",
|
2023-01-06 15:36:05 -05:00
|
|
|
"roms/machines/valuepointp60/1006AV0M.BI1",
|
|
|
|
|
0x1d000, 128);
|
2021-07-04 17:40:39 +02:00
|
|
|
|
|
|
|
|
if (bios_only || !ret)
|
2022-07-27 15:17:53 -04:00
|
|
|
return ret;
|
2021-07-04 17:40:39 +02:00
|
|
|
|
|
|
|
|
machine_at_common_init(model);
|
2025-05-07 19:49:03 +02:00
|
|
|
device_add(&ide_pci_device);
|
2021-07-04 17:40:39 +02:00
|
|
|
|
|
|
|
|
pci_init(PCI_CONFIG_TYPE_2 | PCI_NO_IRQ_STEERING);
|
|
|
|
|
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
|
2023-01-06 15:36:05 -05:00
|
|
|
pci_register_slot(0x01, PCI_CARD_IDE, 0, 0, 0, 0);
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
pci_register_slot(0x03, PCI_CARD_VIDEO, 3, 3, 3, 3);
|
2023-01-06 15:36:05 -05:00
|
|
|
pci_register_slot(0x06, PCI_CARD_NORMAL, 3, 2, 1, 4);
|
|
|
|
|
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 1, 3, 4);
|
|
|
|
|
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 3, 2, 4);
|
2021-07-04 17:40:39 +02:00
|
|
|
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
|
2025-07-27 15:23:43 +02:00
|
|
|
device_add(&kbc_ps2_ps1_pci_device);
|
2021-07-04 17:40:39 +02:00
|
|
|
device_add(&sio_device);
|
2025-08-11 16:36:30 +02:00
|
|
|
device_add_params(&fdc37c6xx_device, (void *) (FDC37C665 | FDC37C6XX_IDE_PRI));
|
2021-07-04 17:40:39 +02:00
|
|
|
device_add(&intel_flash_bxt_ami_device);
|
|
|
|
|
|
|
|
|
|
device_add(&i430lx_device);
|
|
|
|
|
|
Video changes:
1. The passthrough from VGA to 8514/A and/or 8514/A to VGA no longer relies on hackish places where to switch from/to, instead, relying on port 0x3c3 of VGA doing so (though the Mach8/32 still needs some places where to manually switch from/to, mainly the MCA one when configuring the EEPROM).
2. Implemented the MCA behalf of the Mach32 and its corresponding reset function.
3. Properly implemented (more or less) true color, including 24-bit BGR rendering
4. Other fixes such as color patterns and mono patterns being more correct than before in various operating systems and in 24-bit true color.
5. Implemented the onboard Mach32 video of the IBM PS/ValuePoint P60 machine.
6. Made the onboard internal video detect when it's 8514/A compatible or not (CGA/EGA/MDA/VGA/etc.). If the former is selected, then the video monitor flag is used instead (for QT).
7. The TGUI9400 and 9440, if on VLB, now detect the right amount of memory if on 2MB.
8. Initial implementation of the ATI 68875 ramdac used by the Mach32 and made the ATI 68860 8514/A aware when selected with the Mach32AX PCI.
9. Separated the 8514/A ramdac ports from the VGA ramdac ports, allowing seamless transition from/to 8514/A/VGA.
10. Fixed a hdisp problem in the ET4000/W32 cards, where it was doubling the horizontal display in 15bpp+ graphics mode.
11. Removed the 0x3da/0x3ba port hack that was on the Mach8/32 code, relying on the (S)VGA core instead.
12. Reworked and simplified the TGUI9440 pitch register based on logging due to no documentation at all.
2023-08-12 00:00:46 +02:00
|
|
|
if (gfxcard[0] == VID_INTERNAL)
|
|
|
|
|
device_add(&mach32_onboard_pci_device);
|
|
|
|
|
|
2021-07-04 17:40:39 +02:00
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2025-08-13 23:43:51 +02:00
|
|
|
void
|
|
|
|
|
machine_at_premiere_common_init(const machine_t *model, int pci_switch)
|
|
|
|
|
{
|
|
|
|
|
machine_at_common_init_ex(model, 2);
|
|
|
|
|
|
|
|
|
|
device_add(&amstrad_megapc_nvr_device);
|
|
|
|
|
device_add(&ide_pci_2ch_device);
|
|
|
|
|
|
|
|
|
|
pci_init(PCI_CONFIG_TYPE_2 | pci_switch);
|
|
|
|
|
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
|
|
|
|
|
pci_register_slot(0x01, PCI_CARD_IDE, 0, 0, 0, 0);
|
|
|
|
|
pci_register_slot(0x06, PCI_CARD_NORMAL, 3, 2, 1, 4);
|
|
|
|
|
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 1, 3, 4);
|
|
|
|
|
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 3, 2, 4);
|
|
|
|
|
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
|
|
|
|
|
device_add(&kbc_ps2_phoenix_device);
|
|
|
|
|
device_add(&sio_zb_device);
|
|
|
|
|
device_add(&ide_rz1000_pci_single_channel_device);
|
|
|
|
|
device_add_params(&fdc37c6xx_device, (void *) (FDC37C665 | FDC37C6XX_IDE_SEC));
|
|
|
|
|
device_add(&intel_flash_bxt_ami_device);
|
|
|
|
|
}
|
|
|
|
|
|
2021-07-04 17:40:39 +02:00
|
|
|
int
|
|
|
|
|
machine_at_revenge_init(const machine_t *model)
|
|
|
|
|
{
|
|
|
|
|
int ret;
|
|
|
|
|
|
2023-12-30 13:59:04 +01:00
|
|
|
ret = bios_load_linear_combined("roms/machines/revenge/1013af2_.bio",
|
|
|
|
|
"roms/machines/revenge/1013af2_.bi1",
|
2023-01-06 15:36:05 -05:00
|
|
|
0x1c000, 128);
|
2021-07-04 17:40:39 +02:00
|
|
|
|
|
|
|
|
if (bios_only || !ret)
|
2022-07-27 15:17:53 -04:00
|
|
|
return ret;
|
2021-07-04 17:40:39 +02:00
|
|
|
|
|
|
|
|
machine_at_premiere_common_init(model, 0);
|
|
|
|
|
|
|
|
|
|
device_add(&i430lx_device);
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int
|
2025-08-13 23:43:51 +02:00
|
|
|
machine_at_m5pi_init(const machine_t *model)
|
2021-07-04 17:40:39 +02:00
|
|
|
{
|
|
|
|
|
int ret;
|
|
|
|
|
|
2025-08-13 23:43:51 +02:00
|
|
|
ret = bios_load_linear_inverted("roms/machines/m5pi/M5PI10R.BIN",
|
2022-07-27 15:17:53 -04:00
|
|
|
0x000e0000, 131072, 0);
|
2021-07-04 17:40:39 +02:00
|
|
|
|
|
|
|
|
if (bios_only || !ret)
|
2022-07-27 15:17:53 -04:00
|
|
|
return ret;
|
2021-07-04 17:40:39 +02:00
|
|
|
|
2025-08-13 23:43:51 +02:00
|
|
|
machine_at_common_init(model);
|
2021-07-04 17:40:39 +02:00
|
|
|
|
2025-08-13 23:43:51 +02:00
|
|
|
pci_init(PCI_CONFIG_TYPE_2 | PCI_NO_IRQ_STEERING);
|
|
|
|
|
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
|
|
|
|
|
pci_register_slot(0x01, PCI_CARD_IDE, 0, 0, 0, 0);
|
|
|
|
|
pci_register_slot(0x0f, PCI_CARD_NORMAL, 1, 2, 3, 4);
|
|
|
|
|
pci_register_slot(0x0c, PCI_CARD_NORMAL, 2, 3, 4, 1);
|
|
|
|
|
pci_register_slot(0x0b, PCI_CARD_NORMAL, 3, 4, 1, 2);
|
|
|
|
|
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
|
|
|
|
|
device_add(&i430lx_device);
|
|
|
|
|
device_add(&sio_zb_device);
|
|
|
|
|
device_add(&kbc_ps2_phoenix_device);
|
|
|
|
|
device_add(&ide_w83769f_pci_single_channel_device);
|
|
|
|
|
device_add_params(&fdc37c6xx_device, (void *) (FDC37C665 | FDC37C6XX_IDE_SEC));
|
|
|
|
|
device_add(&intel_flash_bxt_ami_device);
|
2021-07-04 17:40:39 +02:00
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int
|
|
|
|
|
machine_at_pb520r_init(const machine_t *model)
|
|
|
|
|
{
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
ret = bios_load_linear_combined("roms/machines/pb520r/1009bc0r.bio",
|
2023-01-06 15:36:05 -05:00
|
|
|
"roms/machines/pb520r/1009bc0r.bi1",
|
|
|
|
|
0x1d000, 128);
|
2021-07-04 17:40:39 +02:00
|
|
|
|
|
|
|
|
if (bios_only || !ret)
|
2022-07-27 15:17:53 -04:00
|
|
|
return ret;
|
2021-07-04 17:40:39 +02:00
|
|
|
|
|
|
|
|
machine_at_common_init(model);
|
|
|
|
|
|
|
|
|
|
pci_init(PCI_CONFIG_TYPE_2);
|
|
|
|
|
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
|
2023-01-06 15:36:05 -05:00
|
|
|
pci_register_slot(0x01, PCI_CARD_IDE, 0, 0, 0, 0);
|
|
|
|
|
pci_register_slot(0x03, PCI_CARD_VIDEO, 3, 3, 3, 3);
|
|
|
|
|
pci_register_slot(0x06, PCI_CARD_NORMAL, 3, 2, 1, 4);
|
|
|
|
|
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 1, 3, 4);
|
|
|
|
|
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 3, 2, 4);
|
2021-07-04 17:40:39 +02:00
|
|
|
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
|
|
|
|
|
device_add(&i430lx_device);
|
|
|
|
|
device_add(&ide_cmd640_pci_single_channel_device);
|
|
|
|
|
|
2023-02-06 04:12:46 -05:00
|
|
|
if (gfxcard[0] == VID_INTERNAL)
|
2022-07-27 15:17:53 -04:00
|
|
|
device_add(&gd5434_onboard_pci_device);
|
2021-07-04 17:40:39 +02:00
|
|
|
|
2025-07-27 15:23:43 +02:00
|
|
|
device_add(&kbc_ps2_pci_device);
|
2021-07-04 17:40:39 +02:00
|
|
|
device_add(&sio_zb_device);
|
2025-08-11 16:36:30 +02:00
|
|
|
device_add_params(&i82091aa_device, (void *) (I82091AA_022 | I82091AA_IDE_PRI));
|
2021-07-04 17:40:39 +02:00
|
|
|
device_add(&intel_flash_bxt_ami_device);
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2025-08-13 23:43:51 +02:00
|
|
|
/* OPTi 597 */
|
2025-01-01 15:51:12 -07:00
|
|
|
int
|
2025-08-13 23:43:51 +02:00
|
|
|
machine_at_excalibur_init(const machine_t *model)
|
2025-01-01 15:51:12 -07:00
|
|
|
{
|
|
|
|
|
int ret;
|
|
|
|
|
|
2025-08-13 23:43:51 +02:00
|
|
|
ret = bios_load_linear_inverted("roms/machines/excalibur/S75P.ROM",
|
|
|
|
|
0x000e0000, 131072, 0);
|
2025-01-01 15:51:12 -07:00
|
|
|
|
|
|
|
|
if (bios_only || !ret)
|
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
|
|
machine_at_common_init(model);
|
|
|
|
|
|
2025-08-13 23:43:51 +02:00
|
|
|
device_add(&opti5x7_device);
|
|
|
|
|
device_add(&ide_opti611_vlb_device);
|
|
|
|
|
device_add_params(&fdc37c6xx_device, (void *) FDC37C661);
|
|
|
|
|
device_add(&kbc_ps2_intel_ami_pci_device);
|
2025-01-01 15:51:12 -07:00
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2025-01-25 00:22:59 +03:00
|
|
|
int
|
|
|
|
|
machine_at_globalyst330_p5_init(const machine_t *model)
|
|
|
|
|
{
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
ret = bios_load_linear("roms/machines/globalyst330_p5/MiTAC_PB5500C_v1.02_120794_ATT.BIN",
|
|
|
|
|
0x000e0000, 131072, 0);
|
|
|
|
|
|
|
|
|
|
if (bios_only || !ret)
|
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
|
|
machine_at_common_init(model);
|
|
|
|
|
|
|
|
|
|
pci_init(PCI_CONFIG_TYPE_1);
|
|
|
|
|
pci_register_slot(0x10, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
|
|
|
|
|
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
|
|
|
|
|
pci_register_slot(0x12, PCI_CARD_NORMAL, 5, 6, 7, 8);
|
|
|
|
|
pci_register_slot(0x13, PCI_CARD_NORMAL, 9, 10, 11, 12);
|
|
|
|
|
pci_register_slot(0x14, PCI_CARD_NORMAL, 13, 14, 15, 16);
|
|
|
|
|
|
|
|
|
|
device_add(&opti5x7_pci_device);
|
|
|
|
|
device_add(&opti822_device);
|
|
|
|
|
device_add(&sst_flash_29ee010_device);
|
2025-07-27 15:23:43 +02:00
|
|
|
device_add(&kbc_at_ami_device);
|
2025-01-25 00:22:59 +03:00
|
|
|
|
|
|
|
|
if (fdc_current[0] == FDC_INTERNAL)
|
|
|
|
|
device_add(&fdc_at_device);
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2021-07-04 17:40:39 +02:00
|
|
|
int
|
|
|
|
|
machine_at_p5vl_init(const machine_t *model)
|
|
|
|
|
{
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
ret = bios_load_linear("roms/machines/p5vl/SM507.ROM",
|
2022-07-27 15:17:53 -04:00
|
|
|
0x000e0000, 131072, 0);
|
2021-07-04 17:40:39 +02:00
|
|
|
|
|
|
|
|
if (bios_only || !ret)
|
2022-07-27 15:17:53 -04:00
|
|
|
return ret;
|
2021-07-04 17:40:39 +02:00
|
|
|
|
|
|
|
|
machine_at_common_init(model);
|
2022-11-02 04:03:55 +01:00
|
|
|
|
2022-11-02 05:19:28 +01:00
|
|
|
pci_init(PCI_CONFIG_TYPE_1);
|
2021-07-04 17:40:39 +02:00
|
|
|
pci_register_slot(0x10, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
|
2023-01-06 15:36:05 -05:00
|
|
|
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
|
|
|
|
|
pci_register_slot(0x12, PCI_CARD_NORMAL, 5, 6, 7, 8);
|
|
|
|
|
pci_register_slot(0x13, PCI_CARD_NORMAL, 9, 10, 11, 12);
|
|
|
|
|
pci_register_slot(0x14, PCI_CARD_NORMAL, 13, 14, 15, 16);
|
2022-11-02 04:03:55 +01:00
|
|
|
|
2022-10-31 05:44:32 +01:00
|
|
|
device_add(&opti5x7_pci_device);
|
2021-07-04 17:40:39 +02:00
|
|
|
device_add(&opti822_device);
|
|
|
|
|
device_add(&sst_flash_29ee010_device);
|
2025-07-27 15:23:43 +02:00
|
|
|
device_add(&kbc_at_ami_device);
|
2021-07-04 17:40:39 +02:00
|
|
|
|
2024-07-20 01:14:35 -04:00
|
|
|
if (fdc_current[0] == FDC_INTERNAL)
|
2022-07-27 15:17:53 -04:00
|
|
|
device_add(&fdc_at_device);
|
2021-07-04 17:40:39 +02:00
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2025-08-13 23:43:51 +02:00
|
|
|
/* SiS 501 */
|
2021-08-21 18:19:10 +02:00
|
|
|
int
|
2021-11-14 14:28:22 -03:00
|
|
|
machine_at_excaliburpci2_init(const machine_t *model)
|
2021-08-21 18:19:10 +02:00
|
|
|
{
|
|
|
|
|
int ret;
|
|
|
|
|
|
2021-11-14 14:28:22 -03:00
|
|
|
ret = bios_load_linear_inverted("roms/machines/excaliburpci2/S722P.ROM",
|
2022-07-27 15:17:53 -04:00
|
|
|
0x000e0000, 131072, 0);
|
2021-08-21 18:19:10 +02:00
|
|
|
|
|
|
|
|
if (bios_only || !ret)
|
2022-07-27 15:17:53 -04:00
|
|
|
return ret;
|
2021-08-21 18:19:10 +02:00
|
|
|
|
2021-11-30 00:25:03 +01:00
|
|
|
machine_at_common_init_ex(model, 2);
|
|
|
|
|
device_add(&ami_1994_nvr_device);
|
2021-08-21 18:19:10 +02:00
|
|
|
|
2024-04-04 03:10:29 +02:00
|
|
|
pci_init(PCI_CONFIG_TYPE_1 | FLAG_TRC_CONTROLS_CPURST);
|
2021-08-21 18:19:10 +02:00
|
|
|
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
|
|
|
|
|
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
|
2023-01-06 15:36:05 -05:00
|
|
|
pci_register_slot(0x08, PCI_CARD_IDE, 0, 0, 0, 0);
|
|
|
|
|
pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4);
|
|
|
|
|
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
|
|
|
|
|
pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2);
|
|
|
|
|
pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 1, 2, 3);
|
2025-08-11 16:36:30 +02:00
|
|
|
device_add_params(&fdc37c6xx_device, (void *) FDC37C665);
|
2025-07-27 15:23:43 +02:00
|
|
|
device_add(&kbc_ps2_ami_pci_device);
|
2021-08-21 18:19:10 +02:00
|
|
|
device_add(&ide_cmd640_pci_legacy_only_device);
|
|
|
|
|
|
|
|
|
|
device_add(&sis_85c50x_device);
|
|
|
|
|
device_add(&intel_flash_bxt_ami_device);
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2025-08-13 23:43:51 +02:00
|
|
|
void
|
|
|
|
|
machine_at_sp4_common_init(const machine_t *model)
|
|
|
|
|
{
|
|
|
|
|
machine_at_common_init(model);
|
|
|
|
|
|
|
|
|
|
pci_init(PCI_CONFIG_TYPE_1 | FLAG_TRC_CONTROLS_CPURST);
|
|
|
|
|
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
|
|
|
|
|
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
|
|
|
|
|
/* Excluded: 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14 */
|
|
|
|
|
pci_register_slot(0x0D, PCI_CARD_IDE, 1, 2, 3, 4);
|
|
|
|
|
/* Excluded: 02, 03*, 04*, 05*, 06*, 07*, 08* */
|
|
|
|
|
/* Slots: 09 (04), 0A (03), 0B (02), 0C (07) */
|
|
|
|
|
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
|
|
|
|
|
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
|
|
|
|
|
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
|
|
|
|
|
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
|
|
|
|
|
device_add(&sis_85c50x_device);
|
|
|
|
|
device_add(&ide_cmd640_pci_device);
|
|
|
|
|
device_add(&kbc_ps2_ami_pci_device);
|
|
|
|
|
device_add_params(&fdc37c6xx_device, (void *) FDC37C665);
|
|
|
|
|
device_add(&intel_flash_bxt_device);
|
|
|
|
|
}
|
|
|
|
|
|
2021-07-04 17:40:39 +02:00
|
|
|
int
|
|
|
|
|
machine_at_p5sp4_init(const machine_t *model)
|
|
|
|
|
{
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
ret = bios_load_linear("roms/machines/p5sp4/0106.001",
|
2022-07-27 15:17:53 -04:00
|
|
|
0x000e0000, 131072, 0);
|
2021-07-04 17:40:39 +02:00
|
|
|
|
|
|
|
|
if (bios_only || !ret)
|
2022-07-27 15:17:53 -04:00
|
|
|
return ret;
|
2021-07-04 17:40:39 +02:00
|
|
|
|
|
|
|
|
machine_at_sp4_common_init(model);
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
2025-08-15 20:59:07 +02:00
|
|
|
|
|
|
|
|
int
|
|
|
|
|
machine_at_ecs50x_init(const machine_t *model)
|
|
|
|
|
{
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
ret = bios_load_linear("roms/machines/ecs50x/ECSSi5piaio.BIN",
|
|
|
|
|
0x000e0000, 131072, 0);
|
|
|
|
|
|
|
|
|
|
if (bios_only || !ret)
|
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
|
|
machine_at_common_init(model);
|
|
|
|
|
|
|
|
|
|
pci_init(PCI_CONFIG_TYPE_1 | FLAG_TRC_CONTROLS_CPURST);
|
|
|
|
|
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
|
|
|
|
|
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
|
|
|
|
|
pci_register_slot(0x02, PCI_CARD_IDE, 1, 2, 3, 4);
|
|
|
|
|
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
|
|
|
|
|
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 4, 1);
|
|
|
|
|
pci_register_slot(0x0D, PCI_CARD_NORMAL, 3, 4, 1, 2);
|
|
|
|
|
pci_register_slot(0x0F, PCI_CARD_NORMAL, 4, 1, 2, 3);
|
|
|
|
|
device_add(&sis_85c50x_device);
|
|
|
|
|
device_add_params(&ide_cmd640_pci_device, (void *) 0x100000);
|
|
|
|
|
device_add(&kbc_ps2_ami_pci_device);
|
|
|
|
|
device_add_params(&fdc37c6xx_device, (void *) FDC37C665);
|
|
|
|
|
device_add(&intel_flash_bxt_device);
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|