2017-05-30 03:38:38 +02:00
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/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Emulation of the Winbond W83877F Super I/O Chip.
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*
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2017-08-24 01:14:39 -04:00
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* Winbond W83877F Super I/O Chip
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* Used by the Award 430HX
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*
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2018-11-08 19:21:55 +01:00
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* Version: @(#)sio_w83877f.c 1.0.14 2018/11/05
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2017-05-30 03:38:38 +02:00
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*
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* Author: Miran Grca, <mgrca8@gmail.com>
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2018-01-17 18:43:36 +01:00
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* Copyright 2016-2018 Miran Grca.
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2017-05-30 03:38:38 +02:00
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*/
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2017-09-25 04:31:20 -04:00
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#include <stdio.h>
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#include <stdint.h>
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2018-11-08 19:21:55 +01:00
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#include <stdlib.h>
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2017-09-25 04:31:20 -04:00
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#include <string.h>
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#include <wchar.h>
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2017-10-17 01:59:09 -04:00
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#include "86box.h"
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2018-01-17 18:43:36 +01:00
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#include "device.h"
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2016-06-26 00:34:39 +02:00
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#include "io.h"
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2017-11-05 01:57:04 -05:00
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#include "pci.h"
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2017-09-25 04:31:20 -04:00
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#include "mem.h"
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#include "rom.h"
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2016-06-26 00:34:39 +02:00
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#include "lpt.h"
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#include "serial.h"
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2017-09-04 01:52:29 -04:00
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#include "floppy/fdd.h"
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2018-01-17 18:43:36 +01:00
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#include "floppy/fdc.h"
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2017-09-04 01:52:29 -04:00
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#include "sio.h"
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2016-06-26 00:34:39 +02:00
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2017-08-24 01:14:39 -04:00
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2018-11-08 19:21:55 +01:00
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#define FDDA_TYPE (dev->regs[7] & 3)
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#define FDDB_TYPE ((dev->regs[7] >> 2) & 3)
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#define FDDC_TYPE ((dev->regs[7] >> 4) & 3)
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#define FDDD_TYPE ((dev->regs[7] >> 6) & 3)
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#define FD_BOOT (dev->regs[8] & 3)
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#define SWWP ((dev->regs[8] >> 4) & 1)
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#define DISFDDWR ((dev->regs[8] >> 5) & 1)
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#define EN3MODE ((dev->regs[9] >> 5) & 1)
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#define DRV2EN_NEG (dev->regs[0xB] & 1) /* 0 = drive 2 installed */
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#define INVERTZ ((dev->regs[0xB] >> 1) & 1) /* 0 = invert DENSEL polarity */
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#define IDENT ((dev->regs[0xB] >> 3) & 1)
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#define HEFERE ((dev->regs[0xC] >> 5) & 1)
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#define HEFRAS (dev->regs[0x16] & 1)
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typedef struct {
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uint8_t tries, reg16_init,
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regs[42];
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int locked, rw_locked,
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cur_reg,
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base_address, key,
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key_times;
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fdc_t *fdc;
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serial_t *uart[2];
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} w83877f_t;
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static void w83877f_write(uint16_t port, uint8_t val, void *priv);
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static uint8_t w83877f_read(uint16_t port, void *priv);
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static void
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w83877f_remap(w83877f_t *dev)
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2016-06-26 00:34:39 +02:00
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{
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2018-11-08 19:21:55 +01:00
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uint8_t hefras = HEFRAS;
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io_removehandler(0x250, 0x0002,
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w83877f_read, NULL, NULL, w83877f_write, NULL, NULL, dev);
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io_removehandler(0x3f0, 0x0002,
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w83877f_read, NULL, NULL, w83877f_write, NULL, NULL, dev);
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dev->base_address = (hefras ? 0x3f0 : 0x250);
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io_sethandler(dev->base_address, 0x0002,
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w83877f_read, NULL, NULL, w83877f_write, NULL, NULL, dev);
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dev->key_times = hefras + 1;
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dev->key = (hefras ? 0x86 : 0x88) | HEFERE;
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2016-06-26 00:34:39 +02:00
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}
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2017-08-24 01:14:39 -04:00
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2018-11-08 19:21:55 +01:00
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static uint8_t
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get_lpt_length(w83877f_t *dev)
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2016-06-26 00:34:39 +02:00
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{
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2018-11-08 19:21:55 +01:00
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uint8_t length = 4;
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2016-06-26 00:34:39 +02:00
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2018-11-08 19:21:55 +01:00
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if (dev->regs[9] & 0x80) {
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if (dev->regs[0] & 0x04)
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length = 8; /* EPP mode. */
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if (dev->regs[0] & 0x08)
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length |= 0x80; /* ECP mode. */
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}
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return length;
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2016-06-26 00:34:39 +02:00
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}
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2017-08-24 01:14:39 -04:00
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2018-11-08 19:21:55 +01:00
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static uint16_t
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make_port(w83877f_t *dev, uint8_t reg)
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2016-06-26 00:34:39 +02:00
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{
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2018-11-08 19:21:55 +01:00
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uint16_t p = 0;
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uint8_t l;
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switch (reg) {
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case 0x20:
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p = ((uint16_t) (dev->regs[reg] & 0xfc)) << 2;
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p &= 0xFF0;
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if ((p < 0x100) || (p > 0x3F0)) p = 0x3F0;
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break;
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case 0x23:
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l = get_lpt_length(dev);
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p = ((uint16_t) (dev->regs[reg] & 0xff)) << 2;
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/* 8 ports in EPP mode, 4 in non-EPP mode. */
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if ((l & 0x0f) == 8)
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p &= 0x3F8;
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else
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p &= 0x3FC;
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if ((p < 0x100) || (p > 0x3FF)) p = 0x378;
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/* In ECP mode, A10 is active. */
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if (l & 0x80)
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p |= 0x400;
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break;
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case 0x24:
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p = ((uint16_t) (dev->regs[reg] & 0xfe)) << 2;
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p &= 0xFF8;
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if ((p < 0x100) || (p > 0x3F8)) p = 0x3F8;
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break;
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case 0x25:
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p = ((uint16_t) (dev->regs[reg] & 0xfe)) << 2;
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p &= 0xFF8;
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if ((p < 0x100) || (p > 0x3F8)) p = 0x2F8;
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break;
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}
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return p;
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2016-06-26 00:34:39 +02:00
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}
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2017-08-24 01:14:39 -04:00
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2018-11-08 19:21:55 +01:00
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static void
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w83877f_serial_handler(w83877f_t *dev, int uart)
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2017-06-16 03:18:59 +02:00
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{
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2018-11-08 19:21:55 +01:00
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int reg_mask = uart ? 0x10 : 0x20;
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int reg_id = uart ? 0x24 : 0x25;
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int irq_mask = uart ? 0x0f : 0xf0;
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int irq_shift = uart ? 4 : 0;
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if ((dev->regs[4] & reg_mask) || !(dev->regs[reg_id] & 0xc0))
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serial_remove(dev->uart[uart]);
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else
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serial_setup(dev->uart[uart], make_port(dev, reg_id), (dev->regs[0x28] & irq_mask) >> irq_shift);
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2017-06-16 03:18:59 +02:00
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}
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2017-08-24 01:14:39 -04:00
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2018-11-08 19:21:55 +01:00
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static void
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w83877f_write(uint16_t port, uint8_t val, void *priv)
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2016-06-26 00:34:39 +02:00
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{
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2018-11-08 19:21:55 +01:00
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w83877f_t *dev = (w83877f_t *) priv;
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uint8_t index = (port & 1) ? 0 : 1;
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uint8_t valxor = 0;
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uint8_t max = 0x2A;
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if (index) {
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if ((val == dev->key) && !dev->locked) {
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if (dev->key_times == 2) {
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if (dev->tries) {
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dev->locked = 1;
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dev->tries = 0;
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} else
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dev->tries++;
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} else {
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dev->locked = 1;
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dev->tries = 0;
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2016-06-26 00:34:39 +02:00
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}
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2018-11-08 19:21:55 +01:00
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} else {
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if (dev->locked) {
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if (val < max)
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dev->cur_reg = val;
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if (val == 0xaa)
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dev->locked = 0;
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} else {
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if (dev->tries)
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dev->tries = 0;
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2016-06-26 00:34:39 +02:00
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}
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}
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return;
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2018-11-08 19:21:55 +01:00
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} else {
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if (dev->locked) {
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if (dev->rw_locked)
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return;
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if ((dev->cur_reg >= 0x26) && (dev->cur_reg <= 0x27))
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return;
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if (dev->cur_reg == 0x29)
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return;
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if (dev->cur_reg == 6)
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val &= 0xF3;
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valxor = val ^ dev->regs[dev->cur_reg];
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dev->regs[dev->cur_reg] = val;
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} else
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return;
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}
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switch (dev->cur_reg) {
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case 0:
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if (valxor & 0xc0) {
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lpt1_remove();
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if (!(dev->regs[4] & 0x80))
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lpt1_init(make_port(dev, 0x23));
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}
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break;
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case 1:
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if (valxor & 0x80)
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fdc_set_swap(dev->fdc, (dev->regs[1] & 0x80) ? 1 : 0);
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break;
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case 4:
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if (valxor & 0x10)
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w83877f_serial_handler(dev, 1);
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if (valxor & 0x20)
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w83877f_serial_handler(dev, 0);
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if (valxor & 0x80) {
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lpt1_remove();
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if (!(dev->regs[4] & 0x80))
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lpt1_init(make_port(dev, 0x23));
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}
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break;
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case 6:
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if (valxor & 0x08) {
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fdc_remove(dev->fdc);
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if (!(dev->regs[6] & 0x08))
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fdc_set_base(dev->fdc, 0x03f0);
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}
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break;
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case 7:
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if (valxor & 0x03)
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fdc_update_rwc(dev->fdc, 0, FDDA_TYPE);
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if (valxor & 0x0c)
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fdc_update_rwc(dev->fdc, 1, FDDB_TYPE);
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if (valxor & 0x30)
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fdc_update_rwc(dev->fdc, 2, FDDC_TYPE);
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if (valxor & 0xc0)
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fdc_update_rwc(dev->fdc, 3, FDDD_TYPE);
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break;
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case 8:
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if (valxor & 0x03)
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fdc_update_boot_drive(dev->fdc, FD_BOOT);
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if (valxor & 0x10)
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fdc_set_swwp(dev->fdc, SWWP ? 1 : 0);
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if (valxor & 0x20)
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fdc_set_diswr(dev->fdc, DISFDDWR ? 1 : 0);
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break;
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case 9:
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if (valxor & 0x20)
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fdc_update_enh_mode(dev->fdc, EN3MODE ? 1 : 0);
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if (valxor & 0x40)
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dev->rw_locked = (val & 0x40) ? 1 : 0;
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if (valxor & 0x80) {
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lpt1_remove();
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if (!(dev->regs[4] & 0x80))
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lpt1_init(make_port(dev, 0x23));
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}
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break;
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case 0xB:
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if (valxor & 1)
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fdc_update_drv2en(dev->fdc, DRV2EN_NEG ? 0 : 1);
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if (valxor & 2)
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fdc_update_densel_polarity(dev->fdc, INVERTZ ? 1 : 0);
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break;
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case 0xC:
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if (valxor & 0x20)
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w83877f_remap(dev);
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break;
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case 0x16:
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if (valxor & 1)
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w83877f_remap(dev);
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break;
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case 0x20:
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if (valxor) {
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fdc_remove(dev->fdc);
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if (!(dev->regs[4] & 0x80))
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fdc_set_base(dev->fdc, make_port(dev, 0x20));
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}
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break;
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case 0x23:
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if (valxor) {
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lpt1_remove();
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if (!(dev->regs[4] & 0x80))
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lpt1_init(make_port(dev, 0x23));
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case 0x24:
|
|
|
|
|
if (valxor & 0xfe)
|
|
|
|
|
w83877f_serial_handler(dev, 0);
|
|
|
|
|
break;
|
|
|
|
|
case 0x25:
|
|
|
|
|
if (valxor & 0xfe)
|
|
|
|
|
w83877f_serial_handler(dev, 1);
|
|
|
|
|
break;
|
|
|
|
|
case 0x28:
|
|
|
|
|
if (valxor & 0xf) {
|
|
|
|
|
if ((dev->regs[0x28] & 0x0f) == 0)
|
|
|
|
|
dev->regs[0x28] |= 0x03;
|
|
|
|
|
if (!(dev->regs[2] & 0x10))
|
|
|
|
|
serial_setup(dev->uart[1], make_port(dev, 0x25), dev->regs[0x28] & 0x0f);
|
|
|
|
|
}
|
|
|
|
|
if (valxor & 0xf0) {
|
|
|
|
|
if ((dev->regs[0x28] & 0xf0) == 0)
|
|
|
|
|
dev->regs[0x28] |= 0x40;
|
|
|
|
|
if (!(dev->regs[4] & 0x20))
|
|
|
|
|
serial_setup(dev->uart[0], make_port(dev, 0x24), (dev->regs[0x28] & 0xf0) >> 4);
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2017-08-24 01:14:39 -04:00
|
|
|
|
2018-11-08 19:21:55 +01:00
|
|
|
static uint8_t
|
|
|
|
|
w83877f_read(uint16_t port, void *priv)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2018-11-08 19:21:55 +01:00
|
|
|
w83877f_t *dev = (w83877f_t *) priv;
|
|
|
|
|
uint8_t ret = 0xff;
|
|
|
|
|
uint8_t index = (port & 1) ? 0 : 1;
|
2016-06-26 00:34:39 +02:00
|
|
|
|
2018-11-08 19:21:55 +01:00
|
|
|
if (dev->locked) {
|
2016-06-26 00:34:39 +02:00
|
|
|
if (index)
|
2018-11-08 19:21:55 +01:00
|
|
|
ret = dev->cur_reg;
|
|
|
|
|
else {
|
|
|
|
|
if (dev->cur_reg == 7)
|
|
|
|
|
ret = (fdc_get_rwc(dev->fdc, 0) | (fdc_get_rwc(dev->fdc, 1) << 2));
|
|
|
|
|
else if ((dev->cur_reg >= 0x18) || !dev->rw_locked)
|
|
|
|
|
ret = dev->regs[dev->cur_reg];
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
2018-11-08 19:21:55 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
w83877f_reset(w83877f_t *dev)
|
|
|
|
|
{
|
|
|
|
|
lpt2_remove();
|
|
|
|
|
|
|
|
|
|
lpt1_remove();
|
|
|
|
|
lpt1_init(0x378);
|
|
|
|
|
|
|
|
|
|
fdc_reset(dev->fdc);
|
|
|
|
|
|
|
|
|
|
memset(dev->regs, 0, 0x2A);
|
|
|
|
|
dev->regs[0x03] = 0x30;
|
|
|
|
|
dev->regs[0x07] = 0xF5;
|
|
|
|
|
dev->regs[0x09] = 0x0A;
|
|
|
|
|
dev->regs[0x0a] = 0x1F;
|
|
|
|
|
dev->regs[0x0c] = 0x28;
|
|
|
|
|
dev->regs[0x0d] = 0xA3;
|
|
|
|
|
dev->regs[0x16] = dev->reg16_init;
|
|
|
|
|
dev->regs[0x1e] = 0x81;
|
|
|
|
|
dev->regs[0x20] = (0x3f0 >> 2) & 0xfc;
|
|
|
|
|
dev->regs[0x21] = (0x1f0 >> 2) & 0xfc;
|
|
|
|
|
dev->regs[0x22] = ((0x3f6 >> 2) & 0xfc) | 1;
|
|
|
|
|
dev->regs[0x23] = (0x378 >> 2);
|
|
|
|
|
dev->regs[0x24] = (0x3f8 >> 2) & 0xfe;
|
|
|
|
|
dev->regs[0x25] = (0x2f8 >> 2) & 0xfe;
|
|
|
|
|
dev->regs[0x26] = (2 << 4) | 4;
|
|
|
|
|
dev->regs[0x27] = (6 << 4) | 7;
|
|
|
|
|
dev->regs[0x28] = (4 << 4) | 3;
|
|
|
|
|
dev->regs[0x29] = 0x62;
|
|
|
|
|
|
|
|
|
|
serial_setup(dev->uart[0], SERIAL1_ADDR, SERIAL1_IRQ);
|
|
|
|
|
serial_setup(dev->uart[1], SERIAL2_ADDR, SERIAL2_IRQ);
|
|
|
|
|
|
|
|
|
|
dev->base_address = 0x3f0;
|
|
|
|
|
dev->key = 0x89;
|
|
|
|
|
dev->key_times = 1;
|
|
|
|
|
|
|
|
|
|
w83877f_remap(dev);
|
|
|
|
|
|
|
|
|
|
dev->locked = 0;
|
|
|
|
|
dev->rw_locked = 0;
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2017-08-24 01:14:39 -04:00
|
|
|
|
2018-11-08 19:21:55 +01:00
|
|
|
static void
|
|
|
|
|
w83877f_close(void *priv)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2018-11-08 19:21:55 +01:00
|
|
|
w83877f_t *dev = (w83877f_t *) priv;
|
|
|
|
|
|
|
|
|
|
free(dev);
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
2017-01-31 20:39:36 +01:00
|
|
|
|
2017-08-24 01:14:39 -04:00
|
|
|
|
2018-11-08 19:21:55 +01:00
|
|
|
static void *
|
|
|
|
|
w83877f_init(const device_t *info)
|
2017-01-31 20:39:36 +01:00
|
|
|
{
|
2018-11-08 19:21:55 +01:00
|
|
|
w83877f_t *dev = (w83877f_t *) malloc(sizeof(w83877f_t));
|
|
|
|
|
memset(dev, 0, sizeof(w83877f_t));
|
|
|
|
|
|
|
|
|
|
dev->fdc = device_add(&fdc_at_winbond_device);
|
|
|
|
|
|
|
|
|
|
dev->uart[0] = device_add_inst(&ns16550_device, 1);
|
|
|
|
|
dev->uart[1] = device_add_inst(&ns16550_device, 2);
|
2018-01-17 18:43:36 +01:00
|
|
|
|
2018-11-08 19:21:55 +01:00
|
|
|
dev->reg16_init = info->local;
|
2017-01-31 20:39:36 +01:00
|
|
|
|
2018-11-08 19:21:55 +01:00
|
|
|
w83877f_reset(dev);
|
|
|
|
|
|
|
|
|
|
return dev;
|
2017-01-31 20:39:36 +01:00
|
|
|
}
|
2018-11-08 19:21:55 +01:00
|
|
|
|
|
|
|
|
|
|
|
|
|
const device_t w83877f_device = {
|
|
|
|
|
"Winbond W83877F Super I/O",
|
|
|
|
|
0,
|
|
|
|
|
5,
|
|
|
|
|
w83877f_init, w83877f_close, NULL,
|
|
|
|
|
NULL, NULL, NULL,
|
|
|
|
|
NULL
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
const device_t w83877f_president_device = {
|
|
|
|
|
"Winbond W83877F Super I/O (President)",
|
|
|
|
|
0,
|
|
|
|
|
4,
|
|
|
|
|
w83877f_init, w83877f_close, NULL,
|
|
|
|
|
NULL, NULL, NULL,
|
|
|
|
|
NULL
|
|
|
|
|
};
|