2017-06-03 00:45:12 +02:00
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/*
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2022-11-13 16:37:58 -05:00
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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2017-06-03 00:45:12 +02:00
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*
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2022-11-13 16:37:58 -05:00
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* This file is part of the 86Box distribution.
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2017-06-03 00:45:12 +02:00
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*
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2022-11-13 16:37:58 -05:00
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* Common 386 CPU code.
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2017-06-03 00:45:12 +02:00
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*
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2020-03-25 00:46:02 +02:00
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*
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2017-06-03 00:45:12 +02:00
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*
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2023-01-06 15:36:29 -05:00
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* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
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2022-11-13 16:37:58 -05:00
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* Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2008-2019 Sarah Walker.
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* Copyright 2016-2019 Miran Grca.
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2017-06-03 00:45:12 +02:00
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*/
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2020-02-29 19:12:23 +01:00
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#ifndef _386_COMMON_H_
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#define _386_COMMON_H_
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2020-04-03 10:48:56 -05:00
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#include <stddef.h>
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2023-06-25 22:20:11 +02:00
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#include <inttypes.h>
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2020-04-03 10:48:56 -05:00
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2023-08-08 19:39:52 +02:00
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#ifdef OPS_286_386
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#define readmemb_n(s,a,b) readmembl_no_mmut_2386((s)+(a),b)
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#define readmemw_n(s,a,b) readmemwl_no_mmut_2386((s)+(a),b)
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#define readmeml_n(s,a,b) readmemll_no_mmut_2386((s)+(a),b)
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#define readmemb(s,a) readmembl_2386((s)+(a))
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#define readmemw(s,a) readmemwl_2386((s)+(a))
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#define readmeml(s,a) readmemll_2386((s)+(a))
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#define readmemq(s,a) readmemql_2386((s)+(a))
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#define writememb_n(s,a,b,v) writemembl_no_mmut_2386((s)+(a),b,v)
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#define writememw_n(s,a,b,v) writememwl_no_mmut_2386((s)+(a),b,v)
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#define writememl_n(s,a,b,v) writememll_no_mmut_2386((s)+(a),b,v)
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#define writememb(s,a,v) writemembl_2386((s)+(a),v)
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#define writememw(s,a,v) writememwl_2386((s)+(a),v)
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#define writememl(s,a,v) writememll_2386((s)+(a),v)
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#define writememq(s,a,v) writememql_2386((s)+(a),v)
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#define do_mmut_rb(s,a,b) do_mmutranslate_2386((s)+(a), b, 1, 0)
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#define do_mmut_rw(s,a,b) do_mmutranslate_2386((s)+(a), b, 2, 0)
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#define do_mmut_rl(s,a,b) do_mmutranslate_2386((s)+(a), b, 4, 0)
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#define do_mmut_rb2(s,a,b) do_mmutranslate_2386((s)+(a), b, 1, 0)
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#define do_mmut_rw2(s,a,b) do_mmutranslate_2386((s)+(a), b, 2, 0)
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#define do_mmut_rl2(s,a,b) do_mmutranslate_2386((s)+(a), b, 4, 0)
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#define do_mmut_wb(s,a,b) do_mmutranslate_2386((s)+(a), b, 1, 1)
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#define do_mmut_ww(s,a,b) do_mmutranslate_2386((s)+(a), b, 2, 1)
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#define do_mmut_wl(s,a,b) do_mmutranslate_2386((s)+(a), b, 4, 1)
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#else
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2022-11-19 10:40:32 -05:00
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#define readmemb_n(s, a, b) ((readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF) ? readmembl_no_mmut((s) + (a), b) : *(uint8_t *) (readlookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))))
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#define readmemw_n(s, a, b) ((readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 1)) ? readmemwl_no_mmut((s) + (a), b) : *(uint16_t *) (readlookup2[(uint32_t) ((s) + (a)) >> 12] + (uint32_t) ((s) + (a))))
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#define readmeml_n(s, a, b) ((readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 3)) ? readmemll_no_mmut((s) + (a), b) : *(uint32_t *) (readlookup2[(uint32_t) ((s) + (a)) >> 12] + (uint32_t) ((s) + (a))))
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#define readmemb(s, a) ((readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF) ? readmembl((s) + (a)) : *(uint8_t *) (readlookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))))
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#define readmemw(s, a) ((readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 1)) ? readmemwl((s) + (a)) : *(uint16_t *) (readlookup2[(uint32_t) ((s) + (a)) >> 12] + (uint32_t) ((s) + (a))))
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#define readmeml(s, a) ((readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 3)) ? readmemll((s) + (a)) : *(uint32_t *) (readlookup2[(uint32_t) ((s) + (a)) >> 12] + (uint32_t) ((s) + (a))))
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#define readmemq(s, a) ((readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 7)) ? readmemql((s) + (a)) : *(uint64_t *) (readlookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))))
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#define writememb_n(s, a, b, v) \
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if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF) \
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writemembl_no_mmut((s) + (a), b, v); \
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else \
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*(uint8_t *) (writelookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))) = v
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#define writememw_n(s, a, b, v) \
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if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 1)) \
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writememwl_no_mmut((s) + (a), b, v); \
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else \
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*(uint16_t *) (writelookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))) = v
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#define writememl_n(s, a, b, v) \
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if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 3)) \
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writememll_no_mmut((s) + (a), b, v); \
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else \
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*(uint32_t *) (writelookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))) = v
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#define writememb(s, a, v) \
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if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF) \
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writemembl((s) + (a), v); \
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else \
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*(uint8_t *) (writelookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))) = v
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#define writememw(s, a, v) \
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if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 1)) \
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writememwl((s) + (a), v); \
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else \
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*(uint16_t *) (writelookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))) = v
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#define writememl(s, a, v) \
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if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 3)) \
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writememll((s) + (a), v); \
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else \
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*(uint32_t *) (writelookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))) = v
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#define writememq(s, a, v) \
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if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 7)) \
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writememql((s) + (a), v); \
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else \
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*(uint64_t *) (writelookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))) = v
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#define do_mmut_rb(s, a, b) \
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if (readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF) \
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do_mmutranslate((s) + (a), b, 1, 0)
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#define do_mmut_rw(s, a, b) \
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if (readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 1)) \
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do_mmutranslate((s) + (a), b, 2, 0)
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#define do_mmut_rl(s, a, b) \
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if (readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 3)) \
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do_mmutranslate((s) + (a), b, 4, 0)
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#define do_mmut_rb2(s, a, b) \
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old_rl2 = readlookup2[(uint32_t) ((s) + (a)) >> 12]; \
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if (old_rl2 == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF) \
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do_mmutranslate((s) + (a), b, 1, 0)
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#define do_mmut_rw2(s, a, b) \
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old_rl2 = readlookup2[(uint32_t) ((s) + (a)) >> 12]; \
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if (old_rl2 == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 1)) \
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do_mmutranslate((s) + (a), b, 2, 0)
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#define do_mmut_rl2(s, a, b) \
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old_rl2 = readlookup2[(uint32_t) ((s) + (a)) >> 12]; \
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if (old_rl2 == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 3)) \
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do_mmutranslate((s) + (a), b, 4, 0)
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#define do_mmut_wb(s, a, b) \
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if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF) \
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do_mmutranslate((s) + (a), b, 1, 1)
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#define do_mmut_ww(s, a, b) \
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if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 1)) \
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do_mmutranslate((s) + (a), b, 2, 1)
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#define do_mmut_wl(s, a, b) \
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if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 3)) \
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do_mmutranslate((s) + (a), b, 4, 1)
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2023-08-08 19:39:52 +02:00
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#endif
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2016-06-26 00:34:39 +02:00
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2023-04-22 18:41:42 -03:00
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int checkio(uint32_t port, int mask);
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2020-02-29 19:12:23 +01:00
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2023-04-22 18:41:42 -03:00
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#define check_io_perm(port, size) \
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2022-11-19 10:40:32 -05:00
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if (msw & 1 && ((CPL > IOPL) || (cpu_state.eflags & VM_FLAG))) { \
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2023-04-22 18:41:42 -03:00
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int tempi = checkio(port, (1 << size) - 1); \
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2022-11-19 10:40:32 -05:00
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if (cpu_state.abrt) \
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return 1; \
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if (tempi) { \
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if (cpu_state.eflags & VM_FLAG) \
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x86gpf_expected(NULL, 0); \
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else \
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x86gpf(NULL, 0); \
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return 1; \
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} \
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}
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#define SEG_CHECK_READ(seg) \
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do { \
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if ((seg)->base == 0xffffffff) { \
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x86gpf("Segment can't read", 0); \
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return 1; \
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} \
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} while (0)
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#define SEG_CHECK_WRITE(seg) \
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do { \
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if ((seg)->base == 0xffffffff) { \
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x86gpf("Segment can't write", 0); \
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return 1; \
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} \
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} while (0)
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#define CHECK_READ(chseg, low, high) \
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if ((low < (chseg)->limit_low) || (high > (chseg)->limit_high) || ((msw & 1) && !(cpu_state.eflags & VM_FLAG) && (((chseg)->access & 10) == 8))) { \
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x86gpf("Limit check (READ)", 0); \
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return 1; \
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} \
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if (msw & 1 && !(cpu_state.eflags & VM_FLAG) && !((chseg)->access & 0x80)) { \
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if ((chseg) == &cpu_state.seg_ss) \
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x86ss(NULL, (chseg)->seg & 0xfffc); \
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else \
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x86np("Read from seg not present", (chseg)->seg & 0xfffc); \
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return 1; \
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}
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#define CHECK_READ_REP(chseg, low, high) \
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if ((low < (chseg)->limit_low) || (high > (chseg)->limit_high)) { \
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x86gpf("Limit check (READ)", 0); \
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break; \
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} \
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if (msw & 1 && !(cpu_state.eflags & VM_FLAG) && !((chseg)->access & 0x80)) { \
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if ((chseg) == &cpu_state.seg_ss) \
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x86ss(NULL, (chseg)->seg & 0xfffc); \
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else \
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x86np("Read from seg not present", (chseg)->seg & 0xfffc); \
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break; \
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}
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#define CHECK_WRITE_COMMON(chseg, low, high) \
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if ((low < (chseg)->limit_low) || (high > (chseg)->limit_high) || !((chseg)->access & 2) || ((msw & 1) && !(cpu_state.eflags & VM_FLAG) && ((chseg)->access & 8))) { \
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x86gpf("Limit check (WRITE)", 0); \
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return 1; \
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} \
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if (msw & 1 && !(cpu_state.eflags & VM_FLAG) && !((chseg)->access & 0x80)) { \
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if ((chseg) == &cpu_state.seg_ss) \
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x86ss(NULL, (chseg)->seg & 0xfffc); \
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else \
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x86np("Write to seg not present", (chseg)->seg & 0xfffc); \
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return 1; \
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}
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#define CHECK_WRITE(chseg, low, high) \
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CHECK_WRITE_COMMON(chseg, low, high)
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#define CHECK_WRITE_REP(chseg, low, high) \
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if ((low < (chseg)->limit_low) || (high > (chseg)->limit_high)) { \
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x86gpf("Limit check (WRITE REP)", 0); \
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break; \
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} \
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|
|
if (msw & 1 && !(cpu_state.eflags & VM_FLAG) && !((chseg)->access & 0x80)) { \
|
|
|
|
|
if ((chseg) == &cpu_state.seg_ss) \
|
|
|
|
|
x86ss(NULL, (chseg)->seg & 0xfffc); \
|
|
|
|
|
else \
|
|
|
|
|
x86np("Write (REP) to seg not present", (chseg)->seg & 0xfffc); \
|
|
|
|
|
break; \
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#define NOTRM \
|
|
|
|
|
if (!(msw & 1) || (cpu_state.eflags & VM_FLAG)) { \
|
|
|
|
|
x86_int(6); \
|
|
|
|
|
return 1; \
|
|
|
|
|
}
|
|
|
|
|
|
2023-08-08 19:39:52 +02:00
|
|
|
#ifdef OPS_286_386
|
|
|
|
|
/* TODO: Introduce functions to read exec. */
|
|
|
|
|
static __inline uint8_t fastreadb(uint32_t a)
|
|
|
|
|
{
|
|
|
|
|
return readmembl(a);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline uint16_t fastreadw(uint32_t a)
|
|
|
|
|
{
|
|
|
|
|
return readmemwl(a);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline uint32_t fastreadl(uint32_t a)
|
|
|
|
|
{
|
|
|
|
|
return readmemll(a);
|
|
|
|
|
}
|
|
|
|
|
#else
|
2022-11-19 10:40:32 -05:00
|
|
|
static __inline uint8_t
|
|
|
|
|
fastreadb(uint32_t a)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2022-11-19 10:40:32 -05:00
|
|
|
uint8_t *t;
|
|
|
|
|
|
|
|
|
|
if ((a >> 12) == pccache)
|
2023-06-25 22:20:11 +02:00
|
|
|
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
|
|
|
|
|
return *((uint8_t *) (((uintptr_t) &pccache2[a] & 0x00000000ffffffffULL) | ((uintptr_t) &pccache2[0] & 0xffffffff00000000ULL)));
|
|
|
|
|
#else
|
2022-11-19 10:40:32 -05:00
|
|
|
return *((uint8_t *) &pccache2[a]);
|
2023-06-25 22:20:11 +02:00
|
|
|
#endif
|
2022-11-19 10:40:32 -05:00
|
|
|
t = getpccache(a);
|
|
|
|
|
if (cpu_state.abrt)
|
|
|
|
|
return 0;
|
|
|
|
|
pccache = a >> 12;
|
|
|
|
|
pccache2 = t;
|
2023-06-25 22:20:11 +02:00
|
|
|
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
|
|
|
|
|
return *((uint8_t *) (((uintptr_t) &pccache2[a] & 0x00000000ffffffffULL) | ((uintptr_t) &pccache2[0] & 0xffffffff00000000ULL)));
|
|
|
|
|
#else
|
2022-11-19 10:40:32 -05:00
|
|
|
return *((uint8_t *) &pccache2[a]);
|
2023-06-25 22:20:11 +02:00
|
|
|
#endif
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2022-11-19 10:40:32 -05:00
|
|
|
static __inline uint16_t
|
|
|
|
|
fastreadw(uint32_t a)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2022-11-19 10:40:32 -05:00
|
|
|
uint8_t *t;
|
|
|
|
|
uint16_t val;
|
|
|
|
|
if ((a & 0xFFF) > 0xFFE) {
|
|
|
|
|
val = fastreadb(a);
|
|
|
|
|
val |= (fastreadb(a + 1) << 8);
|
|
|
|
|
return val;
|
|
|
|
|
}
|
|
|
|
|
if ((a >> 12) == pccache)
|
2023-06-25 22:20:11 +02:00
|
|
|
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
|
|
|
|
|
return *((uint16_t *) (((uintptr_t) &pccache2[a] & 0x00000000ffffffffULL) | ((uintptr_t) &pccache2[0] & 0xffffffff00000000ULL)));
|
|
|
|
|
#else
|
2022-11-19 10:40:32 -05:00
|
|
|
return *((uint16_t *) &pccache2[a]);
|
2023-06-25 22:20:11 +02:00
|
|
|
#endif
|
2022-11-19 10:40:32 -05:00
|
|
|
t = getpccache(a);
|
|
|
|
|
if (cpu_state.abrt)
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
pccache = a >> 12;
|
|
|
|
|
pccache2 = t;
|
2023-06-25 22:20:11 +02:00
|
|
|
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
|
|
|
|
|
return *((uint16_t *) (((uintptr_t) &pccache2[a] & 0x00000000ffffffffULL) | ((uintptr_t) &pccache2[0] & 0xffffffff00000000ULL)));
|
|
|
|
|
#else
|
2022-11-19 10:40:32 -05:00
|
|
|
return *((uint16_t *) &pccache2[a]);
|
2023-06-25 22:20:11 +02:00
|
|
|
#endif
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2022-11-19 10:40:32 -05:00
|
|
|
static __inline uint32_t
|
|
|
|
|
fastreadl(uint32_t a)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2022-11-19 10:40:32 -05:00
|
|
|
uint8_t *t;
|
|
|
|
|
uint32_t val;
|
|
|
|
|
if ((a & 0xFFF) < 0xFFD) {
|
|
|
|
|
if ((a >> 12) != pccache) {
|
|
|
|
|
t = getpccache(a);
|
|
|
|
|
if (cpu_state.abrt)
|
|
|
|
|
return 0;
|
|
|
|
|
pccache2 = t;
|
|
|
|
|
pccache = a >> 12;
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
2023-06-25 22:20:11 +02:00
|
|
|
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
|
|
|
|
|
return *((uint32_t *) (((uintptr_t) &pccache2[a] & 0x00000000ffffffffULL) | ((uintptr_t) &pccache2[0] & 0xffffffff00000000ULL)));
|
|
|
|
|
#else
|
2022-11-19 10:40:32 -05:00
|
|
|
return *((uint32_t *) &pccache2[a]);
|
2023-06-25 22:20:11 +02:00
|
|
|
#endif
|
2022-11-19 10:40:32 -05:00
|
|
|
}
|
|
|
|
|
val = fastreadw(a);
|
|
|
|
|
val |= (fastreadw(a + 2) << 16);
|
|
|
|
|
return val;
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
2023-08-08 19:39:52 +02:00
|
|
|
#endif
|
2016-06-26 00:34:39 +02:00
|
|
|
|
2022-11-19 10:40:32 -05:00
|
|
|
static __inline void *
|
|
|
|
|
get_ram_ptr(uint32_t a)
|
Added the IBM 5161 ISA expansion for PC and XT;
Cleaned up the parallel port emulation, added IRQ support, and made enabling/disabling per port;
Added the Award 430NX and the Intel Classic/PCI (Alfredo, 420TX);
Finished the 586MC1;
Added 8087 emulation;
Moved Cyrix 6x86'es to the Dev branch;
Sanitized/cleaned up memregs.c/h and intel.c/h;
Split the chipsets from machines and sanitized Port 92 emulation;
Added support for the 15bpp mode to the Compaq ATI 28800;
Moved the MR 386DX and 486 machines to the Dev branch;
Ported the new dynamic recompiler from PCem, but it remains in Dev branch until after v2.00;
Ported the new timer code from PCem;
Cleaned up the CPU table of unused stuff and better optimized its structure;
Ported the Open-XT and Open-AT from VARCem, the Open-AT is in the Dev branch;
Ported the XT MFM controller rewrite and adding of more controllers (incl. two RLL ones), from VARCem;
Added the AHA-1540A and the BusTek BT-542B;
Moved the Sumo SCSI-AT to the Dev branch;
Minor IDE, FDC, and floppy drive code clean-ups;
Made NCR 5380/53C400-based cards' BIOS address configurable;
Got rid of the legacy romset variable;
Unified (video) buffer and buffer32 into one and make the unified buffer 32-bit;
Added the Amstead PPC512 per PCem patch by John Elliott;
Switched memory mapping granularity from 16k to 4k (less than 1k not possible due to internal pages);
Rewrote the CL-GD 54xx blitter, fixes Win-OS/2 on the 54x6 among other thing;
Added the Image Manager 1024 and Professional Graphics Controller per PCem patch by John Elliott and work done on VARCem;
Added Headland HT-216, GC-205 and Video 7 VGA 1024i emulation based on PCem commit;
Implemented the fuction keys for the Toshiba T1000/T1200/T3100 enhancement;
Amstrad MegaPC does now works correctly with non-internal graphics card;
The SLiRP code no longer casts a packed struct type to a non-packed struct type;
The Xi8088 and PB410a no longer hang on 86Box when PS/2 mouse is not present;
The S3 Virge on BeOS is no longer broken (was broken by build #1591);
OS/2 2.0 build 6.167 now sees key presses again;
Xi8088 now work on CGA again;
86F images converted from either the old or new variants of the HxC MFM format now work correctly;
Hardware interrupts with a vector of 0xFF are now handled correctly;
OPTi 495SX boards no longer incorrectly have 64 MB maximum RAM when 32 MB is correct;
Fixed VNC keyboard input bugs;
Fixed AT RTC periodic interrupt - Chicago 58s / 73f / 73g / 81 MIDI play no longer hangs with the build's own VTD driver;
Fixed mouse polling with internal mice - Amstrad and Olivetti mice now work correctly;
Triones ATAPI DMA driver now correctly reads a file at the end of a CD image with a sectors number not divisible by 4;
Compaq Portable now works with all graphics cards;
Fixed various MDSI Genius bugs;
Added segment limit checks and improved page fault checks for several CPU instructions - Memphis 15xx WINSETUP and Chicago 58s WINDISK.CPL no longer issue a GPF, and some S3 drivers that used to have glitches, now work correctly;
Further improved the 808x emulation, also fixes the noticably choppy sound when using 808x CPU's, also fixes #355;
OS/2 installer no logner locks up on splash screen on PS/2 Model 70 and 80, fixes #400.
Fixed several Amstead bugs, GEM no longer crashes on the Amstrad 1640, fixes #391.
Ported John Elliott's Amstrad fixes and improvement from PCem, and fixed the default language so it's correctly Engliish, fixes #278, fixes #389.
Fixed a minor IDE timing bug, fixes #388.
Fixed Toshiba T1000 RAM issues, fixes #379.
Fixed EGA/(S)VGA overscan border handling, fixes #378;
Got rid of the now long useless IDE channel 2 auto-removal, fixes #370;
Fixed the BIOS files used by the AMSTRAD PC1512, fixes #366;
Ported the Unicode CD image file name fix from VARCem, fixes #365;
Fixed high density floppy disks on the Xi8088, fixes #359;
Fixed some bugs in the Hercules emulation, fixes #346, fixes #358;
Fixed the SCSI hard disk mode sense pages, fixes #356;
Removed the AMI Unknown 386SX because of impossibility to identify the chipset, closes #349;
Fixed bugs in the serial mouse emulation, fixes #344;
Compiled 86Box binaries now include all the required .DLL's, fixes #341;
Made some combo boxes in the Settings dialog slightly wider, fixes #276.
2019-09-20 14:02:30 +02:00
|
|
|
{
|
2022-11-19 10:40:32 -05:00
|
|
|
if ((a >> 12) == pccache)
|
2023-06-25 22:20:11 +02:00
|
|
|
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
|
|
|
|
|
return (void *) (((uintptr_t) &pccache2[a] & 0x00000000ffffffffULL) | ((uintptr_t) &pccache2[0] & 0xffffffff00000000ULL));
|
|
|
|
|
#else
|
2022-11-19 10:40:32 -05:00
|
|
|
return &pccache2[a];
|
2023-06-25 22:20:11 +02:00
|
|
|
#endif
|
2022-11-19 10:40:32 -05:00
|
|
|
else {
|
|
|
|
|
uint8_t *t = getpccache(a);
|
2023-06-25 22:20:11 +02:00
|
|
|
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
|
|
|
|
|
return (void *) (((uintptr_t) &t[a] & 0x00000000ffffffffULL) | ((uintptr_t) &t[0] & 0xffffffff00000000ULL));
|
|
|
|
|
#else
|
2022-11-19 10:40:32 -05:00
|
|
|
return &t[a];
|
2023-06-25 22:20:11 +02:00
|
|
|
#endif
|
2022-11-19 10:40:32 -05:00
|
|
|
}
|
Added the IBM 5161 ISA expansion for PC and XT;
Cleaned up the parallel port emulation, added IRQ support, and made enabling/disabling per port;
Added the Award 430NX and the Intel Classic/PCI (Alfredo, 420TX);
Finished the 586MC1;
Added 8087 emulation;
Moved Cyrix 6x86'es to the Dev branch;
Sanitized/cleaned up memregs.c/h and intel.c/h;
Split the chipsets from machines and sanitized Port 92 emulation;
Added support for the 15bpp mode to the Compaq ATI 28800;
Moved the MR 386DX and 486 machines to the Dev branch;
Ported the new dynamic recompiler from PCem, but it remains in Dev branch until after v2.00;
Ported the new timer code from PCem;
Cleaned up the CPU table of unused stuff and better optimized its structure;
Ported the Open-XT and Open-AT from VARCem, the Open-AT is in the Dev branch;
Ported the XT MFM controller rewrite and adding of more controllers (incl. two RLL ones), from VARCem;
Added the AHA-1540A and the BusTek BT-542B;
Moved the Sumo SCSI-AT to the Dev branch;
Minor IDE, FDC, and floppy drive code clean-ups;
Made NCR 5380/53C400-based cards' BIOS address configurable;
Got rid of the legacy romset variable;
Unified (video) buffer and buffer32 into one and make the unified buffer 32-bit;
Added the Amstead PPC512 per PCem patch by John Elliott;
Switched memory mapping granularity from 16k to 4k (less than 1k not possible due to internal pages);
Rewrote the CL-GD 54xx blitter, fixes Win-OS/2 on the 54x6 among other thing;
Added the Image Manager 1024 and Professional Graphics Controller per PCem patch by John Elliott and work done on VARCem;
Added Headland HT-216, GC-205 and Video 7 VGA 1024i emulation based on PCem commit;
Implemented the fuction keys for the Toshiba T1000/T1200/T3100 enhancement;
Amstrad MegaPC does now works correctly with non-internal graphics card;
The SLiRP code no longer casts a packed struct type to a non-packed struct type;
The Xi8088 and PB410a no longer hang on 86Box when PS/2 mouse is not present;
The S3 Virge on BeOS is no longer broken (was broken by build #1591);
OS/2 2.0 build 6.167 now sees key presses again;
Xi8088 now work on CGA again;
86F images converted from either the old or new variants of the HxC MFM format now work correctly;
Hardware interrupts with a vector of 0xFF are now handled correctly;
OPTi 495SX boards no longer incorrectly have 64 MB maximum RAM when 32 MB is correct;
Fixed VNC keyboard input bugs;
Fixed AT RTC periodic interrupt - Chicago 58s / 73f / 73g / 81 MIDI play no longer hangs with the build's own VTD driver;
Fixed mouse polling with internal mice - Amstrad and Olivetti mice now work correctly;
Triones ATAPI DMA driver now correctly reads a file at the end of a CD image with a sectors number not divisible by 4;
Compaq Portable now works with all graphics cards;
Fixed various MDSI Genius bugs;
Added segment limit checks and improved page fault checks for several CPU instructions - Memphis 15xx WINSETUP and Chicago 58s WINDISK.CPL no longer issue a GPF, and some S3 drivers that used to have glitches, now work correctly;
Further improved the 808x emulation, also fixes the noticably choppy sound when using 808x CPU's, also fixes #355;
OS/2 installer no logner locks up on splash screen on PS/2 Model 70 and 80, fixes #400.
Fixed several Amstead bugs, GEM no longer crashes on the Amstrad 1640, fixes #391.
Ported John Elliott's Amstrad fixes and improvement from PCem, and fixed the default language so it's correctly Engliish, fixes #278, fixes #389.
Fixed a minor IDE timing bug, fixes #388.
Fixed Toshiba T1000 RAM issues, fixes #379.
Fixed EGA/(S)VGA overscan border handling, fixes #378;
Got rid of the now long useless IDE channel 2 auto-removal, fixes #370;
Fixed the BIOS files used by the AMSTRAD PC1512, fixes #366;
Ported the Unicode CD image file name fix from VARCem, fixes #365;
Fixed high density floppy disks on the Xi8088, fixes #359;
Fixed some bugs in the Hercules emulation, fixes #346, fixes #358;
Fixed the SCSI hard disk mode sense pages, fixes #356;
Removed the AMI Unknown 386SX because of impossibility to identify the chipset, closes #349;
Fixed bugs in the serial mouse emulation, fixes #344;
Compiled 86Box binaries now include all the required .DLL's, fixes #341;
Made some combo boxes in the Settings dialog slightly wider, fixes #276.
2019-09-20 14:02:30 +02:00
|
|
|
}
|
|
|
|
|
|
2023-06-09 14:55:13 +02:00
|
|
|
extern int opcode_length[256];
|
|
|
|
|
|
2023-08-08 19:39:52 +02:00
|
|
|
#ifdef OPS_286_386
|
|
|
|
|
static __inline uint16_t
|
|
|
|
|
fastreadw_fetch(uint32_t a)
|
|
|
|
|
{
|
|
|
|
|
uint16_t val;
|
|
|
|
|
|
|
|
|
|
if ((a & 0xFFF) > 0xFFE) {
|
|
|
|
|
val = fastreadb(a);
|
|
|
|
|
if (opcode_length[val & 0xff] > 1)
|
|
|
|
|
val |= (fastreadb(a + 1) << 8);
|
|
|
|
|
return val;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return readmemwl(a);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline uint32_t
|
|
|
|
|
fastreadl_fetch(uint32_t a)
|
|
|
|
|
{
|
|
|
|
|
uint32_t val;
|
|
|
|
|
|
|
|
|
|
if ((a & 0xFFF) > 0xFFC) {
|
|
|
|
|
val = fastreadw_fetch(a);
|
|
|
|
|
if (opcode_length[val & 0xff] > 2)
|
|
|
|
|
val |= (fastreadw(a + 2) << 16);
|
|
|
|
|
return val;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return readmemll(a);
|
|
|
|
|
}
|
|
|
|
|
#else
|
2023-06-09 14:55:13 +02:00
|
|
|
static __inline uint16_t
|
|
|
|
|
fastreadw_fetch(uint32_t a)
|
|
|
|
|
{
|
|
|
|
|
uint8_t *t;
|
|
|
|
|
uint16_t val;
|
|
|
|
|
if ((a & 0xFFF) > 0xFFE) {
|
|
|
|
|
val = fastreadb(a);
|
|
|
|
|
if (opcode_length[val & 0xff] > 1)
|
|
|
|
|
val |= (fastreadb(a + 1) << 8);
|
|
|
|
|
return val;
|
|
|
|
|
}
|
|
|
|
|
if ((a >> 12) == pccache)
|
2023-06-25 22:20:11 +02:00
|
|
|
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
|
|
|
|
|
return *((uint16_t *) (((uintptr_t) &pccache2[a] & 0x00000000ffffffffULL) | ((uintptr_t) &pccache2[0] & 0xffffffff00000000ULL)));
|
|
|
|
|
#else
|
2023-06-09 14:55:13 +02:00
|
|
|
return *((uint16_t *) &pccache2[a]);
|
2023-06-25 22:20:11 +02:00
|
|
|
#endif
|
2023-06-09 14:55:13 +02:00
|
|
|
t = getpccache(a);
|
|
|
|
|
if (cpu_state.abrt)
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
pccache = a >> 12;
|
|
|
|
|
pccache2 = t;
|
2023-06-25 22:20:11 +02:00
|
|
|
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
|
|
|
|
|
return *((uint16_t *) (((uintptr_t) &pccache2[a] & 0x00000000ffffffffULL) | ((uintptr_t) &pccache2[0] & 0xffffffff00000000ULL)));
|
|
|
|
|
#else
|
2023-06-09 14:55:13 +02:00
|
|
|
return *((uint16_t *) &pccache2[a]);
|
2023-06-25 22:20:11 +02:00
|
|
|
#endif
|
2023-06-09 14:55:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline uint32_t
|
|
|
|
|
fastreadl_fetch(uint32_t a)
|
|
|
|
|
{
|
|
|
|
|
uint8_t *t;
|
|
|
|
|
uint32_t val;
|
|
|
|
|
if ((a & 0xFFF) < 0xFFD) {
|
|
|
|
|
if ((a >> 12) != pccache) {
|
|
|
|
|
t = getpccache(a);
|
|
|
|
|
if (cpu_state.abrt)
|
|
|
|
|
return 0;
|
|
|
|
|
pccache2 = t;
|
|
|
|
|
pccache = a >> 12;
|
|
|
|
|
}
|
2023-06-25 22:20:11 +02:00
|
|
|
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
|
|
|
|
|
return *((uint32_t *) (((uintptr_t) &pccache2[a] & 0x00000000ffffffffULL) | ((uintptr_t) &pccache2[0] & 0xffffffff00000000ULL)));
|
|
|
|
|
#else
|
2023-06-09 14:55:13 +02:00
|
|
|
return *((uint32_t *) &pccache2[a]);
|
2023-06-25 22:20:11 +02:00
|
|
|
#endif
|
2023-06-09 14:55:13 +02:00
|
|
|
}
|
|
|
|
|
val = fastreadw_fetch(a);
|
|
|
|
|
if (opcode_length[val & 0xff] > 2)
|
|
|
|
|
val |= (fastreadw(a + 2) << 16);
|
|
|
|
|
return val;
|
|
|
|
|
}
|
2023-08-08 19:39:52 +02:00
|
|
|
#endif
|
2023-06-09 14:55:13 +02:00
|
|
|
|
2022-11-19 10:40:32 -05:00
|
|
|
static __inline uint8_t
|
|
|
|
|
getbyte(void)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2022-11-19 10:40:32 -05:00
|
|
|
cpu_state.pc++;
|
|
|
|
|
return fastreadb(cs + (cpu_state.pc - 1));
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2022-11-19 10:40:32 -05:00
|
|
|
static __inline uint16_t
|
|
|
|
|
getword(void)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2022-11-19 10:40:32 -05:00
|
|
|
cpu_state.pc += 2;
|
|
|
|
|
return fastreadw(cs + (cpu_state.pc - 2));
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2022-11-19 10:40:32 -05:00
|
|
|
static __inline uint32_t
|
|
|
|
|
getlong(void)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2022-11-19 10:40:32 -05:00
|
|
|
cpu_state.pc += 4;
|
|
|
|
|
return fastreadl(cs + (cpu_state.pc - 4));
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2022-11-19 10:40:32 -05:00
|
|
|
static __inline uint64_t
|
|
|
|
|
getquad(void)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2022-11-19 10:40:32 -05:00
|
|
|
cpu_state.pc += 8;
|
|
|
|
|
return fastreadl(cs + (cpu_state.pc - 8)) | ((uint64_t) fastreadl(cs + (cpu_state.pc - 4)) << 32);
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2023-08-08 19:39:52 +02:00
|
|
|
#ifdef OPS_286_386
|
2023-08-08 21:01:01 +02:00
|
|
|
static __inline uint8_t geteab(void)
|
2023-08-08 19:39:52 +02:00
|
|
|
{
|
|
|
|
|
if (cpu_mod == 3)
|
|
|
|
|
return (cpu_rm & 4) ? cpu_state.regs[cpu_rm & 3].b.h : cpu_state.regs[cpu_rm&3].b.l;
|
|
|
|
|
return readmemb(easeg, cpu_state.eaaddr);
|
|
|
|
|
}
|
|
|
|
|
|
2023-08-08 21:01:01 +02:00
|
|
|
static __inline uint16_t geteaw(void)
|
2023-08-08 19:39:52 +02:00
|
|
|
{
|
|
|
|
|
if (cpu_mod == 3)
|
|
|
|
|
return cpu_state.regs[cpu_rm].w;
|
|
|
|
|
return readmemw(easeg, cpu_state.eaaddr);
|
|
|
|
|
}
|
|
|
|
|
|
2023-08-08 21:01:01 +02:00
|
|
|
static __inline uint32_t geteal(void)
|
2023-08-08 19:39:52 +02:00
|
|
|
{
|
|
|
|
|
if (cpu_mod == 3)
|
|
|
|
|
return cpu_state.regs[cpu_rm].l;
|
|
|
|
|
return readmeml(easeg, cpu_state.eaaddr);
|
|
|
|
|
}
|
|
|
|
|
|
2023-08-08 21:01:01 +02:00
|
|
|
static __inline uint64_t geteaq(void)
|
2023-08-08 19:39:52 +02:00
|
|
|
{
|
|
|
|
|
return readmemq(easeg, cpu_state.eaaddr);
|
|
|
|
|
}
|
|
|
|
|
|
2023-08-08 21:01:01 +02:00
|
|
|
static __inline uint8_t geteab_mem(void)
|
2023-08-08 19:39:52 +02:00
|
|
|
{
|
|
|
|
|
return readmemb(easeg,cpu_state.eaaddr);
|
|
|
|
|
}
|
2023-08-08 21:01:01 +02:00
|
|
|
static __inline uint16_t geteaw_mem(void)
|
2023-08-08 19:39:52 +02:00
|
|
|
{
|
|
|
|
|
return readmemw(easeg,cpu_state.eaaddr);
|
|
|
|
|
}
|
2023-08-08 21:01:01 +02:00
|
|
|
static __inline uint32_t geteal_mem(void)
|
2023-08-08 19:39:52 +02:00
|
|
|
{
|
|
|
|
|
return readmeml(easeg,cpu_state.eaaddr);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline int seteaq_cwc(void)
|
|
|
|
|
{
|
|
|
|
|
CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline void seteaq(uint64_t v)
|
|
|
|
|
{
|
|
|
|
|
if (seteaq_cwc())
|
|
|
|
|
return;
|
|
|
|
|
writememql(easeg + cpu_state.eaaddr, v);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#define seteab(v) if (cpu_mod!=3) { CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr); writemembl_2386(easeg+cpu_state.eaaddr,v); } else if (cpu_rm&4) cpu_state.regs[cpu_rm&3].b.h=v; else cpu_state.regs[cpu_rm].b.l=v
|
|
|
|
|
#define seteaw(v) if (cpu_mod!=3) { CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 1); writememwl_2386(easeg+cpu_state.eaaddr,v); } else cpu_state.regs[cpu_rm].w=v
|
|
|
|
|
#define seteal(v) if (cpu_mod!=3) { CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3); writememll_2386(easeg+cpu_state.eaaddr,v); } else cpu_state.regs[cpu_rm].l=v
|
|
|
|
|
|
|
|
|
|
#define seteab_mem(v) writemembl_2386(easeg+cpu_state.eaaddr,v);
|
|
|
|
|
#define seteaw_mem(v) writememwl_2386(easeg+cpu_state.eaaddr,v);
|
|
|
|
|
#define seteal_mem(v) writememll_2386(easeg+cpu_state.eaaddr,v);
|
|
|
|
|
#else
|
2022-11-19 10:40:32 -05:00
|
|
|
static __inline uint8_t
|
|
|
|
|
geteab(void)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2022-11-19 10:40:32 -05:00
|
|
|
if (cpu_mod == 3)
|
|
|
|
|
return (cpu_rm & 4) ? cpu_state.regs[cpu_rm & 3].b.h : cpu_state.regs[cpu_rm & 3].b.l;
|
|
|
|
|
if (eal_r)
|
|
|
|
|
return *(uint8_t *) eal_r;
|
|
|
|
|
return readmemb(easeg, cpu_state.eaaddr);
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2022-11-19 10:40:32 -05:00
|
|
|
static __inline uint16_t
|
|
|
|
|
geteaw(void)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2022-11-19 10:40:32 -05:00
|
|
|
if (cpu_mod == 3)
|
|
|
|
|
return cpu_state.regs[cpu_rm].w;
|
|
|
|
|
if (eal_r)
|
|
|
|
|
return *(uint16_t *) eal_r;
|
|
|
|
|
return readmemw(easeg, cpu_state.eaaddr);
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2022-11-19 10:40:32 -05:00
|
|
|
static __inline uint32_t
|
|
|
|
|
geteal(void)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2022-11-19 10:40:32 -05:00
|
|
|
if (cpu_mod == 3)
|
|
|
|
|
return cpu_state.regs[cpu_rm].l;
|
|
|
|
|
if (eal_r)
|
|
|
|
|
return *eal_r;
|
|
|
|
|
return readmeml(easeg, cpu_state.eaaddr);
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2022-11-19 10:40:32 -05:00
|
|
|
static __inline uint64_t
|
|
|
|
|
geteaq(void)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2022-11-19 10:40:32 -05:00
|
|
|
return readmemq(easeg, cpu_state.eaaddr);
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2022-11-19 10:40:32 -05:00
|
|
|
static __inline uint8_t
|
|
|
|
|
geteab_mem(void)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2022-11-19 10:40:32 -05:00
|
|
|
if (eal_r)
|
|
|
|
|
return *(uint8_t *) eal_r;
|
|
|
|
|
return readmemb(easeg, cpu_state.eaaddr);
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
2022-11-19 10:40:32 -05:00
|
|
|
static __inline uint16_t
|
|
|
|
|
geteaw_mem(void)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2022-11-19 10:40:32 -05:00
|
|
|
if (eal_r)
|
|
|
|
|
return *(uint16_t *) eal_r;
|
|
|
|
|
return readmemw(easeg, cpu_state.eaaddr);
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
2022-11-19 10:40:32 -05:00
|
|
|
static __inline uint32_t
|
|
|
|
|
geteal_mem(void)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2022-11-19 10:40:32 -05:00
|
|
|
if (eal_r)
|
|
|
|
|
return *eal_r;
|
|
|
|
|
return readmeml(easeg, cpu_state.eaaddr);
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2022-11-19 10:40:32 -05:00
|
|
|
static __inline int
|
|
|
|
|
seteaq_cwc(void)
|
2019-09-21 03:33:05 +02:00
|
|
|
{
|
2022-11-19 10:40:32 -05:00
|
|
|
CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr);
|
|
|
|
|
return 0;
|
2019-09-21 03:33:05 +02:00
|
|
|
}
|
|
|
|
|
|
2022-11-19 10:40:32 -05:00
|
|
|
static __inline void
|
|
|
|
|
seteaq(uint64_t v)
|
2016-06-26 00:34:39 +02:00
|
|
|
{
|
2022-11-19 10:40:32 -05:00
|
|
|
if (seteaq_cwc())
|
|
|
|
|
return;
|
|
|
|
|
writememql(easeg + cpu_state.eaaddr, v);
|
2016-06-26 00:34:39 +02:00
|
|
|
}
|
|
|
|
|
|
2022-11-19 10:40:32 -05:00
|
|
|
#define seteab(v) \
|
|
|
|
|
if (cpu_mod != 3) { \
|
|
|
|
|
CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr); \
|
|
|
|
|
if (eal_w) \
|
|
|
|
|
*(uint8_t *) eal_w = v; \
|
|
|
|
|
else \
|
|
|
|
|
writemembl(easeg + cpu_state.eaaddr, v); \
|
|
|
|
|
} else if (cpu_rm & 4) \
|
|
|
|
|
cpu_state.regs[cpu_rm & 3].b.h = v; \
|
|
|
|
|
else \
|
|
|
|
|
cpu_state.regs[cpu_rm].b.l = v
|
|
|
|
|
#define seteaw(v) \
|
|
|
|
|
if (cpu_mod != 3) { \
|
|
|
|
|
CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 1); \
|
|
|
|
|
if (eal_w) \
|
|
|
|
|
*(uint16_t *) eal_w = v; \
|
|
|
|
|
else \
|
|
|
|
|
writememwl(easeg + cpu_state.eaaddr, v); \
|
|
|
|
|
} else \
|
|
|
|
|
cpu_state.regs[cpu_rm].w = v
|
|
|
|
|
#define seteal(v) \
|
|
|
|
|
if (cpu_mod != 3) { \
|
|
|
|
|
CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3); \
|
|
|
|
|
if (eal_w) \
|
|
|
|
|
*eal_w = v; \
|
|
|
|
|
else \
|
|
|
|
|
writememll(easeg + cpu_state.eaaddr, v); \
|
|
|
|
|
} else \
|
|
|
|
|
cpu_state.regs[cpu_rm].l = v
|
|
|
|
|
|
|
|
|
|
#define seteab_mem(v) \
|
|
|
|
|
if (eal_w) \
|
|
|
|
|
*(uint8_t *) eal_w = v; \
|
|
|
|
|
else \
|
|
|
|
|
writemembl(easeg + cpu_state.eaaddr, v);
|
|
|
|
|
#define seteaw_mem(v) \
|
|
|
|
|
if (eal_w) \
|
|
|
|
|
*(uint16_t *) eal_w = v; \
|
|
|
|
|
else \
|
|
|
|
|
writememwl(easeg + cpu_state.eaaddr, v);
|
|
|
|
|
#define seteal_mem(v) \
|
|
|
|
|
if (eal_w) \
|
|
|
|
|
*eal_w = v; \
|
|
|
|
|
else \
|
|
|
|
|
writememll(easeg + cpu_state.eaaddr, v);
|
2023-08-08 19:39:52 +02:00
|
|
|
#endif
|
2022-11-19 10:40:32 -05:00
|
|
|
|
|
|
|
|
#define getbytef() \
|
|
|
|
|
((uint8_t) (fetchdat)); \
|
|
|
|
|
cpu_state.pc++
|
|
|
|
|
#define getwordf() \
|
|
|
|
|
((uint16_t) (fetchdat)); \
|
|
|
|
|
cpu_state.pc += 2
|
|
|
|
|
#define getbyte2f() \
|
|
|
|
|
((uint8_t) (fetchdat >> 8)); \
|
|
|
|
|
cpu_state.pc++
|
|
|
|
|
#define getword2f() \
|
|
|
|
|
((uint16_t) (fetchdat >> 8)); \
|
|
|
|
|
cpu_state.pc += 2
|
2020-02-29 19:12:23 +01:00
|
|
|
|
|
|
|
|
#endif
|