2016-08-14 22:07:17 -04:00
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/* Copyright holders: Sarah Walker
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see COPYING for more details
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*/
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2016-06-26 00:34:39 +02:00
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static int opMOVZX_w_b_a16(uint32_t fetchdat)
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{
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uint8_t temp;
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fetch_ea_16(fetchdat);
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temp = geteab(); if (abrt) return 1;
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2016-08-15 01:34:46 +02:00
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cpu_state.regs[cpu_reg].w = (uint16_t)temp;
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2016-06-26 00:34:39 +02:00
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CLOCK_CYCLES(3);
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return 0;
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}
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static int opMOVZX_w_b_a32(uint32_t fetchdat)
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{
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uint8_t temp;
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fetch_ea_32(fetchdat);
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temp = geteab(); if (abrt) return 1;
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2016-08-15 01:34:46 +02:00
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cpu_state.regs[cpu_reg].w = (uint16_t)temp;
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2016-06-26 00:34:39 +02:00
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CLOCK_CYCLES(3);
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return 0;
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}
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static int opMOVZX_l_b_a16(uint32_t fetchdat)
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{
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uint8_t temp;
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fetch_ea_16(fetchdat);
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temp = geteab(); if (abrt) return 1;
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2016-08-15 01:34:46 +02:00
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cpu_state.regs[cpu_reg].l = (uint32_t)temp;
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2016-06-26 00:34:39 +02:00
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CLOCK_CYCLES(3);
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return 0;
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}
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static int opMOVZX_l_b_a32(uint32_t fetchdat)
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{
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uint8_t temp;
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fetch_ea_32(fetchdat);
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temp = geteab(); if (abrt) return 1;
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2016-08-15 01:34:46 +02:00
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cpu_state.regs[cpu_reg].l = (uint32_t)temp;
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2016-06-26 00:34:39 +02:00
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CLOCK_CYCLES(3);
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return 0;
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}
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static int opMOVZX_w_w_a16(uint32_t fetchdat)
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{
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uint16_t temp;
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fetch_ea_16(fetchdat);
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temp = geteaw(); if (abrt) return 1;
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2016-08-15 01:34:46 +02:00
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cpu_state.regs[cpu_reg].w = temp;
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2016-06-26 00:34:39 +02:00
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CLOCK_CYCLES(3);
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return 0;
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}
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static int opMOVZX_w_w_a32(uint32_t fetchdat)
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{
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uint16_t temp;
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fetch_ea_32(fetchdat);
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temp = geteaw(); if (abrt) return 1;
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2016-08-15 01:34:46 +02:00
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cpu_state.regs[cpu_reg].w = temp;
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2016-06-26 00:34:39 +02:00
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CLOCK_CYCLES(3);
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return 0;
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}
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static int opMOVZX_l_w_a16(uint32_t fetchdat)
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{
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uint16_t temp;
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fetch_ea_16(fetchdat);
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temp = geteaw(); if (abrt) return 1;
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2016-08-15 01:34:46 +02:00
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cpu_state.regs[cpu_reg].l = (uint32_t)temp;
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2016-06-26 00:34:39 +02:00
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CLOCK_CYCLES(3);
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return 0;
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}
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static int opMOVZX_l_w_a32(uint32_t fetchdat)
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{
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uint16_t temp;
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fetch_ea_32(fetchdat);
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temp = geteaw(); if (abrt) return 1;
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2016-08-15 01:34:46 +02:00
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cpu_state.regs[cpu_reg].l = (uint32_t)temp;
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2016-06-26 00:34:39 +02:00
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CLOCK_CYCLES(3);
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return 0;
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}
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static int opMOVSX_w_b_a16(uint32_t fetchdat)
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{
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uint8_t temp;
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fetch_ea_16(fetchdat);
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temp = geteab(); if (abrt) return 1;
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2016-08-15 01:34:46 +02:00
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cpu_state.regs[cpu_reg].w = (uint16_t)temp;
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2016-06-26 00:34:39 +02:00
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if (temp & 0x80)
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2016-08-15 01:34:46 +02:00
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cpu_state.regs[cpu_reg].w |= 0xff00;
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2016-06-26 00:34:39 +02:00
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CLOCK_CYCLES(3);
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return 0;
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}
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static int opMOVSX_w_b_a32(uint32_t fetchdat)
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{
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uint8_t temp;
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fetch_ea_32(fetchdat);
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temp = geteab(); if (abrt) return 1;
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2016-08-15 01:34:46 +02:00
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cpu_state.regs[cpu_reg].w = (uint16_t)temp;
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2016-06-26 00:34:39 +02:00
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if (temp & 0x80)
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2016-08-15 01:34:46 +02:00
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cpu_state.regs[cpu_reg].w |= 0xff00;
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2016-06-26 00:34:39 +02:00
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CLOCK_CYCLES(3);
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return 0;
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}
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static int opMOVSX_l_b_a16(uint32_t fetchdat)
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{
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uint8_t temp;
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fetch_ea_16(fetchdat);
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temp = geteab(); if (abrt) return 1;
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2016-08-15 01:34:46 +02:00
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cpu_state.regs[cpu_reg].l = (uint32_t)temp;
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2016-06-26 00:34:39 +02:00
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if (temp & 0x80)
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2016-08-15 01:34:46 +02:00
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cpu_state.regs[cpu_reg].l |= 0xffffff00;
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2016-06-26 00:34:39 +02:00
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CLOCK_CYCLES(3);
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return 0;
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}
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static int opMOVSX_l_b_a32(uint32_t fetchdat)
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{
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uint8_t temp;
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fetch_ea_32(fetchdat);
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temp = geteab(); if (abrt) return 1;
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2016-08-15 01:34:46 +02:00
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cpu_state.regs[cpu_reg].l = (uint32_t)temp;
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2016-06-26 00:34:39 +02:00
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if (temp & 0x80)
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2016-08-15 01:34:46 +02:00
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cpu_state.regs[cpu_reg].l |= 0xffffff00;
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2016-06-26 00:34:39 +02:00
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CLOCK_CYCLES(3);
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return 0;
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}
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static int opMOVSX_l_w_a16(uint32_t fetchdat)
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{
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uint16_t temp;
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fetch_ea_16(fetchdat);
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temp = geteaw(); if (abrt) return 1;
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2016-08-15 01:34:46 +02:00
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cpu_state.regs[cpu_reg].l = (uint32_t)temp;
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2016-06-26 00:34:39 +02:00
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if (temp & 0x8000)
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2016-08-15 01:34:46 +02:00
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cpu_state.regs[cpu_reg].l |= 0xffff0000;
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2016-06-26 00:34:39 +02:00
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CLOCK_CYCLES(3);
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return 0;
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}
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static int opMOVSX_l_w_a32(uint32_t fetchdat)
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{
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uint16_t temp;
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fetch_ea_32(fetchdat);
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temp = geteaw(); if (abrt) return 1;
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2016-08-15 01:34:46 +02:00
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cpu_state.regs[cpu_reg].l = (uint32_t)temp;
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2016-06-26 00:34:39 +02:00
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if (temp & 0x8000)
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2016-08-15 01:34:46 +02:00
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cpu_state.regs[cpu_reg].l |= 0xffff0000;
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2016-06-26 00:34:39 +02:00
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CLOCK_CYCLES(3);
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return 0;
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}
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