Added the IBM 5161 ISA expansion for PC and XT;
Cleaned up the parallel port emulation, added IRQ support, and made enabling/disabling per port;
Added the Award 430NX and the Intel Classic/PCI (Alfredo, 420TX);
Finished the 586MC1;
Added 8087 emulation;
Moved Cyrix 6x86'es to the Dev branch;
Sanitized/cleaned up memregs.c/h and intel.c/h;
Split the chipsets from machines and sanitized Port 92 emulation;
Added support for the 15bpp mode to the Compaq ATI 28800;
Moved the MR 386DX and 486 machines to the Dev branch;
Ported the new dynamic recompiler from PCem, but it remains in Dev branch until after v2.00;
Ported the new timer code from PCem;
Cleaned up the CPU table of unused stuff and better optimized its structure;
Ported the Open-XT and Open-AT from VARCem, the Open-AT is in the Dev branch;
Ported the XT MFM controller rewrite and adding of more controllers (incl. two RLL ones), from VARCem;
Added the AHA-1540A and the BusTek BT-542B;
Moved the Sumo SCSI-AT to the Dev branch;
Minor IDE, FDC, and floppy drive code clean-ups;
Made NCR 5380/53C400-based cards' BIOS address configurable;
Got rid of the legacy romset variable;
Unified (video) buffer and buffer32 into one and make the unified buffer 32-bit;
Added the Amstead PPC512 per PCem patch by John Elliott;
Switched memory mapping granularity from 16k to 4k (less than 1k not possible due to internal pages);
Rewrote the CL-GD 54xx blitter, fixes Win-OS/2 on the 54x6 among other thing;
Added the Image Manager 1024 and Professional Graphics Controller per PCem patch by John Elliott and work done on VARCem;
Added Headland HT-216, GC-205 and Video 7 VGA 1024i emulation based on PCem commit;
Implemented the fuction keys for the Toshiba T1000/T1200/T3100 enhancement;
Amstrad MegaPC does now works correctly with non-internal graphics card;
The SLiRP code no longer casts a packed struct type to a non-packed struct type;
The Xi8088 and PB410a no longer hang on 86Box when PS/2 mouse is not present;
The S3 Virge on BeOS is no longer broken (was broken by build #1591);
OS/2 2.0 build 6.167 now sees key presses again;
Xi8088 now work on CGA again;
86F images converted from either the old or new variants of the HxC MFM format now work correctly;
Hardware interrupts with a vector of 0xFF are now handled correctly;
OPTi 495SX boards no longer incorrectly have 64 MB maximum RAM when 32 MB is correct;
Fixed VNC keyboard input bugs;
Fixed AT RTC periodic interrupt - Chicago 58s / 73f / 73g / 81 MIDI play no longer hangs with the build's own VTD driver;
Fixed mouse polling with internal mice - Amstrad and Olivetti mice now work correctly;
Triones ATAPI DMA driver now correctly reads a file at the end of a CD image with a sectors number not divisible by 4;
Compaq Portable now works with all graphics cards;
Fixed various MDSI Genius bugs;
Added segment limit checks and improved page fault checks for several CPU instructions - Memphis 15xx WINSETUP and Chicago 58s WINDISK.CPL no longer issue a GPF, and some S3 drivers that used to have glitches, now work correctly;
Further improved the 808x emulation, also fixes the noticably choppy sound when using 808x CPU's, also fixes #355;
OS/2 installer no logner locks up on splash screen on PS/2 Model 70 and 80, fixes #400.
Fixed several Amstead bugs, GEM no longer crashes on the Amstrad 1640, fixes #391.
Ported John Elliott's Amstrad fixes and improvement from PCem, and fixed the default language so it's correctly Engliish, fixes #278, fixes #389.
Fixed a minor IDE timing bug, fixes #388.
Fixed Toshiba T1000 RAM issues, fixes #379.
Fixed EGA/(S)VGA overscan border handling, fixes #378;
Got rid of the now long useless IDE channel 2 auto-removal, fixes #370;
Fixed the BIOS files used by the AMSTRAD PC1512, fixes #366;
Ported the Unicode CD image file name fix from VARCem, fixes #365;
Fixed high density floppy disks on the Xi8088, fixes #359;
Fixed some bugs in the Hercules emulation, fixes #346, fixes #358;
Fixed the SCSI hard disk mode sense pages, fixes #356;
Removed the AMI Unknown 386SX because of impossibility to identify the chipset, closes #349;
Fixed bugs in the serial mouse emulation, fixes #344;
Compiled 86Box binaries now include all the required .DLL's, fixes #341;
Made some combo boxes in the Settings dialog slightly wider, fixes #276.
2019-09-20 14:02:30 +02:00
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static int opPADDB_a16(uint32_t fetchdat)
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{
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MMX_REG src;
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MMX_ENTER();
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fetch_ea_16(fetchdat);
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MMX_GETSRC();
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cpu_state.MM[cpu_reg].b[0] += src.b[0];
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cpu_state.MM[cpu_reg].b[1] += src.b[1];
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cpu_state.MM[cpu_reg].b[2] += src.b[2];
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cpu_state.MM[cpu_reg].b[3] += src.b[3];
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cpu_state.MM[cpu_reg].b[4] += src.b[4];
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cpu_state.MM[cpu_reg].b[5] += src.b[5];
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cpu_state.MM[cpu_reg].b[6] += src.b[6];
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cpu_state.MM[cpu_reg].b[7] += src.b[7];
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return 0;
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}
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static int opPADDB_a32(uint32_t fetchdat)
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{
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MMX_REG src;
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MMX_ENTER();
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fetch_ea_32(fetchdat);
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MMX_GETSRC();
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cpu_state.MM[cpu_reg].b[0] += src.b[0];
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cpu_state.MM[cpu_reg].b[1] += src.b[1];
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cpu_state.MM[cpu_reg].b[2] += src.b[2];
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cpu_state.MM[cpu_reg].b[3] += src.b[3];
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cpu_state.MM[cpu_reg].b[4] += src.b[4];
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cpu_state.MM[cpu_reg].b[5] += src.b[5];
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cpu_state.MM[cpu_reg].b[6] += src.b[6];
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cpu_state.MM[cpu_reg].b[7] += src.b[7];
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return 0;
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}
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static int opPADDW_a16(uint32_t fetchdat)
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{
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MMX_REG src;
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MMX_ENTER();
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fetch_ea_16(fetchdat);
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MMX_GETSRC();
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cpu_state.MM[cpu_reg].w[0] += src.w[0];
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cpu_state.MM[cpu_reg].w[1] += src.w[1];
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cpu_state.MM[cpu_reg].w[2] += src.w[2];
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cpu_state.MM[cpu_reg].w[3] += src.w[3];
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return 0;
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}
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static int opPADDW_a32(uint32_t fetchdat)
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{
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MMX_REG src;
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MMX_ENTER();
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fetch_ea_32(fetchdat);
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MMX_GETSRC();
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cpu_state.MM[cpu_reg].w[0] += src.w[0];
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cpu_state.MM[cpu_reg].w[1] += src.w[1];
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cpu_state.MM[cpu_reg].w[2] += src.w[2];
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cpu_state.MM[cpu_reg].w[3] += src.w[3];
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return 0;
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}
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static int opPADDD_a16(uint32_t fetchdat)
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{
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MMX_REG src;
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|
MMX_ENTER();
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fetch_ea_16(fetchdat);
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MMX_GETSRC();
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cpu_state.MM[cpu_reg].l[0] += src.l[0];
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cpu_state.MM[cpu_reg].l[1] += src.l[1];
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return 0;
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}
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static int opPADDD_a32(uint32_t fetchdat)
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{
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MMX_REG src;
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MMX_ENTER();
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fetch_ea_32(fetchdat);
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MMX_GETSRC();
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cpu_state.MM[cpu_reg].l[0] += src.l[0];
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cpu_state.MM[cpu_reg].l[1] += src.l[1];
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return 0;
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}
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static int opPADDSB_a16(uint32_t fetchdat)
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{
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MMX_REG src;
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MMX_ENTER();
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fetch_ea_16(fetchdat);
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MMX_GETSRC();
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cpu_state.MM[cpu_reg].sb[0] = SSATB(cpu_state.MM[cpu_reg].sb[0] + src.sb[0]);
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cpu_state.MM[cpu_reg].sb[1] = SSATB(cpu_state.MM[cpu_reg].sb[1] + src.sb[1]);
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cpu_state.MM[cpu_reg].sb[2] = SSATB(cpu_state.MM[cpu_reg].sb[2] + src.sb[2]);
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cpu_state.MM[cpu_reg].sb[3] = SSATB(cpu_state.MM[cpu_reg].sb[3] + src.sb[3]);
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cpu_state.MM[cpu_reg].sb[4] = SSATB(cpu_state.MM[cpu_reg].sb[4] + src.sb[4]);
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cpu_state.MM[cpu_reg].sb[5] = SSATB(cpu_state.MM[cpu_reg].sb[5] + src.sb[5]);
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cpu_state.MM[cpu_reg].sb[6] = SSATB(cpu_state.MM[cpu_reg].sb[6] + src.sb[6]);
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cpu_state.MM[cpu_reg].sb[7] = SSATB(cpu_state.MM[cpu_reg].sb[7] + src.sb[7]);
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return 0;
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}
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static int opPADDSB_a32(uint32_t fetchdat)
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{
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MMX_REG src;
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MMX_ENTER();
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fetch_ea_32(fetchdat);
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MMX_GETSRC();
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cpu_state.MM[cpu_reg].sb[0] = SSATB(cpu_state.MM[cpu_reg].sb[0] + src.sb[0]);
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cpu_state.MM[cpu_reg].sb[1] = SSATB(cpu_state.MM[cpu_reg].sb[1] + src.sb[1]);
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cpu_state.MM[cpu_reg].sb[2] = SSATB(cpu_state.MM[cpu_reg].sb[2] + src.sb[2]);
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cpu_state.MM[cpu_reg].sb[3] = SSATB(cpu_state.MM[cpu_reg].sb[3] + src.sb[3]);
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cpu_state.MM[cpu_reg].sb[4] = SSATB(cpu_state.MM[cpu_reg].sb[4] + src.sb[4]);
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cpu_state.MM[cpu_reg].sb[5] = SSATB(cpu_state.MM[cpu_reg].sb[5] + src.sb[5]);
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cpu_state.MM[cpu_reg].sb[6] = SSATB(cpu_state.MM[cpu_reg].sb[6] + src.sb[6]);
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cpu_state.MM[cpu_reg].sb[7] = SSATB(cpu_state.MM[cpu_reg].sb[7] + src.sb[7]);
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return 0;
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}
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static int opPADDUSB_a16(uint32_t fetchdat)
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{
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MMX_REG src;
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|
MMX_ENTER();
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|
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|
fetch_ea_16(fetchdat);
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|
MMX_GETSRC();
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cpu_state.MM[cpu_reg].b[0] = USATB(cpu_state.MM[cpu_reg].b[0] + src.b[0]);
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cpu_state.MM[cpu_reg].b[1] = USATB(cpu_state.MM[cpu_reg].b[1] + src.b[1]);
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cpu_state.MM[cpu_reg].b[2] = USATB(cpu_state.MM[cpu_reg].b[2] + src.b[2]);
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cpu_state.MM[cpu_reg].b[3] = USATB(cpu_state.MM[cpu_reg].b[3] + src.b[3]);
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cpu_state.MM[cpu_reg].b[4] = USATB(cpu_state.MM[cpu_reg].b[4] + src.b[4]);
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cpu_state.MM[cpu_reg].b[5] = USATB(cpu_state.MM[cpu_reg].b[5] + src.b[5]);
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cpu_state.MM[cpu_reg].b[6] = USATB(cpu_state.MM[cpu_reg].b[6] + src.b[6]);
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cpu_state.MM[cpu_reg].b[7] = USATB(cpu_state.MM[cpu_reg].b[7] + src.b[7]);
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return 0;
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}
|
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static int opPADDUSB_a32(uint32_t fetchdat)
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{
|
|
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|
|
MMX_REG src;
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MMX_ENTER();
|
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|
|
|
|
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fetch_ea_32(fetchdat);
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MMX_GETSRC();
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|
|
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|
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cpu_state.MM[cpu_reg].b[0] = USATB(cpu_state.MM[cpu_reg].b[0] + src.b[0]);
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|
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cpu_state.MM[cpu_reg].b[1] = USATB(cpu_state.MM[cpu_reg].b[1] + src.b[1]);
|
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|
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cpu_state.MM[cpu_reg].b[2] = USATB(cpu_state.MM[cpu_reg].b[2] + src.b[2]);
|
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|
|
cpu_state.MM[cpu_reg].b[3] = USATB(cpu_state.MM[cpu_reg].b[3] + src.b[3]);
|
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|
|
cpu_state.MM[cpu_reg].b[4] = USATB(cpu_state.MM[cpu_reg].b[4] + src.b[4]);
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|
cpu_state.MM[cpu_reg].b[5] = USATB(cpu_state.MM[cpu_reg].b[5] + src.b[5]);
|
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|
|
|
cpu_state.MM[cpu_reg].b[6] = USATB(cpu_state.MM[cpu_reg].b[6] + src.b[6]);
|
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|
|
|
cpu_state.MM[cpu_reg].b[7] = USATB(cpu_state.MM[cpu_reg].b[7] + src.b[7]);
|
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|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int opPADDSW_a16(uint32_t fetchdat)
|
|
|
|
|
{
|
|
|
|
|
MMX_REG src;
|
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|
|
|
MMX_ENTER();
|
|
|
|
|
|
|
|
|
|
fetch_ea_16(fetchdat);
|
|
|
|
|
MMX_GETSRC();
|
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|
|
|
|
|
|
|
|
cpu_state.MM[cpu_reg].sw[0] = SSATW(cpu_state.MM[cpu_reg].sw[0] + src.sw[0]);
|
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|
|
|
cpu_state.MM[cpu_reg].sw[1] = SSATW(cpu_state.MM[cpu_reg].sw[1] + src.sw[1]);
|
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|
|
|
cpu_state.MM[cpu_reg].sw[2] = SSATW(cpu_state.MM[cpu_reg].sw[2] + src.sw[2]);
|
|
|
|
|
cpu_state.MM[cpu_reg].sw[3] = SSATW(cpu_state.MM[cpu_reg].sw[3] + src.sw[3]);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
static int opPADDSW_a32(uint32_t fetchdat)
|
|
|
|
|
{
|
|
|
|
|
MMX_REG src;
|
|
|
|
|
MMX_ENTER();
|
|
|
|
|
|
|
|
|
|
fetch_ea_32(fetchdat);
|
|
|
|
|
MMX_GETSRC();
|
|
|
|
|
|
|
|
|
|
cpu_state.MM[cpu_reg].sw[0] = SSATW(cpu_state.MM[cpu_reg].sw[0] + src.sw[0]);
|
|
|
|
|
cpu_state.MM[cpu_reg].sw[1] = SSATW(cpu_state.MM[cpu_reg].sw[1] + src.sw[1]);
|
|
|
|
|
cpu_state.MM[cpu_reg].sw[2] = SSATW(cpu_state.MM[cpu_reg].sw[2] + src.sw[2]);
|
|
|
|
|
cpu_state.MM[cpu_reg].sw[3] = SSATW(cpu_state.MM[cpu_reg].sw[3] + src.sw[3]);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int opPADDUSW_a16(uint32_t fetchdat)
|
|
|
|
|
{
|
|
|
|
|
MMX_REG src;
|
|
|
|
|
MMX_ENTER();
|
|
|
|
|
|
|
|
|
|
fetch_ea_16(fetchdat);
|
|
|
|
|
MMX_GETSRC();
|
|
|
|
|
|
|
|
|
|
cpu_state.MM[cpu_reg].w[0] = USATW(cpu_state.MM[cpu_reg].w[0] + src.w[0]);
|
|
|
|
|
cpu_state.MM[cpu_reg].w[1] = USATW(cpu_state.MM[cpu_reg].w[1] + src.w[1]);
|
|
|
|
|
cpu_state.MM[cpu_reg].w[2] = USATW(cpu_state.MM[cpu_reg].w[2] + src.w[2]);
|
|
|
|
|
cpu_state.MM[cpu_reg].w[3] = USATW(cpu_state.MM[cpu_reg].w[3] + src.w[3]);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
static int opPADDUSW_a32(uint32_t fetchdat)
|
|
|
|
|
{
|
|
|
|
|
MMX_REG src;
|
|
|
|
|
MMX_ENTER();
|
|
|
|
|
|
|
|
|
|
fetch_ea_32(fetchdat);
|
|
|
|
|
MMX_GETSRC();
|
|
|
|
|
|
|
|
|
|
cpu_state.MM[cpu_reg].w[0] = USATW(cpu_state.MM[cpu_reg].w[0] + src.w[0]);
|
|
|
|
|
cpu_state.MM[cpu_reg].w[1] = USATW(cpu_state.MM[cpu_reg].w[1] + src.w[1]);
|
|
|
|
|
cpu_state.MM[cpu_reg].w[2] = USATW(cpu_state.MM[cpu_reg].w[2] + src.w[2]);
|
|
|
|
|
cpu_state.MM[cpu_reg].w[3] = USATW(cpu_state.MM[cpu_reg].w[3] + src.w[3]);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int opPMADDWD_a16(uint32_t fetchdat)
|
|
|
|
|
{
|
|
|
|
|
MMX_REG src;
|
|
|
|
|
MMX_ENTER();
|
|
|
|
|
|
|
|
|
|
fetch_ea_16(fetchdat);
|
|
|
|
|
MMX_GETSRC();
|
|
|
|
|
|
|
|
|
|
if (cpu_state.MM[cpu_reg].l[0] == 0x80008000 && src.l[0] == 0x80008000)
|
|
|
|
|
cpu_state.MM[cpu_reg].l[0] = 0x80000000;
|
|
|
|
|
else
|
|
|
|
|
cpu_state.MM[cpu_reg].sl[0] = ((int32_t)cpu_state.MM[cpu_reg].sw[0] * (int32_t)src.sw[0]) + ((int32_t)cpu_state.MM[cpu_reg].sw[1] * (int32_t)src.sw[1]);
|
|
|
|
|
|
|
|
|
|
if (cpu_state.MM[cpu_reg].l[1] == 0x80008000 && src.l[1] == 0x80008000)
|
|
|
|
|
cpu_state.MM[cpu_reg].l[1] = 0x80000000;
|
|
|
|
|
else
|
|
|
|
|
cpu_state.MM[cpu_reg].sl[1] = ((int32_t)cpu_state.MM[cpu_reg].sw[2] * (int32_t)src.sw[2]) + ((int32_t)cpu_state.MM[cpu_reg].sw[3] * (int32_t)src.sw[3]);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
static int opPMADDWD_a32(uint32_t fetchdat)
|
|
|
|
|
{
|
|
|
|
|
MMX_REG src;
|
|
|
|
|
MMX_ENTER();
|
|
|
|
|
|
|
|
|
|
fetch_ea_32(fetchdat);
|
|
|
|
|
MMX_GETSRC();
|
|
|
|
|
|
|
|
|
|
if (cpu_state.MM[cpu_reg].l[0] == 0x80008000 && src.l[0] == 0x80008000)
|
|
|
|
|
cpu_state.MM[cpu_reg].l[0] = 0x80000000;
|
|
|
|
|
else
|
|
|
|
|
cpu_state.MM[cpu_reg].sl[0] = ((int32_t)cpu_state.MM[cpu_reg].sw[0] * (int32_t)src.sw[0]) + ((int32_t)cpu_state.MM[cpu_reg].sw[1] * (int32_t)src.sw[1]);
|
|
|
|
|
|
|
|
|
|
if (cpu_state.MM[cpu_reg].l[1] == 0x80008000 && src.l[1] == 0x80008000)
|
|
|
|
|
cpu_state.MM[cpu_reg].l[1] = 0x80000000;
|
|
|
|
|
else
|
|
|
|
|
cpu_state.MM[cpu_reg].sl[1] = ((int32_t)cpu_state.MM[cpu_reg].sw[2] * (int32_t)src.sw[2]) + ((int32_t)cpu_state.MM[cpu_reg].sw[3] * (int32_t)src.sw[3]);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static int opPMULLW_a16(uint32_t fetchdat)
|
|
|
|
|
{
|
|
|
|
|
MMX_ENTER();
|
|
|
|
|
|
|
|
|
|
fetch_ea_16(fetchdat);
|
|
|
|
|
if (cpu_mod == 3)
|
|
|
|
|
{
|
|
|
|
|
cpu_state.MM[cpu_reg].w[0] *= cpu_state.MM[cpu_rm].w[0];
|
|
|
|
|
cpu_state.MM[cpu_reg].w[1] *= cpu_state.MM[cpu_rm].w[1];
|
|
|
|
|
cpu_state.MM[cpu_reg].w[2] *= cpu_state.MM[cpu_rm].w[2];
|
|
|
|
|
cpu_state.MM[cpu_reg].w[3] *= cpu_state.MM[cpu_rm].w[3];
|
|
|
|
|
CLOCK_CYCLES(1);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
MMX_REG src;
|
|
|
|
|
|
|
|
|
|
SEG_CHECK_READ(cpu_state.ea_seg);
|
|
|
|
|
src.l[0] = readmeml(easeg, cpu_state.eaaddr);
|
|
|
|
|
src.l[1] = readmeml(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 0;
|
|
|
|
|
cpu_state.MM[cpu_reg].w[0] *= src.w[0];
|
|
|
|
|
cpu_state.MM[cpu_reg].w[1] *= src.w[1];
|
|
|
|
|
cpu_state.MM[cpu_reg].w[2] *= src.w[2];
|
|
|
|
|
cpu_state.MM[cpu_reg].w[3] *= src.w[3];
|
|
|
|
|
CLOCK_CYCLES(2);
|
|
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
static int opPMULLW_a32(uint32_t fetchdat)
|
|
|
|
|
{
|
|
|
|
|
MMX_ENTER();
|
|
|
|
|
|
|
|
|
|
fetch_ea_32(fetchdat);
|
|
|
|
|
if (cpu_mod == 3)
|
|
|
|
|
{
|
|
|
|
|
cpu_state.MM[cpu_reg].w[0] *= cpu_state.MM[cpu_rm].w[0];
|
|
|
|
|
cpu_state.MM[cpu_reg].w[1] *= cpu_state.MM[cpu_rm].w[1];
|
|
|
|
|
cpu_state.MM[cpu_reg].w[2] *= cpu_state.MM[cpu_rm].w[2];
|
|
|
|
|
cpu_state.MM[cpu_reg].w[3] *= cpu_state.MM[cpu_rm].w[3];
|
|
|
|
|
CLOCK_CYCLES(1);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
MMX_REG src;
|
|
|
|
|
|
|
|
|
|
SEG_CHECK_READ(cpu_state.ea_seg);
|
|
|
|
|
src.l[0] = readmeml(easeg, cpu_state.eaaddr);
|
|
|
|
|
src.l[1] = readmeml(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 0;
|
|
|
|
|
cpu_state.MM[cpu_reg].w[0] *= src.w[0];
|
|
|
|
|
cpu_state.MM[cpu_reg].w[1] *= src.w[1];
|
|
|
|
|
cpu_state.MM[cpu_reg].w[2] *= src.w[2];
|
|
|
|
|
cpu_state.MM[cpu_reg].w[3] *= src.w[3];
|
|
|
|
|
CLOCK_CYCLES(2);
|
|
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int opPMULHW_a16(uint32_t fetchdat)
|
|
|
|
|
{
|
|
|
|
|
MMX_ENTER();
|
|
|
|
|
|
|
|
|
|
fetch_ea_16(fetchdat);
|
|
|
|
|
if (cpu_mod == 3)
|
|
|
|
|
{
|
|
|
|
|
cpu_state.MM[cpu_reg].w[0] = ((int32_t)cpu_state.MM[cpu_reg].sw[0] * (int32_t)cpu_state.MM[cpu_rm].sw[0]) >> 16;
|
|
|
|
|
cpu_state.MM[cpu_reg].w[1] = ((int32_t)cpu_state.MM[cpu_reg].sw[1] * (int32_t)cpu_state.MM[cpu_rm].sw[1]) >> 16;
|
|
|
|
|
cpu_state.MM[cpu_reg].w[2] = ((int32_t)cpu_state.MM[cpu_reg].sw[2] * (int32_t)cpu_state.MM[cpu_rm].sw[2]) >> 16;
|
|
|
|
|
cpu_state.MM[cpu_reg].w[3] = ((int32_t)cpu_state.MM[cpu_reg].sw[3] * (int32_t)cpu_state.MM[cpu_rm].sw[3]) >> 16;
|
|
|
|
|
CLOCK_CYCLES(1);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
MMX_REG src;
|
|
|
|
|
|
|
|
|
|
SEG_CHECK_READ(cpu_state.ea_seg);
|
|
|
|
|
src.l[0] = readmeml(easeg, cpu_state.eaaddr);
|
|
|
|
|
src.l[1] = readmeml(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 0;
|
|
|
|
|
cpu_state.MM[cpu_reg].w[0] = ((int32_t)cpu_state.MM[cpu_reg].sw[0] * (int32_t)src.sw[0]) >> 16;
|
|
|
|
|
cpu_state.MM[cpu_reg].w[1] = ((int32_t)cpu_state.MM[cpu_reg].sw[1] * (int32_t)src.sw[1]) >> 16;
|
|
|
|
|
cpu_state.MM[cpu_reg].w[2] = ((int32_t)cpu_state.MM[cpu_reg].sw[2] * (int32_t)src.sw[2]) >> 16;
|
|
|
|
|
cpu_state.MM[cpu_reg].w[3] = ((int32_t)cpu_state.MM[cpu_reg].sw[3] * (int32_t)src.sw[3]) >> 16;
|
|
|
|
|
CLOCK_CYCLES(2);
|
|
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
static int opPMULHW_a32(uint32_t fetchdat)
|
|
|
|
|
{
|
|
|
|
|
MMX_ENTER();
|
|
|
|
|
|
|
|
|
|
fetch_ea_32(fetchdat);
|
|
|
|
|
if (cpu_mod == 3)
|
|
|
|
|
{
|
|
|
|
|
cpu_state.MM[cpu_reg].w[0] = ((int32_t)cpu_state.MM[cpu_reg].sw[0] * (int32_t)cpu_state.MM[cpu_rm].sw[0]) >> 16;
|
|
|
|
|
cpu_state.MM[cpu_reg].w[1] = ((int32_t)cpu_state.MM[cpu_reg].sw[1] * (int32_t)cpu_state.MM[cpu_rm].sw[1]) >> 16;
|
|
|
|
|
cpu_state.MM[cpu_reg].w[2] = ((int32_t)cpu_state.MM[cpu_reg].sw[2] * (int32_t)cpu_state.MM[cpu_rm].sw[2]) >> 16;
|
|
|
|
|
cpu_state.MM[cpu_reg].w[3] = ((int32_t)cpu_state.MM[cpu_reg].sw[3] * (int32_t)cpu_state.MM[cpu_rm].sw[3]) >> 16;
|
|
|
|
|
CLOCK_CYCLES(1);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
MMX_REG src;
|
|
|
|
|
|
|
|
|
|
SEG_CHECK_READ(cpu_state.ea_seg);
|
|
|
|
|
src.l[0] = readmeml(easeg, cpu_state.eaaddr);
|
|
|
|
|
src.l[1] = readmeml(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 0;
|
|
|
|
|
cpu_state.MM[cpu_reg].w[0] = ((int32_t)cpu_state.MM[cpu_reg].sw[0] * (int32_t)src.sw[0]) >> 16;
|
|
|
|
|
cpu_state.MM[cpu_reg].w[1] = ((int32_t)cpu_state.MM[cpu_reg].sw[1] * (int32_t)src.sw[1]) >> 16;
|
|
|
|
|
cpu_state.MM[cpu_reg].w[2] = ((int32_t)cpu_state.MM[cpu_reg].sw[2] * (int32_t)src.sw[2]) >> 16;
|
|
|
|
|
cpu_state.MM[cpu_reg].w[3] = ((int32_t)cpu_state.MM[cpu_reg].sw[3] * (int32_t)src.sw[3]) >> 16;
|
|
|
|
|
CLOCK_CYCLES(2);
|
|
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int opPSUBB_a16(uint32_t fetchdat)
|
|
|
|
|
{
|
|
|
|
|
MMX_REG src;
|
|
|
|
|
MMX_ENTER();
|
|
|
|
|
|
|
|
|
|
fetch_ea_16(fetchdat);
|
|
|
|
|
MMX_GETSRC();
|
|
|
|
|
|
|
|
|
|
cpu_state.MM[cpu_reg].b[0] -= src.b[0];
|
|
|
|
|
cpu_state.MM[cpu_reg].b[1] -= src.b[1];
|
|
|
|
|
cpu_state.MM[cpu_reg].b[2] -= src.b[2];
|
|
|
|
|
cpu_state.MM[cpu_reg].b[3] -= src.b[3];
|
|
|
|
|
cpu_state.MM[cpu_reg].b[4] -= src.b[4];
|
|
|
|
|
cpu_state.MM[cpu_reg].b[5] -= src.b[5];
|
|
|
|
|
cpu_state.MM[cpu_reg].b[6] -= src.b[6];
|
|
|
|
|
cpu_state.MM[cpu_reg].b[7] -= src.b[7];
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
static int opPSUBB_a32(uint32_t fetchdat)
|
|
|
|
|
{
|
|
|
|
|
MMX_REG src;
|
|
|
|
|
MMX_ENTER();
|
|
|
|
|
|
|
|
|
|
fetch_ea_32(fetchdat);
|
|
|
|
|
MMX_GETSRC();
|
|
|
|
|
|
|
|
|
|
cpu_state.MM[cpu_reg].b[0] -= src.b[0];
|
|
|
|
|
cpu_state.MM[cpu_reg].b[1] -= src.b[1];
|
|
|
|
|
cpu_state.MM[cpu_reg].b[2] -= src.b[2];
|
|
|
|
|
cpu_state.MM[cpu_reg].b[3] -= src.b[3];
|
|
|
|
|
cpu_state.MM[cpu_reg].b[4] -= src.b[4];
|
|
|
|
|
cpu_state.MM[cpu_reg].b[5] -= src.b[5];
|
|
|
|
|
cpu_state.MM[cpu_reg].b[6] -= src.b[6];
|
|
|
|
|
cpu_state.MM[cpu_reg].b[7] -= src.b[7];
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int opPSUBW_a16(uint32_t fetchdat)
|
|
|
|
|
{
|
|
|
|
|
MMX_REG src;
|
|
|
|
|
MMX_ENTER();
|
|
|
|
|
|
|
|
|
|
fetch_ea_16(fetchdat);
|
|
|
|
|
MMX_GETSRC();
|
|
|
|
|
|
|
|
|
|
cpu_state.MM[cpu_reg].w[0] -= src.w[0];
|
|
|
|
|
cpu_state.MM[cpu_reg].w[1] -= src.w[1];
|
|
|
|
|
cpu_state.MM[cpu_reg].w[2] -= src.w[2];
|
|
|
|
|
cpu_state.MM[cpu_reg].w[3] -= src.w[3];
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
static int opPSUBW_a32(uint32_t fetchdat)
|
|
|
|
|
{
|
|
|
|
|
MMX_REG src;
|
|
|
|
|
MMX_ENTER();
|
|
|
|
|
|
|
|
|
|
fetch_ea_32(fetchdat);
|
|
|
|
|
MMX_GETSRC();
|
|
|
|
|
|
|
|
|
|
cpu_state.MM[cpu_reg].w[0] -= src.w[0];
|
|
|
|
|
cpu_state.MM[cpu_reg].w[1] -= src.w[1];
|
|
|
|
|
cpu_state.MM[cpu_reg].w[2] -= src.w[2];
|
|
|
|
|
cpu_state.MM[cpu_reg].w[3] -= src.w[3];
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int opPSUBD_a16(uint32_t fetchdat)
|
|
|
|
|
{
|
|
|
|
|
MMX_REG src;
|
|
|
|
|
MMX_ENTER();
|
|
|
|
|
|
|
|
|
|
fetch_ea_16(fetchdat);
|
|
|
|
|
MMX_GETSRC();
|
|
|
|
|
|
|
|
|
|
cpu_state.MM[cpu_reg].l[0] -= src.l[0];
|
|
|
|
|
cpu_state.MM[cpu_reg].l[1] -= src.l[1];
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
static int opPSUBD_a32(uint32_t fetchdat)
|
|
|
|
|
{
|
|
|
|
|
MMX_REG src;
|
|
|
|
|
MMX_ENTER();
|
|
|
|
|
|
|
|
|
|
fetch_ea_32(fetchdat);
|
|
|
|
|
MMX_GETSRC();
|
|
|
|
|
|
|
|
|
|
cpu_state.MM[cpu_reg].l[0] -= src.l[0];
|
|
|
|
|
cpu_state.MM[cpu_reg].l[1] -= src.l[1];
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int opPSUBSB_a16(uint32_t fetchdat)
|
|
|
|
|
{
|
|
|
|
|
MMX_REG src;
|
2020-04-10 01:08:52 +02:00
|
|
|
pclog("opPSUBSB_a16(%08X)\n", fetchdat);
|
Added the IBM 5161 ISA expansion for PC and XT;
Cleaned up the parallel port emulation, added IRQ support, and made enabling/disabling per port;
Added the Award 430NX and the Intel Classic/PCI (Alfredo, 420TX);
Finished the 586MC1;
Added 8087 emulation;
Moved Cyrix 6x86'es to the Dev branch;
Sanitized/cleaned up memregs.c/h and intel.c/h;
Split the chipsets from machines and sanitized Port 92 emulation;
Added support for the 15bpp mode to the Compaq ATI 28800;
Moved the MR 386DX and 486 machines to the Dev branch;
Ported the new dynamic recompiler from PCem, but it remains in Dev branch until after v2.00;
Ported the new timer code from PCem;
Cleaned up the CPU table of unused stuff and better optimized its structure;
Ported the Open-XT and Open-AT from VARCem, the Open-AT is in the Dev branch;
Ported the XT MFM controller rewrite and adding of more controllers (incl. two RLL ones), from VARCem;
Added the AHA-1540A and the BusTek BT-542B;
Moved the Sumo SCSI-AT to the Dev branch;
Minor IDE, FDC, and floppy drive code clean-ups;
Made NCR 5380/53C400-based cards' BIOS address configurable;
Got rid of the legacy romset variable;
Unified (video) buffer and buffer32 into one and make the unified buffer 32-bit;
Added the Amstead PPC512 per PCem patch by John Elliott;
Switched memory mapping granularity from 16k to 4k (less than 1k not possible due to internal pages);
Rewrote the CL-GD 54xx blitter, fixes Win-OS/2 on the 54x6 among other thing;
Added the Image Manager 1024 and Professional Graphics Controller per PCem patch by John Elliott and work done on VARCem;
Added Headland HT-216, GC-205 and Video 7 VGA 1024i emulation based on PCem commit;
Implemented the fuction keys for the Toshiba T1000/T1200/T3100 enhancement;
Amstrad MegaPC does now works correctly with non-internal graphics card;
The SLiRP code no longer casts a packed struct type to a non-packed struct type;
The Xi8088 and PB410a no longer hang on 86Box when PS/2 mouse is not present;
The S3 Virge on BeOS is no longer broken (was broken by build #1591);
OS/2 2.0 build 6.167 now sees key presses again;
Xi8088 now work on CGA again;
86F images converted from either the old or new variants of the HxC MFM format now work correctly;
Hardware interrupts with a vector of 0xFF are now handled correctly;
OPTi 495SX boards no longer incorrectly have 64 MB maximum RAM when 32 MB is correct;
Fixed VNC keyboard input bugs;
Fixed AT RTC periodic interrupt - Chicago 58s / 73f / 73g / 81 MIDI play no longer hangs with the build's own VTD driver;
Fixed mouse polling with internal mice - Amstrad and Olivetti mice now work correctly;
Triones ATAPI DMA driver now correctly reads a file at the end of a CD image with a sectors number not divisible by 4;
Compaq Portable now works with all graphics cards;
Fixed various MDSI Genius bugs;
Added segment limit checks and improved page fault checks for several CPU instructions - Memphis 15xx WINSETUP and Chicago 58s WINDISK.CPL no longer issue a GPF, and some S3 drivers that used to have glitches, now work correctly;
Further improved the 808x emulation, also fixes the noticably choppy sound when using 808x CPU's, also fixes #355;
OS/2 installer no logner locks up on splash screen on PS/2 Model 70 and 80, fixes #400.
Fixed several Amstead bugs, GEM no longer crashes on the Amstrad 1640, fixes #391.
Ported John Elliott's Amstrad fixes and improvement from PCem, and fixed the default language so it's correctly Engliish, fixes #278, fixes #389.
Fixed a minor IDE timing bug, fixes #388.
Fixed Toshiba T1000 RAM issues, fixes #379.
Fixed EGA/(S)VGA overscan border handling, fixes #378;
Got rid of the now long useless IDE channel 2 auto-removal, fixes #370;
Fixed the BIOS files used by the AMSTRAD PC1512, fixes #366;
Ported the Unicode CD image file name fix from VARCem, fixes #365;
Fixed high density floppy disks on the Xi8088, fixes #359;
Fixed some bugs in the Hercules emulation, fixes #346, fixes #358;
Fixed the SCSI hard disk mode sense pages, fixes #356;
Removed the AMI Unknown 386SX because of impossibility to identify the chipset, closes #349;
Fixed bugs in the serial mouse emulation, fixes #344;
Compiled 86Box binaries now include all the required .DLL's, fixes #341;
Made some combo boxes in the Settings dialog slightly wider, fixes #276.
2019-09-20 14:02:30 +02:00
|
|
|
MMX_ENTER();
|
|
|
|
|
|
|
|
|
|
fetch_ea_16(fetchdat);
|
|
|
|
|
MMX_GETSRC();
|
|
|
|
|
|
|
|
|
|
cpu_state.MM[cpu_reg].sb[0] = SSATB(cpu_state.MM[cpu_reg].sb[0] - src.sb[0]);
|
|
|
|
|
cpu_state.MM[cpu_reg].sb[1] = SSATB(cpu_state.MM[cpu_reg].sb[1] - src.sb[1]);
|
|
|
|
|
cpu_state.MM[cpu_reg].sb[2] = SSATB(cpu_state.MM[cpu_reg].sb[2] - src.sb[2]);
|
|
|
|
|
cpu_state.MM[cpu_reg].sb[3] = SSATB(cpu_state.MM[cpu_reg].sb[3] - src.sb[3]);
|
|
|
|
|
cpu_state.MM[cpu_reg].sb[4] = SSATB(cpu_state.MM[cpu_reg].sb[4] - src.sb[4]);
|
|
|
|
|
cpu_state.MM[cpu_reg].sb[5] = SSATB(cpu_state.MM[cpu_reg].sb[5] - src.sb[5]);
|
|
|
|
|
cpu_state.MM[cpu_reg].sb[6] = SSATB(cpu_state.MM[cpu_reg].sb[6] - src.sb[6]);
|
|
|
|
|
cpu_state.MM[cpu_reg].sb[7] = SSATB(cpu_state.MM[cpu_reg].sb[7] - src.sb[7]);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
static int opPSUBSB_a32(uint32_t fetchdat)
|
|
|
|
|
{
|
|
|
|
|
MMX_REG src;
|
2020-04-10 01:08:52 +02:00
|
|
|
pclog("opPSUBSB_a32(%08X)\n", fetchdat);
|
Added the IBM 5161 ISA expansion for PC and XT;
Cleaned up the parallel port emulation, added IRQ support, and made enabling/disabling per port;
Added the Award 430NX and the Intel Classic/PCI (Alfredo, 420TX);
Finished the 586MC1;
Added 8087 emulation;
Moved Cyrix 6x86'es to the Dev branch;
Sanitized/cleaned up memregs.c/h and intel.c/h;
Split the chipsets from machines and sanitized Port 92 emulation;
Added support for the 15bpp mode to the Compaq ATI 28800;
Moved the MR 386DX and 486 machines to the Dev branch;
Ported the new dynamic recompiler from PCem, but it remains in Dev branch until after v2.00;
Ported the new timer code from PCem;
Cleaned up the CPU table of unused stuff and better optimized its structure;
Ported the Open-XT and Open-AT from VARCem, the Open-AT is in the Dev branch;
Ported the XT MFM controller rewrite and adding of more controllers (incl. two RLL ones), from VARCem;
Added the AHA-1540A and the BusTek BT-542B;
Moved the Sumo SCSI-AT to the Dev branch;
Minor IDE, FDC, and floppy drive code clean-ups;
Made NCR 5380/53C400-based cards' BIOS address configurable;
Got rid of the legacy romset variable;
Unified (video) buffer and buffer32 into one and make the unified buffer 32-bit;
Added the Amstead PPC512 per PCem patch by John Elliott;
Switched memory mapping granularity from 16k to 4k (less than 1k not possible due to internal pages);
Rewrote the CL-GD 54xx blitter, fixes Win-OS/2 on the 54x6 among other thing;
Added the Image Manager 1024 and Professional Graphics Controller per PCem patch by John Elliott and work done on VARCem;
Added Headland HT-216, GC-205 and Video 7 VGA 1024i emulation based on PCem commit;
Implemented the fuction keys for the Toshiba T1000/T1200/T3100 enhancement;
Amstrad MegaPC does now works correctly with non-internal graphics card;
The SLiRP code no longer casts a packed struct type to a non-packed struct type;
The Xi8088 and PB410a no longer hang on 86Box when PS/2 mouse is not present;
The S3 Virge on BeOS is no longer broken (was broken by build #1591);
OS/2 2.0 build 6.167 now sees key presses again;
Xi8088 now work on CGA again;
86F images converted from either the old or new variants of the HxC MFM format now work correctly;
Hardware interrupts with a vector of 0xFF are now handled correctly;
OPTi 495SX boards no longer incorrectly have 64 MB maximum RAM when 32 MB is correct;
Fixed VNC keyboard input bugs;
Fixed AT RTC periodic interrupt - Chicago 58s / 73f / 73g / 81 MIDI play no longer hangs with the build's own VTD driver;
Fixed mouse polling with internal mice - Amstrad and Olivetti mice now work correctly;
Triones ATAPI DMA driver now correctly reads a file at the end of a CD image with a sectors number not divisible by 4;
Compaq Portable now works with all graphics cards;
Fixed various MDSI Genius bugs;
Added segment limit checks and improved page fault checks for several CPU instructions - Memphis 15xx WINSETUP and Chicago 58s WINDISK.CPL no longer issue a GPF, and some S3 drivers that used to have glitches, now work correctly;
Further improved the 808x emulation, also fixes the noticably choppy sound when using 808x CPU's, also fixes #355;
OS/2 installer no logner locks up on splash screen on PS/2 Model 70 and 80, fixes #400.
Fixed several Amstead bugs, GEM no longer crashes on the Amstrad 1640, fixes #391.
Ported John Elliott's Amstrad fixes and improvement from PCem, and fixed the default language so it's correctly Engliish, fixes #278, fixes #389.
Fixed a minor IDE timing bug, fixes #388.
Fixed Toshiba T1000 RAM issues, fixes #379.
Fixed EGA/(S)VGA overscan border handling, fixes #378;
Got rid of the now long useless IDE channel 2 auto-removal, fixes #370;
Fixed the BIOS files used by the AMSTRAD PC1512, fixes #366;
Ported the Unicode CD image file name fix from VARCem, fixes #365;
Fixed high density floppy disks on the Xi8088, fixes #359;
Fixed some bugs in the Hercules emulation, fixes #346, fixes #358;
Fixed the SCSI hard disk mode sense pages, fixes #356;
Removed the AMI Unknown 386SX because of impossibility to identify the chipset, closes #349;
Fixed bugs in the serial mouse emulation, fixes #344;
Compiled 86Box binaries now include all the required .DLL's, fixes #341;
Made some combo boxes in the Settings dialog slightly wider, fixes #276.
2019-09-20 14:02:30 +02:00
|
|
|
MMX_ENTER();
|
|
|
|
|
|
|
|
|
|
fetch_ea_32(fetchdat);
|
|
|
|
|
MMX_GETSRC();
|
|
|
|
|
|
|
|
|
|
cpu_state.MM[cpu_reg].sb[0] = SSATB(cpu_state.MM[cpu_reg].sb[0] - src.sb[0]);
|
|
|
|
|
cpu_state.MM[cpu_reg].sb[1] = SSATB(cpu_state.MM[cpu_reg].sb[1] - src.sb[1]);
|
|
|
|
|
cpu_state.MM[cpu_reg].sb[2] = SSATB(cpu_state.MM[cpu_reg].sb[2] - src.sb[2]);
|
|
|
|
|
cpu_state.MM[cpu_reg].sb[3] = SSATB(cpu_state.MM[cpu_reg].sb[3] - src.sb[3]);
|
|
|
|
|
cpu_state.MM[cpu_reg].sb[4] = SSATB(cpu_state.MM[cpu_reg].sb[4] - src.sb[4]);
|
|
|
|
|
cpu_state.MM[cpu_reg].sb[5] = SSATB(cpu_state.MM[cpu_reg].sb[5] - src.sb[5]);
|
|
|
|
|
cpu_state.MM[cpu_reg].sb[6] = SSATB(cpu_state.MM[cpu_reg].sb[6] - src.sb[6]);
|
|
|
|
|
cpu_state.MM[cpu_reg].sb[7] = SSATB(cpu_state.MM[cpu_reg].sb[7] - src.sb[7]);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int opPSUBUSB_a16(uint32_t fetchdat)
|
|
|
|
|
{
|
|
|
|
|
MMX_REG src;
|
|
|
|
|
MMX_ENTER();
|
|
|
|
|
|
|
|
|
|
fetch_ea_16(fetchdat);
|
|
|
|
|
MMX_GETSRC();
|
|
|
|
|
|
|
|
|
|
cpu_state.MM[cpu_reg].b[0] = USATB(cpu_state.MM[cpu_reg].b[0] - src.b[0]);
|
|
|
|
|
cpu_state.MM[cpu_reg].b[1] = USATB(cpu_state.MM[cpu_reg].b[1] - src.b[1]);
|
|
|
|
|
cpu_state.MM[cpu_reg].b[2] = USATB(cpu_state.MM[cpu_reg].b[2] - src.b[2]);
|
|
|
|
|
cpu_state.MM[cpu_reg].b[3] = USATB(cpu_state.MM[cpu_reg].b[3] - src.b[3]);
|
|
|
|
|
cpu_state.MM[cpu_reg].b[4] = USATB(cpu_state.MM[cpu_reg].b[4] - src.b[4]);
|
|
|
|
|
cpu_state.MM[cpu_reg].b[5] = USATB(cpu_state.MM[cpu_reg].b[5] - src.b[5]);
|
|
|
|
|
cpu_state.MM[cpu_reg].b[6] = USATB(cpu_state.MM[cpu_reg].b[6] - src.b[6]);
|
|
|
|
|
cpu_state.MM[cpu_reg].b[7] = USATB(cpu_state.MM[cpu_reg].b[7] - src.b[7]);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
static int opPSUBUSB_a32(uint32_t fetchdat)
|
|
|
|
|
{
|
|
|
|
|
MMX_REG src;
|
|
|
|
|
MMX_ENTER();
|
|
|
|
|
|
|
|
|
|
fetch_ea_32(fetchdat);
|
|
|
|
|
MMX_GETSRC();
|
|
|
|
|
|
|
|
|
|
cpu_state.MM[cpu_reg].b[0] = USATB(cpu_state.MM[cpu_reg].b[0] - src.b[0]);
|
|
|
|
|
cpu_state.MM[cpu_reg].b[1] = USATB(cpu_state.MM[cpu_reg].b[1] - src.b[1]);
|
|
|
|
|
cpu_state.MM[cpu_reg].b[2] = USATB(cpu_state.MM[cpu_reg].b[2] - src.b[2]);
|
|
|
|
|
cpu_state.MM[cpu_reg].b[3] = USATB(cpu_state.MM[cpu_reg].b[3] - src.b[3]);
|
|
|
|
|
cpu_state.MM[cpu_reg].b[4] = USATB(cpu_state.MM[cpu_reg].b[4] - src.b[4]);
|
|
|
|
|
cpu_state.MM[cpu_reg].b[5] = USATB(cpu_state.MM[cpu_reg].b[5] - src.b[5]);
|
|
|
|
|
cpu_state.MM[cpu_reg].b[6] = USATB(cpu_state.MM[cpu_reg].b[6] - src.b[6]);
|
|
|
|
|
cpu_state.MM[cpu_reg].b[7] = USATB(cpu_state.MM[cpu_reg].b[7] - src.b[7]);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int opPSUBSW_a16(uint32_t fetchdat)
|
|
|
|
|
{
|
|
|
|
|
MMX_REG src;
|
|
|
|
|
MMX_ENTER();
|
|
|
|
|
|
|
|
|
|
fetch_ea_16(fetchdat);
|
|
|
|
|
MMX_GETSRC();
|
|
|
|
|
|
|
|
|
|
cpu_state.MM[cpu_reg].sw[0] = SSATW(cpu_state.MM[cpu_reg].sw[0] - src.sw[0]);
|
|
|
|
|
cpu_state.MM[cpu_reg].sw[1] = SSATW(cpu_state.MM[cpu_reg].sw[1] - src.sw[1]);
|
|
|
|
|
cpu_state.MM[cpu_reg].sw[2] = SSATW(cpu_state.MM[cpu_reg].sw[2] - src.sw[2]);
|
|
|
|
|
cpu_state.MM[cpu_reg].sw[3] = SSATW(cpu_state.MM[cpu_reg].sw[3] - src.sw[3]);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
static int opPSUBSW_a32(uint32_t fetchdat)
|
|
|
|
|
{
|
|
|
|
|
MMX_REG src;
|
|
|
|
|
MMX_ENTER();
|
|
|
|
|
|
|
|
|
|
fetch_ea_32(fetchdat);
|
|
|
|
|
MMX_GETSRC();
|
|
|
|
|
|
|
|
|
|
cpu_state.MM[cpu_reg].sw[0] = SSATW(cpu_state.MM[cpu_reg].sw[0] - src.sw[0]);
|
|
|
|
|
cpu_state.MM[cpu_reg].sw[1] = SSATW(cpu_state.MM[cpu_reg].sw[1] - src.sw[1]);
|
|
|
|
|
cpu_state.MM[cpu_reg].sw[2] = SSATW(cpu_state.MM[cpu_reg].sw[2] - src.sw[2]);
|
|
|
|
|
cpu_state.MM[cpu_reg].sw[3] = SSATW(cpu_state.MM[cpu_reg].sw[3] - src.sw[3]);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int opPSUBUSW_a16(uint32_t fetchdat)
|
|
|
|
|
{
|
|
|
|
|
MMX_REG src;
|
|
|
|
|
MMX_ENTER();
|
|
|
|
|
|
|
|
|
|
fetch_ea_16(fetchdat);
|
|
|
|
|
MMX_GETSRC();
|
|
|
|
|
|
|
|
|
|
cpu_state.MM[cpu_reg].w[0] = USATW(cpu_state.MM[cpu_reg].w[0] - src.w[0]);
|
|
|
|
|
cpu_state.MM[cpu_reg].w[1] = USATW(cpu_state.MM[cpu_reg].w[1] - src.w[1]);
|
|
|
|
|
cpu_state.MM[cpu_reg].w[2] = USATW(cpu_state.MM[cpu_reg].w[2] - src.w[2]);
|
|
|
|
|
cpu_state.MM[cpu_reg].w[3] = USATW(cpu_state.MM[cpu_reg].w[3] - src.w[3]);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
static int opPSUBUSW_a32(uint32_t fetchdat)
|
|
|
|
|
{
|
|
|
|
|
MMX_REG src;
|
|
|
|
|
MMX_ENTER();
|
|
|
|
|
|
|
|
|
|
fetch_ea_32(fetchdat);
|
|
|
|
|
MMX_GETSRC();
|
|
|
|
|
|
|
|
|
|
cpu_state.MM[cpu_reg].w[0] = USATW(cpu_state.MM[cpu_reg].w[0] - src.w[0]);
|
|
|
|
|
cpu_state.MM[cpu_reg].w[1] = USATW(cpu_state.MM[cpu_reg].w[1] - src.w[1]);
|
|
|
|
|
cpu_state.MM[cpu_reg].w[2] = USATW(cpu_state.MM[cpu_reg].w[2] - src.w[2]);
|
|
|
|
|
cpu_state.MM[cpu_reg].w[3] = USATW(cpu_state.MM[cpu_reg].w[3] - src.w[3]);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|