185 lines
4.1 KiB
C
185 lines
4.1 KiB
C
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/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the OPTi 82C802G/82C895 chipset.
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*
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*
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* Note: The shadowing of the chipset is enough to get the current machine
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* to work. Getting anything other to work will require excessive amount
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* of rewrites and improvements. Also, considering the similarities with the
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* 82C495XLC & 82C802G it can be merged with opti495.c and also get 82C802G
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* implemented.
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*
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* Copyright 2020 Tiseno100.
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/keyboard.h>
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#include <86box/mem.h>
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#include <86box/fdd.h>
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#include <86box/fdc.h>
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#include <86box/port_92.h>
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#include <86box/chipset.h>
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typedef struct
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{
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uint8_t idx,
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regs[256],
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scratch[2];
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} opti895_t;
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static void
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opti895_recalc(opti895_t *dev)
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{
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uint32_t base;
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uint32_t i, shflags = 0;
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shadowbios = 0;
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shadowbios_write = 0;
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for (i = 0; i < 8; i++) {
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if(dev->regs[0x22] & (i << 8) && (i==7)){
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shadowbios = 1;
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shadowbios_write = 1;
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mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
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}
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else if(!(dev->regs[0x22] & (i << 8)) && (i==7)) {
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shadowbios = 0;
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shadowbios_write = 0;
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mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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}
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/*
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We'll ignore it for now
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base = 0xc0000 + (i << 14);
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if (dev->regs[0x26] & (1 << i) && (i<=3)) {
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shflags = (dev->regs[0x26] & 0x20) ? (MEM_READ_INTERNAL | MEM_WRITE_DISABLED) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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mem_set_mem_state(base, 0x4000, shflags);
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} else mem_set_mem_state(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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*/
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base = 0xd0000 + (i << 14);
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if (dev->regs[0x23] & (1 << i)) {
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if(base < 0xe0000)
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shflags = (dev->regs[0x22] & 0x10) ? (MEM_READ_INTERNAL | MEM_WRITE_DISABLED) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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else
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shflags = (dev->regs[0x22] & 0x08) ? (MEM_READ_INTERNAL | MEM_WRITE_DISABLED) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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mem_set_mem_state(base, 0x4000, shflags);
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} else mem_set_mem_state(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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}
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flushmmucache();
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}
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static void
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opti895_write(uint16_t addr, uint8_t val, void *priv)
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{
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opti895_t *dev = (opti895_t *) priv;
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switch (addr) {
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case 0x22:
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dev->idx = val;
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break;
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case 0x24:
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dev->regs[dev->idx] = val;
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pclog("dev->regs[%04x] = %08x\n", dev->idx, val);
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switch(dev->idx){
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case 0x21:
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if(dev->regs[0x21] & 0x10){
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cpu_cache_ext_enabled = 1;
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cpu_update_waitstates();
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}
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break;
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case 0x22:
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case 0x23:
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case 0x26:
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opti895_recalc(dev);
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break;
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}
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break;
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case 0xe1:
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case 0xe2:
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dev->scratch[addr] = val;
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break;
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}
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}
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static uint8_t
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opti895_read(uint16_t addr, void *priv)
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{
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uint8_t ret = 0xff;
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opti895_t *dev = (opti895_t *) priv;
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switch (addr) {
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case 0x24:
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ret = dev->regs[dev->idx];
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break;
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case 0xe1:
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case 0xe2:
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ret = dev->scratch[addr];
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break;
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}
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return ret;
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}
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static void
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opti895_close(void *priv)
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{
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opti895_t *dev = (opti895_t *) priv;
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free(dev);
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}
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static void *
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opti895_init(const device_t *info)
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{
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opti895_t *dev = (opti895_t *) malloc(sizeof(opti895_t));
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memset(dev, 0, sizeof(opti895_t));
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device_add(&port_92_device);
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io_sethandler(0x0022, 0x0001, opti895_read, NULL, NULL, opti895_write, NULL, NULL, dev);
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io_sethandler(0x0024, 0x0001, opti895_read, NULL, NULL, opti895_write, NULL, NULL, dev);
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dev->scratch[0] = dev->scratch[1] = 0xff;
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io_sethandler(0x00e1, 0x0002, opti895_read, NULL, NULL, opti895_write, NULL, NULL, dev);
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return dev;
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}
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const device_t opti895_device = {
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"OPTi 82C895",
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0,
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0,
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opti895_init, opti895_close, NULL,
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NULL, NULL, NULL,
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NULL
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};
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