2017-06-03 00:45:12 +02:00
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/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* CPU type handler.
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*
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2017-10-15 02:43:13 +02:00
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* Version: @(#)cpu.h 1.0.2 2017/10/14
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2017-06-03 00:45:12 +02:00
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*
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2017-10-07 22:18:30 -04:00
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* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
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2017-06-03 00:45:12 +02:00
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* leilei,
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* Miran Grca, <mgrca8@gmail.com>
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2017-10-07 22:18:30 -04:00
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*
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2017-06-03 00:45:12 +02:00
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* Copyright 2008-2017 Sarah Walker.
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* Copyright 2016-2017 leilei.
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2017-10-07 22:18:30 -04:00
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* Copyright 2016,2017 Miran Grca.
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2017-06-03 00:45:12 +02:00
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*/
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2017-10-07 22:18:30 -04:00
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#ifndef EMU_CPU_H
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# define EMU_CPU_H
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2016-06-26 00:34:39 +02:00
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extern int cpu, cpu_manufacturer;
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/*808x class CPUs*/
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#define CPU_8088 0
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#define CPU_8086 1
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/*286 class CPUs*/
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#define CPU_286 2
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/*386 class CPUs*/
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#define CPU_386SX 3
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#define CPU_386DX 4
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2016-06-29 06:39:35 +02:00
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#define CPU_RAPIDCAD 5
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#define CPU_486SLC 6
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#define CPU_486DLC 7
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2016-06-26 00:34:39 +02:00
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/*486 class CPUs*/
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2016-06-29 06:39:35 +02:00
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#define CPU_i486SX 8
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#define CPU_Am486SX 9
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#define CPU_Cx486S 10
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#define CPU_i486DX 11
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#define CPU_Am486DX 12
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#define CPU_Cx486DX 13
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2017-07-15 12:46:44 +02:00
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#define CPU_iDX4 14
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#define CPU_Cx5x86 15
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2016-06-26 00:34:39 +02:00
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/*586 class CPUs*/
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2017-07-15 12:46:44 +02:00
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#define CPU_WINCHIP 16
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#define CPU_PENTIUM 17
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#define CPU_PENTIUMMMX 18
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#define CPU_Cx6x86 19
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#define CPU_Cx6x86MX 20
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#define CPU_Cx6x86L 21
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#define CPU_CxGX1 22
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#define CPU_K5 23
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#define CPU_5K86 24
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#define CPU_K6 25
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2016-06-26 00:34:39 +02:00
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/*686 class CPUs*/
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2017-07-15 12:46:44 +02:00
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#define CPU_PENTIUMPRO 26
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2016-08-13 03:32:38 +02:00
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/*
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2017-07-15 12:46:44 +02:00
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#define CPU_PENTIUM2 27
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#define CPU_PENTIUM2D 28 */
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#define CPU_PENTIUM2D 27
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2016-06-26 00:34:39 +02:00
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#define MANU_INTEL 0
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#define MANU_AMD 1
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#define MANU_CYRIX 2
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#define MANU_IDT 3
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extern int timing_rr;
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extern int timing_mr, timing_mrl;
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extern int timing_rm, timing_rml;
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extern int timing_mm, timing_mml;
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extern int timing_bt, timing_bnt;
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extern int timing_int, timing_int_rm, timing_int_v86, timing_int_pm, timing_int_pm_outer;
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extern int timing_iret_rm, timing_iret_v86, timing_iret_pm, timing_iret_pm_outer;
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extern int timing_call_rm, timing_call_pm, timing_call_pm_gate, timing_call_pm_gate_inner;
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extern int timing_retf_rm, timing_retf_pm, timing_retf_pm_outer;
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extern int timing_jmp_rm, timing_jmp_pm, timing_jmp_pm_gate;
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2017-06-05 01:33:14 +02:00
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extern int timing_misaligned;
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2016-06-26 00:34:39 +02:00
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typedef struct
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{
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char name[32];
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int cpu_type;
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int speed;
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int rspeed;
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int multi;
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int pci_speed;
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uint32_t edx_reset;
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uint32_t cpuid_model;
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uint16_t cyrix_id;
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int cpu_flags;
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2016-12-23 03:16:24 +01:00
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int mem_read_cycles, mem_write_cycles;
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int cache_read_cycles, cache_write_cycles;
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2016-06-26 00:34:39 +02:00
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} CPU;
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extern CPU cpus_8088[];
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extern CPU cpus_8086[];
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extern CPU cpus_286[];
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2017-02-19 01:58:21 +01:00
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extern CPU cpus_i386SX[];
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2016-12-23 03:16:24 +01:00
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extern CPU cpus_i386DX[];
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2017-02-19 01:58:21 +01:00
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extern CPU cpus_Am386SX[];
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2016-12-23 03:16:24 +01:00
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extern CPU cpus_Am386DX[];
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2017-02-19 01:58:21 +01:00
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extern CPU cpus_486SLC[];
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2016-12-23 03:16:24 +01:00
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extern CPU cpus_486DLC[];
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2016-06-26 00:34:39 +02:00
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extern CPU cpus_i486[];
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extern CPU cpus_Am486[];
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extern CPU cpus_Cx486[];
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extern CPU cpus_WinChip[];
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extern CPU cpus_Pentium5V[];
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extern CPU cpus_Pentium5V50[];
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extern CPU cpus_PentiumS5[];
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extern CPU cpus_K5[];
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extern CPU cpus_K56[];
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extern CPU cpus_Pentium[];
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extern CPU cpus_6x86[];
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extern CPU cpus_PentiumPro[];
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extern CPU cpus_Pentium2[];
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extern CPU cpus_Pentium2D[];
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extern CPU cpus_pcjr[];
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2017-06-05 01:33:14 +02:00
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extern CPU cpus_europc[];
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2016-06-26 00:34:39 +02:00
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extern CPU cpus_pc1512[];
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extern CPU cpus_ibmat[];
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2017-10-14 07:03:19 +02:00
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extern CPU cpus_ibmxt286[];
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2016-06-26 00:34:39 +02:00
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extern CPU cpus_ps1_m2011[];
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2017-02-20 00:16:42 +01:00
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extern CPU cpus_ps2_m30_286[];
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2016-06-26 00:34:39 +02:00
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extern CPU cpus_acer[];
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extern int cpu_iscyrix;
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extern int cpu_16bitbus;
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extern int cpu_busspeed;
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extern int cpu_multi;
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2017-06-05 01:33:14 +02:00
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/*Cyrix 5x86/6x86 only has data misalignment penalties when crossing 8-byte boundaries*/
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extern int cpu_cyrix_alignment;
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2016-06-26 00:34:39 +02:00
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extern int cpu_hasrdtsc;
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extern int cpu_hasMSR;
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extern int cpu_hasMMX;
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extern int cpu_hasCR4;
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2017-07-15 12:46:44 +02:00
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extern int cpu_hasVME;
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2016-06-26 00:34:39 +02:00
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#define CR4_TSD (1 << 2)
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#define CR4_DE (1 << 3)
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#define CR4_MCE (1 << 6)
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#define CR4_PCE (1 << 8)
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#define CR4_OSFXSR (1 << 9)
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extern uint64_t cpu_CR4_mask;
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#define CPU_SUPPORTS_DYNAREC 1
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2016-07-19 02:44:32 +02:00
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#define CPU_REQUIRES_DYNAREC 2
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2016-06-26 00:34:39 +02:00
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2016-12-23 03:16:24 +01:00
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extern int cpu_cycles_read, cpu_cycles_read_l, cpu_cycles_write, cpu_cycles_write_l;
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extern int cpu_prefetch_cycles, cpu_prefetch_width;
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extern int cpu_waitstates;
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extern int cpu_cache_int_enabled, cpu_cache_ext_enabled;
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2017-06-03 00:45:12 +02:00
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extern int cpu_pci_speed;
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2016-12-23 03:16:24 +01:00
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2016-06-26 00:34:39 +02:00
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extern uint64_t tsc;
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void cyrix_write(uint16_t addr, uint8_t val, void *priv);
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uint8_t cyrix_read(uint16_t addr, void *priv);
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extern int is8086;
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void cpu_CPUID();
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void cpu_RDMSR();
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void cpu_WRMSR();
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extern int cpu_use_dynarec;
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extern int xt_cpu_multi;
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#define ISA_CYCLES_SHIFT 6
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extern int isa_cycles;
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#define ISA_CYCLES(x) ((x * isa_cycles) >> ISA_CYCLES_SHIFT)
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2016-12-23 03:16:24 +01:00
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void cpu_update_waitstates();
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2017-05-05 01:49:42 +02:00
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void cpu_set();
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2016-12-23 03:16:24 +01:00
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2017-08-16 01:04:44 +02:00
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typedef struct
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{
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uint32_t tr1, tr12;
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uint32_t cesr;
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uint32_t fcr;
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uint64_t fcr2, fcr3;
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} msr_t;
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extern msr_t msr;
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2017-10-07 22:18:30 -04:00
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#endif /*EMU_CPU_H*/
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