From 015283e5dba25ee34b9f62b51398b653bc3a8d4c Mon Sep 17 00:00:00 2001 From: OBattler Date: Mon, 31 Oct 2022 05:44:32 +0100 Subject: [PATCH] Preliminary OPTi 822 rewrite. --- src/chipset/opti5x7.c | 36 +++- src/chipset/opti822.c | 379 +++++++++++++++++++++-------------- src/chipset/opti895.c | 32 ++- src/include/86box/chipset.h | 2 + src/machine/m_at_386dx_486.c | 2 +- src/machine/m_at_socket4.c | 2 +- src/machine/m_at_socket5.c | 2 +- 7 files changed, 288 insertions(+), 167 deletions(-) diff --git a/src/chipset/opti5x7.c b/src/chipset/opti5x7.c index d85ed4f54..76989481e 100644 --- a/src/chipset/opti5x7.c +++ b/src/chipset/opti5x7.c @@ -34,7 +34,8 @@ typedef struct { - uint8_t idx, regs[16]; + uint8_t idx, is_pci, + regs[16]; } opti5x7_t; #ifdef ENABLE_OPTI5X7_LOG @@ -75,11 +76,20 @@ opti5x7_shadow_map(int cur_reg, opti5x7_t *dev) 0 1 Read from DRAM (write protected) */ if (cur_reg == 0x06) { - mem_set_mem_state_both(0xe0000, 0x10000, ((dev->regs[6] & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[6] & 2) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)); - mem_set_mem_state_both(0xf0000, 0x10000, ((dev->regs[6] & 4) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[6] & 8) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)); + if (dev->is_pci) { + mem_set_mem_state_cpu_both(0xe0000, 0x10000, ((dev->regs[6] & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[6] & 2) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)); + mem_set_mem_state_cpu_both(0xf0000, 0x10000, ((dev->regs[6] & 4) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[6] & 8) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)); + } else { + mem_set_mem_state_both(0xe0000, 0x10000, ((dev->regs[6] & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[6] & 2) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)); + mem_set_mem_state_both(0xf0000, 0x10000, ((dev->regs[6] & 4) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[6] & 8) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)); + } } else { - for (int i = 0; i < 4; i++) - mem_set_mem_state_both(0xc0000 + ((cur_reg & 1) << 16) + (i << 14), 0x4000, ((dev->regs[cur_reg] & (1 << (2 * i))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[cur_reg] & (2 << (2 * i))) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)); + for (int i = 0; i < 4; i++) { + if (dev->is_pci) + mem_set_mem_state_cpu_both(0xc0000 + ((cur_reg & 1) << 16) + (i << 14), 0x4000, ((dev->regs[cur_reg] & (1 << (2 * i))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[cur_reg] & (2 << (2 * i))) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)); + else + mem_set_mem_state_both(0xc0000 + ((cur_reg & 1) << 16) + (i << 14), 0x4000, ((dev->regs[cur_reg] & (1 << (2 * i))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[cur_reg] & (2 << (2 * i))) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)); + } } flushmmucache_nopc(); @@ -161,6 +171,8 @@ opti5x7_init(const device_t *info) opti5x7_t *dev = (opti5x7_t *) malloc(sizeof(opti5x7_t)); memset(dev, 0, sizeof(opti5x7_t)); + dev->is_pci = info->local; + io_sethandler(0x0022, 0x0001, opti5x7_read, NULL, NULL, opti5x7_write, NULL, NULL, dev); io_sethandler(0x0024, 0x0001, opti5x7_read, NULL, NULL, opti5x7_write, NULL, NULL, dev); @@ -182,3 +194,17 @@ const device_t opti5x7_device = { .force_redraw = NULL, .config = NULL }; + +const device_t opti5x7_pci_device = { + .name = "OPTi 82C5x6/82C5x7 (PCI)", + .internal_name = "opti5x7_pci", + .flags = 0, + .local = 1, + .init = opti5x7_init, + .close = opti5x7_close, + .reset = NULL, + { .available = NULL }, + .speed_changed = NULL, + .force_redraw = NULL, + .config = NULL +}; diff --git a/src/chipset/opti822.c b/src/chipset/opti822.c index ec8ce699e..20f0e8a67 100644 --- a/src/chipset/opti822.c +++ b/src/chipset/opti822.c @@ -6,14 +6,15 @@ * * This file is part of the 86Box distribution. * - * Implementation of the OPTi 82C822 VESA Local Bus to PCI Bridge Interface. + * Implementation of the OPTi 82C822 VESA Local Bus to PCI + * Bridge Interface. * * - * Authors: Tiseno100, * - * Copyright 2021 Tiseno100. + * Authors: Miran Grca, + * + * Copyright 2022 Miran Grca. */ - #include #include #include @@ -22,283 +23,349 @@ #include #define HAVE_STDARG_H #include <86box/86box.h> -#include "cpu.h" -#include <86box/timer.h> -#include <86box/io.h> #include <86box/device.h> - +#include <86box/io.h> +#include <86box/apm.h> +#include <86box/dma.h> #include <86box/mem.h> +#include <86box/smram.h> #include <86box/pci.h> - +#include <86box/timer.h> +#include <86box/pic.h> +#include <86box/pit.h> +#include <86box/port_92.h> +#include <86box/hdc_ide.h> +#include <86box/hdc.h> +#include <86box/machine.h> #include <86box/chipset.h> +#include <86box/spd.h> -/* Shadow RAM */ -#define SYSTEM_READ ((dev->pci_conf[0x44] & 2) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) -#define SYSTEM_WRITE ((dev->pci_conf[0x44] & 1) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY) -#define SHADOW_READ ((dev->pci_conf[cur_reg] & (1 << (4 + i))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) -#define SHADOW_WRITE ((dev->pci_conf[cur_reg] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY) +#define MEM_STATE_SHADOW_R 0x01 +#define MEM_STATE_SHADOW_W 0x02 +#define MEM_STATE_SMRAM 0x04 + + +typedef struct +{ + uint8_t irq_convert, + pci_regs[256]; +} opti822_t; + + +#define ENABLE_OPTI822_LOG 1 #ifdef ENABLE_OPTI822_LOG int opti822_do_log = ENABLE_OPTI822_LOG; + static void opti822_log(const char *fmt, ...) { va_list ap; if (opti822_do_log) { - va_start(ap, fmt); - pclog_ex(fmt, ap); - va_end(ap); + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); } } #else -# define opti822_log(fmt, ...) +#define opti822_log(fmt, ...) #endif -typedef struct opti822_t { - uint8_t pci_conf[256]; -} opti822_t; -int opti822_irq_routing[7] = { 5, 9, 0x0a, 0x0b, 0x0c, 0x0e, 0x0f }; - -void -opti822_shadow(int cur_reg, opti822_t *dev) +/* NOTE: We cheat here. The real ALi M1435 uses a level to edge triggered IRQ converter + when the most siginificant bit is set. We work around that by manipulating the + emulated PIC's ELCR register. */ +static void +opti822_update_irqs(opti822_t *dev, int set) { - if (cur_reg == 0x44) - mem_set_mem_state_both(0xf0000, 0x10000, SYSTEM_READ | SYSTEM_WRITE); - else - for (int i = 0; i < 4; i++) - mem_set_mem_state_both(0xe0000 - (((cur_reg & 3) - 1) << 16) + (i << 14), 0x4000, SHADOW_READ | SHADOW_WRITE); + uint8_t val; + int i, reg; + int shift, irq; + int irq_map[8] = { -1, 5, 9, 10, 11, 12, 14, 15 }; + pic_t *temp_pic; - flushmmucache_nopc(); + dev->irq_convert = (dev->pci_regs[0x53] & 0x08); + + for (i = 0; i < 4; i++) { + reg = 0x80 + (i >> 1); + shift = (i & 1) << 2; + val = (dev->pci_regs[reg] >> shift) & 0x0f; + irq = irq_map[val & 0x07]; + if (irq == -1) + continue; + temp_pic = (irq >= 8) ? &pic2 : &pic; + irq &= 7; + if (dev->irq_convert && set && (val & 0x08)) + temp_pic->elcr |= (1 << irq); + else + temp_pic->elcr &= ~(1 << irq); + } } + static void -opti822_write(int func, int addr, uint8_t val, void *priv) +opti822_pci_write(int func, int addr, uint8_t val, void *priv) { - opti822_t *dev = (opti822_t *) priv; + int irq, irq_map[8] = { -1, 5, 9, 10, 11, 12, 14, 15 }; - switch (func) { - case 0x04: /* Command Register */ - dev->pci_conf[addr] = val & 0x40; + opti822_log("opti822_write(%02X, %02X, %02X)\n", func, addr, val); + + if (func > 0) + return; + + switch (addr) { + /* Command Register */ + case 0x04: + dev->pci_regs[addr] = (val & 0x40) | 0x07; break; - case 0x05: /* Command Register */ - dev->pci_conf[addr] = val & 1; + /* Status Register */ + case 0x06: + if (!(dev->pci_regs[0x52] & 0x04)) + dev->pci_regs[addr] = (val & 0x80); + break; + case 0x07: + dev->pci_regs[addr] &= ~(val & 0xf9); break; - case 0x06: /* Status Register */ - dev->pci_conf[addr] |= val & 0xc0; - break; - - case 0x07: /* Status Register */ - dev->pci_conf[addr] = val & 0xa9; + /* Master Latency Timer Register */ + case 0x0d: + dev->pci_regs[addr] = val; break; case 0x40: - dev->pci_conf[addr] = val & 0xc0; + dev->pci_regs[addr] = (val & 0xc0) | 0x01; break; - case 0x41: - dev->pci_conf[addr] = val & 0xcf; + /* TODO: Bit 15th enable the PCI Bridge when 1. */ + dev->pci_regs[addr] = val & 0xcf; break; case 0x42: - dev->pci_conf[addr] = val & 0xf8; + dev->pci_regs[addr] = val & 0xf8; break; - case 0x43: - dev->pci_conf[addr] = val; + dev->pci_regs[addr] = val; break; - case 0x44: /* Shadow RAM */ + /* TODO: We do not currently allow separate shadow RAM mapping for PCI. */ case 0x45: + dev->pci_regs[addr] = val; + break; case 0x46: + dev->pci_regs[addr] = val; + break; case 0x47: - dev->pci_conf[addr] = (addr == 0x44) ? (val & 0xcb) : val; - opti822_shadow(addr, dev); + dev->pci_regs[addr] = val; + break; + + /* Memory hole stuff. */ + case 0x48 ... 0x51: + dev->pci_regs[addr] = val; break; - case 0x48: - case 0x49: - case 0x4a: - case 0x4b: - case 0x4c: - case 0x4d: - case 0x4e: - case 0x4f: - case 0x50: - case 0x51: case 0x52: + dev->pci_regs[addr] = val; + break; + case 0x53: - case 0x54: - case 0x55: - case 0x56: - case 0x57: - dev->pci_conf[addr] = val; + dev->pci_regs[addr] = val; + opti822_update_irqs(dev, 0); + opti822_update_irqs(dev, 1); + break; + + case 0x54 ... 0x57: + dev->pci_regs[addr] = val; break; case 0x58: - dev->pci_conf[addr] = val & 0xfc; + dev->pci_regs[addr] = val & 0xfc; + break; + case 0x59 ... 0x5b: + dev->pci_regs[addr] = val; break; - case 0x59: - case 0x5a: - case 0x5b: - case 0x5c: - case 0x5d: - case 0x5e: - case 0x5f: - dev->pci_conf[addr] = val; + case 0x5c ... 0x5f: + dev->pci_regs[addr] = val; break; case 0x60: - dev->pci_conf[addr] = val & 0xfc; + dev->pci_regs[addr] = val & 0xfc; + break; + case 0x61 ... 0x63: + dev->pci_regs[addr] = val; break; - case 0x61: - case 0x62: - case 0x63: - case 0x64: - case 0x65: - case 0x66: - case 0x67: - dev->pci_conf[addr] = val; + case 0x64 ... 0x67: + dev->pci_regs[addr] = val; break; case 0x68: - dev->pci_conf[addr] = val & 0xfc; + dev->pci_regs[addr] = val & 0xfc; + break; + case 0x69 ... 0x6b: + dev->pci_regs[addr] = val; break; - case 0x69: - case 0x6a: - case 0x6b: - case 0x6c: - case 0x6d: - case 0x6e: - case 0x6f: - dev->pci_conf[addr] = val; + case 0x6c ... 0x6f: + dev->pci_regs[addr] = val; break; case 0x70: - dev->pci_conf[addr] = val & 0xfc; + dev->pci_regs[addr] = val & 0xfc; break; - - case 0x71: - case 0x72: - case 0x73: - dev->pci_conf[addr] = val; + case 0x71 ... 0x73: + dev->pci_regs[addr] = val; break; case 0x74: - dev->pci_conf[addr] = val & 0xfc; + dev->pci_regs[addr] = val & 0xf8; break; + /* ROMCS# and NVMCS# stuff. */ case 0x75: + dev->pci_regs[addr] = val; + break; + case 0x76: - dev->pci_conf[addr] = val; + dev->pci_regs[addr] = val; break; case 0x77: - dev->pci_conf[addr] = val & 0xe7; + dev->pci_regs[addr] = val; break; + /* Enabling of memory blocks at ISA bus. */ case 0x78: - dev->pci_conf[addr] = val; + dev->pci_regs[addr] = val; break; - case 0x79: - dev->pci_conf[addr] = val & 0xfc; + dev->pci_regs[addr] = val & 0xfc; break; case 0x7a: - case 0x7b: - case 0x7c: - case 0x7d: - case 0x7e: - dev->pci_conf[addr] = val; + dev->pci_regs[addr] = val; + break; + + case 0x7b ... 0x7c: + dev->pci_regs[addr] = val; + break; + + case 0x7d ... 0x7e: + dev->pci_regs[addr] = val; break; case 0x7f: - dev->pci_conf[addr] = val & 3; + dev->pci_regs[addr] = val & 0x03; break; - case 0x80: - case 0x81: + case 0x80 ... 0x81: + dev->pci_regs[addr] = val; + break; case 0x82: - case 0x84: - case 0x85: + dev->pci_regs[addr] = val; + break; + + case 0x84 ... 0x85: + dev->pci_regs[addr] = val; + break; case 0x86: - dev->pci_conf[addr] = val; + dev->pci_regs[addr] = val; break; - case 0x88: /* PCI IRQ Routing */ - case 0x89: /* Very hacky implementation. Needs surely a rewrite after */ - case 0x8a: /* a PCI rework happens. */ - case 0x8b: - case 0x8c: - case 0x8d: - case 0x8e: - case 0x8f: - dev->pci_conf[addr] = val; - if (addr % 2) { - pci_set_irq_routing(PCI_INTB, ((val & 0x0f) != 0) ? opti822_irq_routing[(val & 7) - 1] : PCI_IRQ_DISABLED); - pci_set_irq_routing(PCI_INTA, (((val >> 4) & 0x0f) != 0) ? opti822_irq_routing[((val >> 4) & 7) - 1] : PCI_IRQ_DISABLED); - } else { - pci_set_irq_routing(PCI_INTD, ((val & 0x0f) != 0) ? opti822_irq_routing[(val & 7) - 1] : PCI_IRQ_DISABLED); - pci_set_irq_routing(PCI_INTC, (((val >> 4) & 0x0f) != 0) ? opti822_irq_routing[((val >> 4) & 7) - 1] : PCI_IRQ_DISABLED); - } - break; + case 0x88 ... 0x8f: + dev->pci_regs[addr] = val; + opti822_update_irqs(dev, 0); + irq = irq_map[val & 0x07]; + if (irq >= 0) { + opti822_log("Set IRQ routing: INT %c%c -> %02X\n", 0x41 + ((addr & 0x01) << 1), ((addr & 0x06) >> 1) + 1, irq); + pci_set_irq_routing(PCI_INTA + ((addr & 0x07) << 1), irq); + } else { + opti822_log("Set IRQ routing: INT %c%c -> FF\n", 0x41 + ((addr & 0x01) << 1), ((addr & 0x06) >> 1) + 1); + pci_set_irq_routing(PCI_INTA + ((addr & 0x07) << 1), PCI_IRQ_DISABLED); + } + irq = irq_map[(val >> 4) & 0x07]; + if (irq >= 0) { + opti822_log("Set IRQ routing: INT %c%c -> %02X\n", 0x42 + ((addr & 0x01) << 1), ((addr & 0x06) >> 1) + 1, irq); + pci_set_irq_routing(PCI_INTB + ((addr & 0x07) << 1), irq); + } else { + opti822_log("Set IRQ routing: INT %c%c -> FF\n", 0x42 + ((addr & 0x01) << 1), ((addr & 0x06) >> 1) + 1); + pci_set_irq_routing(PCI_INTB + ((addr & 0x07) << 1), PCI_IRQ_DISABLED); + } + opti822_update_irqs(dev, 1); + break; } - - opti822_log("OPTI822: dev->pci_conf[%02x] = %02x\n", addr, dev->pci_conf[addr]); } + static uint8_t -opti822_read(int func, int addr, void *priv) +opti822_pci_read(int func, int addr, void *priv) { opti822_t *dev = (opti822_t *) priv; - return dev->pci_conf[addr]; + uint8_t ret; + + ret = 0xff; + + if (func == 0) + ret = dev->pci_regs[addr]; + + opti822_log("opti822_read(%02X, %02X) = %02X\n", func, addr, ret); + + return ret; } + static void opti822_reset(void *priv) { opti822_t *dev = (opti822_t *) priv; - dev->pci_conf[0x00] = 0x45; - dev->pci_conf[0x01] = 0x10; - dev->pci_conf[0x02] = 0x22; - dev->pci_conf[0x03] = 0xc8; - dev->pci_conf[0x04] = 7; - dev->pci_conf[0x06] = 0x40; - dev->pci_conf[0x07] = 1; - dev->pci_conf[0x08] = 1; - dev->pci_conf[0x0b] = 6; - dev->pci_conf[0x0d] = 0x20; - dev->pci_conf[0x40] = 1; - dev->pci_conf[0x43] = 0x20; - dev->pci_conf[0x52] = 6; - dev->pci_conf[0x53] = 0x90; + pci_set_pmc(0); + + memset(dev->pci_regs, 0, 256); + + dev->pci_regs[0x00] = 0x45; dev->pci_regs[0x01] = 0x10; /*OPTi*/ + dev->pci_regs[0x02] = 0x22; dev->pci_regs[0x03] = 0xc8; /*82C822 PCIB*/ + dev->pci_regs[0x04] = 0x07; + dev->pci_regs[0x06] = 0x80; + dev->pci_regs[0x07] = 0x02; + dev->pci_regs[0x08] = 0x01; + dev->pci_regs[0x0b] = 0x06; + dev->pci_regs[0x0d] = 0x20; + + dev->pci_regs[0x40] = 0x01; dev->pci_regs[0x41] = 0x0c; + dev->pci_regs[0x43] = 0x02; + dev->pci_regs[0x52] = 0x06; + dev->pci_regs[0x53] = 0x90; + + dev->irq_convert = 0; + + pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED); + pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED); + pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED); + pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED); } + static void -opti822_close(void *priv) +opti822_close(void *p) { - opti822_t *dev = (opti822_t *) priv; + opti822_t *dev = (opti822_t *)p; free(dev); } + static void * opti822_init(const device_t *info) { opti822_t *dev = (opti822_t *) malloc(sizeof(opti822_t)); memset(dev, 0, sizeof(opti822_t)); - pci_add_card(PCI_ADD_NORTHBRIDGE, opti822_read, opti822_write, dev); + pci_add_card(PCI_ADD_NORTHBRIDGE, opti822_pci_read, opti822_pci_write, dev); opti822_reset(dev); diff --git a/src/chipset/opti895.c b/src/chipset/opti895.c index b2e9ae0e0..95aaf4cb6 100644 --- a/src/chipset/opti895.c +++ b/src/chipset/opti895.c @@ -35,6 +35,7 @@ typedef struct { uint8_t idx, forced_green, + is_pci, regs[256], scratch[2]; @@ -78,7 +79,10 @@ opti895_recalc(opti895_t *dev) shflags = MEM_READ_INTERNAL | MEM_WRITE_DISABLED; } - mem_set_mem_state_both(0xf0000, 0x10000, shflags); + if (dev->is_pci) + mem_set_mem_state_cpu_both(0xf0000, 0x10000, shflags); + else + mem_set_mem_state_both(0xf0000, 0x10000, shflags); for (i = 0; i < 8; i++) { base = 0xd0000 + (i << 14); @@ -98,7 +102,10 @@ opti895_recalc(opti895_t *dev) } } - mem_set_mem_state_both(base, 0x4000, shflags); + if (dev->is_pci) + mem_set_mem_state_cpu_both(base, 0x4000, shflags); + else + mem_set_mem_state_both(base, 0x4000, shflags); } for (i = 0; i < 4; i++) { @@ -119,7 +126,10 @@ opti895_recalc(opti895_t *dev) } } - mem_set_mem_state_both(base, 0x4000, shflags); + if (dev->is_pci) + mem_set_mem_state_cpu_both(base, 0x4000, shflags); + else + mem_set_mem_state_both(base, 0x4000, shflags); } flushmmucache_nopc(); @@ -232,6 +242,8 @@ opti895_init(const device_t *info) io_sethandler(0x0022, 0x0003, opti895_read, NULL, NULL, opti895_write, NULL, NULL, dev); + dev->is_pci = info->local; + dev->scratch[0] = dev->scratch[1] = 0xff; dev->regs[0x01] = 0xc0; @@ -276,6 +288,20 @@ const device_t opti802g_device = { .config = NULL }; +const device_t opti802g_pci_device = { + .name = "OPTi 82C802G (PCI)", + .internal_name = "opti802g_pci", + .flags = 0, + .local = 1, + .init = opti895_init, + .close = opti895_close, + .reset = NULL, + { .available = NULL }, + .speed_changed = NULL, + .force_redraw = NULL, + .config = NULL +}; + const device_t opti895_device = { .name = "OPTi 82C895", .internal_name = "opti895", diff --git a/src/include/86box/chipset.h b/src/include/86box/chipset.h index 6cd49b2f1..25f6ac924 100644 --- a/src/include/86box/chipset.h +++ b/src/include/86box/chipset.h @@ -108,10 +108,12 @@ extern const device_t opti291_device; extern const device_t opti493_device; extern const device_t opti495_device; extern const device_t opti802g_device; +extern const device_t opti802g_pci_device; extern const device_t opti822_device; extern const device_t opti895_device; extern const device_t opti5x7_device; +extern const device_t opti5x7_pci_device; /* SiS */ extern const device_t rabbit_device; diff --git a/src/machine/m_at_386dx_486.c b/src/machine/m_at_386dx_486.c index 1f616b791..638ac831b 100644 --- a/src/machine/m_at_386dx_486.c +++ b/src/machine/m_at_386dx_486.c @@ -637,7 +637,7 @@ machine_at_pc330_6573_init(const machine_t *model) /* doesn't like every CPU oth pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1); pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2); - device_add(&opti802g_device); + device_add(&opti802g_pci_device); device_add(&opti822_device); device_add(&keyboard_ps2_device); device_add(&fdc37c665_device); diff --git a/src/machine/m_at_socket4.c b/src/machine/m_at_socket4.c index f47a6f6df..b67277ed7 100644 --- a/src/machine/m_at_socket4.c +++ b/src/machine/m_at_socket4.c @@ -390,7 +390,7 @@ machine_at_p5vl_init(const machine_t *model) pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4); pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1); pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2); - device_add(&opti5x7_device); + device_add(&opti5x7_pci_device); device_add(&opti822_device); device_add(&sst_flash_29ee010_device); device_add(&keyboard_at_ami_device); diff --git a/src/machine/m_at_socket5.c b/src/machine/m_at_socket5.c index 4e51acb47..94d1b5ea6 100644 --- a/src/machine/m_at_socket5.c +++ b/src/machine/m_at_socket5.c @@ -340,7 +340,7 @@ machine_at_hot543_init(const machine_t *model) pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4); pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1); pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2); - device_add(&opti5x7_device); + device_add(&opti5x7_pci_device); device_add(&opti822_device); device_add(&sst_flash_29ee010_device); device_add(&keyboard_at_device);