diff --git a/src/chipset/intel_piix.c b/src/chipset/intel_piix.c index 6969d3274..ed9fd9460 100644 --- a/src/chipset/intel_piix.c +++ b/src/chipset/intel_piix.c @@ -59,7 +59,6 @@ typedef struct piix_io_trap_t { } piix_io_trap_t; typedef struct _piix_ { - uint8_t cur_readout_reg; uint8_t rev; uint8_t type; uint8_t func_shift; @@ -67,7 +66,6 @@ typedef struct _piix_ { uint8_t pci_slot; uint8_t no_mirq0; uint8_t regs[4][256]; - uint8_t readout_regs[256]; uint16_t func0_id; uint16_t nvr_io_base; uint16_t acpi_io_base; @@ -1185,31 +1183,6 @@ piix_read(int func, int addr, void *priv) return ret; } -static void -board_write(uint16_t port, uint8_t val, void *priv) -{ - piix_t *dev = (piix_t *) priv; - - if (port == 0x00e0) - dev->cur_readout_reg = val; - else if (port == 0x00e1) - dev->readout_regs[dev->cur_readout_reg] = val; -} - -static uint8_t -board_read(uint16_t port, void *priv) -{ - const piix_t *dev = (piix_t *) priv; - uint8_t ret = 0x64; - - if (port == 0x00e0) - ret = dev->cur_readout_reg; - else if (port == 0x00e1) - ret = dev->readout_regs[dev->cur_readout_reg]; - - return ret; -} - static void piix_reset_hard(piix_t *dev) { @@ -1624,40 +1597,6 @@ piix_init(const device_t *info) if (dev->type < 3) pci_enable_mirq(1); - dev->readout_regs[0] = 0xff; - dev->readout_regs[1] = 0x40; - dev->readout_regs[2] = 0xff; - - /* Port E1 register 01 (TODO: Find how multipliers > 3.0 are defined): - - Bit 6: 1 = can boot, 0 = no; - Bit 7, 1 = multiplier (00 = 2.5, 01 = 2.0, 10 = 3.0, 11 = 1.5); - Bit 5, 4 = bus speed (00 = 50 MHz, 01 = 66 MHz, 10 = 60 MHz, 11 = ????): - Bit 7, 5, 4, 1: 0000 = 125 MHz, 0010 = 166 MHz, 0100 = 150 MHz, 0110 = ??? MHz; - 0001 = 100 MHz, 0011 = 133 MHz, 0101 = 120 MHz, 0111 = ??? MHz; - 1000 = 150 MHz, 1010 = 200 MHz, 1100 = 180 MHz, 1110 = ??? MHz; - 1001 = 75 MHz, 1011 = 100 MHz, 1101 = 90 MHz, 1111 = ??? MHz */ - - if (cpu_busspeed <= 40000000) - dev->readout_regs[1] |= 0x30; - else if ((cpu_busspeed > 40000000) && (cpu_busspeed <= 50000000)) - dev->readout_regs[1] |= 0x00; - else if ((cpu_busspeed > 50000000) && (cpu_busspeed <= 60000000)) - dev->readout_regs[1] |= 0x20; - else if (cpu_busspeed > 60000000) - dev->readout_regs[1] |= 0x10; - - if (cpu_dmulti <= 1.5) - dev->readout_regs[1] |= 0x82; - else if ((cpu_dmulti > 1.5) && (cpu_dmulti <= 2.0)) - dev->readout_regs[1] |= 0x02; - else if ((cpu_dmulti > 2.0) && (cpu_dmulti <= 2.5)) - dev->readout_regs[1] |= 0x00; - else if (cpu_dmulti > 2.5) - dev->readout_regs[1] |= 0x80; - - io_sethandler(0x00e0, 0x0002, board_read, NULL, NULL, board_write, NULL, NULL, dev); - #if 0 device_add(&i8254_sec_device); #endif diff --git a/src/device/kbc_at.c b/src/device/kbc_at.c index 447c07780..aaa746570 100644 --- a/src/device/kbc_at.c +++ b/src/device/kbc_at.c @@ -509,9 +509,6 @@ kbc_scan_kbd_at(atkbc_t *dev) } } -static void -write_p2(atkbc_t *dev, uint8_t val); - static void kbc_at_poll_at(atkbc_t *dev) { @@ -778,6 +775,7 @@ static void write_p2(atkbc_t *dev, uint8_t val) { uint8_t old = dev->p2; + kbc_at_log("ATkbc: write P2: %02X (old: %02X)\n", val, dev->p2); uint8_t kbc_ven = dev->flags & KBC_VEN_MASK; @@ -851,6 +849,25 @@ write_p2(atkbc_t *dev, uint8_t val) } } +uint8_t +kbc_at_read_p(void *priv, uint8_t port, uint8_t mask) +{ + atkbc_t *dev = (atkbc_t *) priv; + uint8_t *p = (port == 2) ? &dev->p2 : &dev->p1; + uint8_t ret = *p & mask; + + return ret; +} + +void +kbc_at_write_p(void *priv, uint8_t port, uint8_t mask, uint8_t val) +{ + atkbc_t *dev = (atkbc_t *) priv; + uint8_t *p = (port == 2) ? &dev->p2 : &dev->p1; + + *p = (*p & mask) | val; +} + static void write_p2_fast_a20(atkbc_t *dev, uint8_t val) { diff --git a/src/floppy/fdc.c b/src/floppy/fdc.c index c32b1f442..de8508e69 100644 --- a/src/floppy/fdc.c +++ b/src/floppy/fdc.c @@ -81,6 +81,7 @@ int fdc_current[FDC_MAX] = { 0, 0 }; volatile int fdcinited = 0; +// #define ENABLE_FDC_LOG 1 #ifdef ENABLE_FDC_LOG int fdc_do_log = ENABLE_FDC_LOG; @@ -395,6 +396,20 @@ fdc_update_rwc(fdc_t *fdc, int drive, int rwc) fdc_rate(fdc, drive); } +uint8_t +fdc_get_media_id(fdc_t *fdc, int id) +{ + uint8_t ret = fdc->media_id & (1 << id); + + return ret; +} + +void +fdc_set_media_id(fdc_t *fdc, int id, int set) +{ + fdc->media_id = (fdc->media_id & ~(1 << id)) | (set << id); +} + int fdc_get_boot_drive(fdc_t *fdc) { @@ -1369,7 +1384,7 @@ fdc_read(uint16_t addr, void *priv) } else if (!fdc->enh_mode) ret = 0x20; else - ret = fdc->rwc[drive] << 4; + ret = (fdc->rwc[drive] << 4) | (fdc->media_id << 6); break; case 4: /*Status*/ ret = fdc->stat; @@ -2352,6 +2367,8 @@ fdc_reset(void *priv) } fdc->power_down = 0; + + fdc->media_id = 0; } static void diff --git a/src/include/86box/fdc.h b/src/include/86box/fdc.h index 2d17380d0..36cfaeb7a 100644 --- a/src/include/86box/fdc.h +++ b/src/include/86box/fdc.h @@ -119,6 +119,8 @@ typedef struct fdc_t { uint8_t lock; uint8_t dsr; + uint8_t media_id; + uint8_t params[15]; uint8_t specify[2]; uint8_t res[11]; @@ -166,6 +168,9 @@ extern void fdc_3f1_enable(fdc_t *fdc, int enable); extern int fdc_get_bit_rate(fdc_t *fdc); extern int fdc_get_bitcell_period(fdc_t *fdc); +extern uint8_t fdc_get_media_id(fdc_t *fdc, int id); +extern void fdc_set_media_id(fdc_t *fdc, int id, int set); + /* A few functions to communicate between Super I/O chips and the FDC. */ extern void fdc_update_enh_mode(fdc_t *fdc, int enh_mode); extern int fdc_get_rwc(fdc_t *fdc, int drive); diff --git a/src/include/86box/keyboard.h b/src/include/86box/keyboard.h index e21fa60d9..583960e80 100644 --- a/src/include/86box/keyboard.h +++ b/src/include/86box/keyboard.h @@ -285,6 +285,7 @@ extern int keyboard_isfsexit(void); extern int keyboard_isfsexit_up(void); extern void keyboard_set_is_amstrad(int ams); extern void kbc_at_set_ps2(void *priv, uint8_t ps2); +extern uint8_t kbc_at_read_p(void *priv, uint8_t port, uint8_t mask); extern void kbc_at_write_p(void *priv, uint8_t port, uint8_t mask, uint8_t val); extern void kbc_at_set_fast_reset(uint8_t new_fast_reset); diff --git a/src/include/86box/machine.h b/src/include/86box/machine.h index 4469b55c2..d62947848 100644 --- a/src/include/86box/machine.h +++ b/src/include/86box/machine.h @@ -806,6 +806,7 @@ extern int machine_at_p65up5_cp6nd_init(const machine_t *); /* m_at_slot1.c */ extern int machine_at_m729_init(const machine_t *); +extern int machine_at_acerv62x_init(const machine_t *); extern int machine_at_p65up5_cpknd_init(const machine_t *); extern int machine_at_kn97_init(const machine_t *); @@ -969,10 +970,14 @@ extern int machine_xt_compaq_deskpro_init(const machine_t *); extern int machine_xt_compaq_portable_init(const machine_t *); /* m_xt_laserxt.c */ -#ifdef USE_LASERXT extern int machine_xt_laserxt_init(const machine_t *); +#ifdef EMU_DEVICE_H +extern const device_t laserxt_device; +#endif extern int machine_xt_lxt3_init(const machine_t *); -#endif /* USE_LASERXT */ +#ifdef EMU_DEVICE_H +extern const device_t lxt3_device; +#endif /* m_xt_philips.c */ extern int machine_xt_p3105_init(const machine_t *); diff --git a/src/include/86box/sio.h b/src/include/86box/sio.h index 7fcb376b9..bdff29f7f 100644 --- a/src/include/86box/sio.h +++ b/src/include/86box/sio.h @@ -48,14 +48,22 @@ extern const device_t fdc37c669_370_device; extern const device_t fdc37c67x_device; -extern const device_t fdc37c931apm_device; -extern const device_t fdc37c931apm_compaq_device; -extern const device_t fdc37c932fr_device; -extern const device_t fdc37c932qf_device; -extern const device_t fdc37c932_device; -extern const device_t fdc37c935_device; -extern const device_t fdc37c935_370_device; -extern const device_t fdc37c935_no_nvr_device; +#define FDC37C93X_NORMAL 0x0002 +#define FDC37C93X_FR 0x0003 +#define FDC37C93X_APM 0x0030 +#define FDC37C93X_CHIP_ID 0x00ff + +#define FDC37C931 0x0100 /* Compaq KBC firmware and configuration registers on GPIO ports. */ +#define FDC37C932 0x0200 /* AMI '5' Megakey KBC firmware. */ +#define FDC37C933 0x0300 /* IBM KBC firmware. */ +#define FDC37C935 0x0500 /* Phoenix Multikey/42 1.38 KBC firmware. */ +#define FDC37C937 0x0700 /* Phoenix Multikey/42i 4.16 KBC firmware. */ +#define FDC37C93X_KBC 0x0f00 + +#define FDC37C93X_NO_NVR 0x1000 +#define FDC37C93X_370 0x2000 + +extern const device_t fdc37c93x_device; extern const device_t fdc37m60x_device; extern const device_t fdc37m60x_370_device; diff --git a/src/machine/CMakeLists.txt b/src/machine/CMakeLists.txt index ff6a66801..4098f2553 100644 --- a/src/machine/CMakeLists.txt +++ b/src/machine/CMakeLists.txt @@ -20,6 +20,7 @@ add_library(mch OBJECT machine_table.c m_xt.c m_xt_compaq.c + m_xt_laserxt.c m_xt_philips.c m_xt_t1000.c m_xt_t1000_vid.c @@ -64,11 +65,6 @@ if(DESKPRO386) target_compile_definitions(mch PRIVATE USE_DESKPRO386) endif() -if(LASERXT) - target_sources(mch PRIVATE m_xt_laserxt.c) - target_compile_definitions(mch PRIVATE USE_LASERXT) -endif() - if(OLIVETTI) target_compile_definitions(mch PRIVATE USE_OLIVETTI) endif() diff --git a/src/machine/m_at_slot1.c b/src/machine/m_at_slot1.c index a3ff921e3..bd3a4833f 100644 --- a/src/machine/m_at_slot1.c +++ b/src/machine/m_at_slot1.c @@ -40,6 +40,35 @@ #include <86box/clock.h> #include <86box/snd_ac97.h> +int +machine_at_acerv62x_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear("roms/machines/acerv62x/v62xc0s1.bin", + 0x000c0000, 262144, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init_ex(model, 2); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 5, 0, 0, 4); + pci_register_slot(0x12, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x10, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x0F, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1); + device_add(&i440fx_device); + device_add(&piix3_device); + device_add_params(&fdc37c93x_device, (void *) (FDC37C935 | FDC37C93X_APM)); + device_add(&sst_flash_29ee020_device); + + return ret; +} + int machine_at_p65up5_cpknd_init(const machine_t *model) { @@ -131,7 +160,7 @@ machine_at_spitfire_init(const machine_t *model) if (bios_only || !ret) return ret; - machine_at_common_init_ex(model, 2); + machine_at_common_init(model); pci_init(PCI_CONFIG_TYPE_1); pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); @@ -143,7 +172,7 @@ machine_at_spitfire_init(const machine_t *model) pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4); device_add(&i440lx_device); device_add(&piix4e_device); - device_add(&fdc37c935_no_nvr_device); + device_add_params(&fdc37c93x_device, (void *) (FDC37C935 | FDC37C93X_NORMAL | FDC37C93X_NO_NVR)); device_add(&intel_flash_bxt_device); spd_register(SPD_TYPE_SDRAM, 0xF, 256); device_add(&lm78_device); /* no reporting in BIOS */ diff --git a/src/machine/m_at_socket7.c b/src/machine/m_at_socket7.c index 3fe883323..319856d41 100644 --- a/src/machine/m_at_socket7.c +++ b/src/machine/m_at_socket7.c @@ -69,7 +69,8 @@ machine_at_acerv35n_init(const machine_t *model) pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4); device_add(&i430hx_device); device_add(&piix3_device); - device_add(&fdc37c932fr_device); + /* The chip is not marked FR but the BIOS accesses register 06h of GPIO. */ + device_add_params(&fdc37c93x_device, (void *) (FDC37C935 | FDC37C93X_FR)); device_add(&sst_flash_29ee010_device); return ret; @@ -160,7 +161,7 @@ machine_at_m7shi_init(const machine_t *model) pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); device_add(&i430hx_device); device_add(&piix3_device); - device_add(&fdc37c935_device); + device_add_params(&fdc37c93x_device, (void *) (FDC37C935 | FDC37C93X_NORMAL)); device_add(&intel_flash_bxt_device); return ret; @@ -568,7 +569,7 @@ machine_at_presario2240_init(const machine_t *model) device_add(&i430vx_device); device_add(&piix3_device); - device_add(&fdc37c932qf_device); + device_add_params(&fdc37c93x_device, (void *) (FDC37C932 | FDC37C93X_NORMAL)); device_add(&sst_flash_29ee020_device); return ret; @@ -598,7 +599,7 @@ machine_at_presario4500_init(const machine_t *model) device_add(&i430vx_device); device_add(&piix3_device); - device_add(&fdc37c931apm_compaq_device); + device_add_params(&fdc37c93x_device, (void *) (FDC37C931 | FDC37C93X_APM)); device_add(&sst_flash_29ee020_device); return ret; @@ -631,7 +632,7 @@ machine_at_dellhannibalp_init(const machine_t *model) pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 4); device_add(&i430vx_device); device_add(&piix3_device); - device_add(&fdc37c932fr_device); + device_add_params(&fdc37c93x_device, (void *) (FDC37C932 | FDC37C93X_FR)); device_add(&intel_flash_bxt_ami_device); return ret; @@ -659,7 +660,7 @@ machine_at_p55va_init(const machine_t *model) pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0); device_add(&i430vx_device); device_add(&piix3_device); - device_add(&fdc37c932fr_device); + device_add_params(&fdc37c93x_device, (void *) (FDC37C932 | FDC37C93X_FR)); device_add(&intel_flash_bxt_device); return ret; @@ -687,7 +688,7 @@ machine_at_brio80xx_init(const machine_t *model) pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); device_add(&i430vx_device); device_add(&piix3_device); - device_add(&fdc37c935_370_device); + device_add_params(&fdc37c93x_device, (void *) (FDC37C935 | FDC37C93X_NORMAL | FDC37C93X_370)); device_add(&sst_flash_29ee020_device); return ret; @@ -756,7 +757,7 @@ machine_at_pb810_init(const machine_t *model) device_add(&i430vx_device); device_add(&piix3_device); - device_add(&fdc37c935_370_device); + device_add_params(&fdc37c93x_device, (void *) (FDC37C935 | FDC37C93X_NORMAL | FDC37C93X_370)); device_add(&intel_flash_bxt_device); return ret; @@ -851,7 +852,7 @@ machine_at_gw2kte_init(const machine_t *model) device_add(&i430vx_device); device_add(&piix3_device); - device_add(&fdc37c932fr_device); + device_add_params(&fdc37c93x_device, (void *) (FDC37C932 | FDC37C93X_FR)); device_add(&intel_flash_bxt_ami_device); return ret; @@ -1553,7 +1554,7 @@ machine_at_thunderbolt_init(const machine_t *model) if (bios_only || !ret) return ret; - machine_at_common_init_ex(model, 2); + machine_at_common_init(model); pci_init(PCI_CONFIG_TYPE_1); pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); @@ -1564,7 +1565,7 @@ machine_at_thunderbolt_init(const machine_t *model) pci_register_slot(0x14, PCI_CARD_NORMAL, 3, 0, 1, 2); device_add(&i430tx_device); device_add(&piix4_device); - device_add(&fdc37c935_device); + device_add_params(&fdc37c93x_device, (void *) (FDC37C935 | FDC37C93X_NORMAL | FDC37C93X_NO_NVR)); device_add(&intel_flash_bxt_device); spd_register(SPD_TYPE_SDRAM, 0x3, 128); diff --git a/src/machine/m_at_socket7_3v.c b/src/machine/m_at_socket7_3v.c index 4b980f2b0..913c82518 100644 --- a/src/machine/m_at_socket7_3v.c +++ b/src/machine/m_at_socket7_3v.c @@ -455,7 +455,7 @@ machine_at_pb640_init(const machine_t *model) device_add(&piix_rev02_device); if (gfxcard[0] == VID_INTERNAL) - device_add(&gd5440_onboard_pci_device); + device_add(machine_get_vid_device(machine)); device_add(&keyboard_ps2_intel_ami_pci_device); device_add(&pc87306_device); @@ -546,7 +546,7 @@ machine_at_acerm3a_init(const machine_t *model) pci_register_slot(0x10, PCI_CARD_VIDEO, 4, 0, 0, 0); device_add(&i430hx_device); device_add(&piix3_device); - device_add(&fdc37c935_device); + device_add_params(&fdc37c93x_device, (void *) (FDC37C935 | FDC37C93X_NORMAL)); device_add(&sst_flash_29ee010_device); @@ -700,7 +700,7 @@ machine_at_gw2kma_init(const machine_t *model) device_add(&i430vx_device); device_add(&piix3_device); - device_add(&fdc37c932fr_device); + device_add_params(&fdc37c93x_device, (void *) (FDC37C932 | FDC37C93X_FR)); device_add(&intel_flash_bxt_ami_device); return ret; @@ -819,7 +819,7 @@ machine_at_vectra54_init(const machine_t *model) device_add(&i430fx_device); device_add(&piix_device); - device_add(&fdc37c932_device); + device_add_params(&fdc37c93x_device, (void *) (FDC37C932 | FDC37C93X_NORMAL)); device_add(&sst_flash_29ee010_device); return ret; diff --git a/src/machine/m_at_socket8.c b/src/machine/m_at_socket8.c index 935a26fb2..479c4b9fc 100644 --- a/src/machine/m_at_socket8.c +++ b/src/machine/m_at_socket8.c @@ -188,7 +188,7 @@ machine_at_acerv60n_init(const machine_t *model) pci_register_slot(0x0C, PCI_CARD_NORMAL, 2, 3, 4, 1); device_add(&i440fx_device); device_add(&piix3_device); - device_add(&fdc37c935_device); + device_add_params(&fdc37c93x_device, (void *) (FDC37C935 | FDC37C93X_NORMAL)); device_add(&sst_flash_29ee010_device); return ret; @@ -389,7 +389,7 @@ machine_at_m6mi_init(const machine_t *model) pci_register_slot(0x0F, PCI_CARD_NORMAL, 4, 1, 2, 3); device_add(&i440fx_device); device_add(&piix3_device); - device_add(&fdc37c935_device); + device_add_params(&fdc37c93x_device, (void *) (FDC37C935 | FDC37C93X_NORMAL)); device_add(&intel_flash_bxt_device); return ret; diff --git a/src/machine/m_pcjr.c b/src/machine/m_pcjr.c index ca9e72fca..d4d3b09cf 100644 --- a/src/machine/m_pcjr.c +++ b/src/machine/m_pcjr.c @@ -1566,7 +1566,8 @@ machine_pcjr_init(UNUSED(const machine_t *model)) device_add(&fdc_pcjr_device); device_add(&ns8250_pcjr_device); - serial_set_next_inst(SERIAL_MAX); /* So that serial_standalone_init() won't do anything. */ + /* So that serial_standalone_init() won't do anything. */ + serial_set_next_inst(SERIAL_MAX - 1); /* "All the inputs are 'read' with one 'IN' from address hex 201." - PCjr Technical Reference (Nov. 83), p.2-119 diff --git a/src/machine/m_xt_laserxt.c b/src/machine/m_xt_laserxt.c index c0405f99a..d298e726b 100644 --- a/src/machine/m_xt_laserxt.c +++ b/src/machine/m_xt_laserxt.c @@ -1,6 +1,7 @@ /*This is the chipset used in the LaserXT series model*/ #include #include +#include #include #include #include <86box/86box.h> @@ -21,125 +22,411 @@ #include <86box/keyboard.h> #include <86box/plat_unused.h> -static int laserxt_emspage[4]; -static int laserxt_emscontrol[4]; -static mem_mapping_t laserxt_ems_mapping[4]; -static int laserxt_ems_baseaddr_index = 0; -static int laserxt_is_lxt3 = 0; +#define EMS_TOTAL_MAX 0x00100000 -static uint32_t -get_laserxt_ems_addr(uint32_t addr) +typedef struct { - if (laserxt_emspage[(addr >> 14) & 3] & 0x80) { - addr = (!laserxt_is_lxt3 ? 0x70000 + (((mem_size + 64) & 255) << 10) : 0x30000 + (((mem_size + 320) & 511) << 10)) + ((laserxt_emspage[(addr >> 14) & 3] & 0x0F) << 14) + ((laserxt_emspage[(addr >> 14) & 3] & 0x40) << 12) + (addr & 0x3FFF); - } + uint8_t page; + uint8_t ctrl; - return addr; + uint32_t phys; + uint32_t virt; + + mem_mapping_t mapping; + + uint8_t *ram; + + void *parent; +} lxt_ems_t; + +typedef struct +{ + int ems_base_idx; + + lxt_ems_t ems[4]; + + uint16_t io_base; + uint32_t base; + + uint32_t mem_size; + + uint8_t *ram; + + void *parent; +} lxt_ems_board_t; + +typedef struct +{ + int is_lxt3; + + lxt_ems_board_t *ems_boards[2]; +} lxt_t; + +static void +ems_update_virt(lxt_ems_t *dev, uint8_t new_page) +{ + lxt_ems_board_t *board = (lxt_ems_board_t *) dev->parent; + lxt_t *lxt = (lxt_t *) board->parent; + + dev->page = new_page; + + if (new_page & 0x80) { + if (lxt->is_lxt3) { + /* Point invalid pages at 1 MB which is outside the maximum. */ + if ((new_page & 0x7f) >= 0x40) + dev->virt = EMS_TOTAL_MAX; + else + dev->virt = ((new_page & 0x7f) << 14); + } else + dev->virt = ((new_page & 0x0f) << 14) + ((new_page & 0x40) << 12); + + if (dev->virt >= board->mem_size) + dev->virt = EMS_TOTAL_MAX; + } else + dev->virt = EMS_TOTAL_MAX; + + dev->ram = board->ram + dev->virt; + + if ((new_page & 0x80) && (dev->virt != EMS_TOTAL_MAX)) { + mem_mapping_enable(&dev->mapping); + + mem_mapping_set_exec(&dev->mapping, dev->ram); + mem_mapping_set_p(&dev->mapping, dev->ram); + } else + mem_mapping_disable(&dev->mapping); + + flushmmucache(); } static void -laserxt_write(uint16_t port, uint8_t val, UNUSED(void *priv)) +lxt_ems_out(uint16_t port, uint8_t val, void *priv) { - uint32_t paddr; - uint32_t vaddr; - switch (port) { - case 0x0208: - case 0x4208: - case 0x8208: - case 0xC208: - laserxt_emspage[port >> 14] = val; - paddr = 0xC0000 + (port & 0xC000) + (((laserxt_ems_baseaddr_index + (4 - (port >> 14))) & 0x0C) << 14); - if (val & 0x80) { - mem_mapping_enable(&laserxt_ems_mapping[port >> 14]); - vaddr = get_laserxt_ems_addr(paddr); - mem_mapping_set_exec(&laserxt_ems_mapping[port >> 14], ram + vaddr); - } else { - mem_mapping_disable(&laserxt_ems_mapping[port >> 14]); - } - flushmmucache(); - break; - case 0x0209: - case 0x4209: - case 0x8209: - case 0xC209: - laserxt_emscontrol[port >> 14] = val; - laserxt_ems_baseaddr_index = 0; + lxt_ems_board_t *dev = (lxt_ems_board_t *) priv; + uint8_t reg = port >> 14; + uint32_t saddrs[8] = { 0xc4000, 0xc8000, 0xcc000, 0xd0000, + 0xd4000, 0xd8000, 0xdc000, 0xe0000 }; + uint32_t saddr; + + if (port & 0x0001) { + dev->ems[reg].ctrl = val; + + if (reg < 0x03) { + dev->ems_base_idx = (dev->ems_base_idx & ~(0x04 >> (2 - reg))) | + ((dev->ems[reg].ctrl & 0x80) >> (7 - reg)); + + saddr = saddrs[dev->ems_base_idx]; + for (uint8_t i = 0; i < 4; i++) { - laserxt_ems_baseaddr_index |= (laserxt_emscontrol[i] & 0x80) >> (7 - i); + uint32_t base = saddr + (i * 0x4000); + mem_mapping_set_addr(&dev->ems[i].mapping, base, 0x4000); + if (!(dev->ems[i].page & 0x80) || (dev->ems[i].virt == EMS_TOTAL_MAX)) + mem_mapping_disable(&dev->ems[i].mapping); } + } - mem_mapping_set_addr(&laserxt_ems_mapping[0], 0xC0000 + (((laserxt_ems_baseaddr_index + 4) & 0x0C) << 14), 0x4000); - mem_mapping_set_addr(&laserxt_ems_mapping[1], 0xC4000 + (((laserxt_ems_baseaddr_index + 3) & 0x0C) << 14), 0x4000); - mem_mapping_set_addr(&laserxt_ems_mapping[2], 0xC8000 + (((laserxt_ems_baseaddr_index + 2) & 0x0C) << 14), 0x4000); - mem_mapping_set_addr(&laserxt_ems_mapping[3], 0xCC000 + (((laserxt_ems_baseaddr_index + 1) & 0x0C) << 14), 0x4000); - flushmmucache(); - break; - - default: - break; + flushmmucache(); + } else if (!(port & 0x0001)) { + dev->ems[reg].page = val; + ems_update_virt(&dev->ems[reg], val); } } static uint8_t -laserxt_read(uint16_t port, UNUSED(void *priv)) +lxt_ems_in(uint16_t port, void *priv) { - switch (port) { - case 0x0208: - case 0x4208: - case 0x8208: - case 0xC208: - return laserxt_emspage[port >> 14]; - case 0x0209: - case 0x4209: - case 0x8209: - case 0xC209: - return laserxt_emscontrol[port >> 14]; + lxt_ems_board_t *dev = (lxt_ems_board_t *) priv; + uint8_t reg = port >> 14; + uint8_t ret = 0xff; - default: - break; - } - return 0xff; + if (port & 0x0001) + ret = dev->ems[reg].ctrl; + else + ret = dev->ems[reg].page; + + return ret; } static void -mem_write_laserxtems(uint32_t addr, uint8_t val, UNUSED(void *priv)) +lxt_ems_write(uint32_t addr, uint8_t val, void *priv) { - addr = get_laserxt_ems_addr(addr); - if (addr < (mem_size << 10)) - ram[addr] = val; + uint8_t *mem = (uint8_t *) priv; + + mem[addr & 0x3fff] = val; } static uint8_t -mem_read_laserxtems(uint32_t addr, UNUSED(void *priv)) +lxt_ems_read(uint32_t addr, void *priv) { - uint8_t val = 0xFF; - addr = get_laserxt_ems_addr(addr); - if (addr < (mem_size << 10)) - val = ram[addr]; - return val; + uint8_t *mem = (uint8_t *) priv; + uint8_t ret = 0xff; + + ret = mem[addr & 0x3fff]; + + return ret; +} + +static lxt_ems_board_t * +lxt_ems_init(lxt_t *parent, int en, uint16_t io, uint32_t mem) +{ + lxt_ems_board_t *dev = (lxt_ems_board_t *) calloc(1, sizeof(lxt_ems_board_t)); + + if (en) { + dev->parent = parent; + + if (io != 0x0000) { + io_sethandler(io , 0x0002, lxt_ems_in, NULL, NULL, lxt_ems_out, NULL, NULL, dev); + io_sethandler(io | 0x4000, 0x0002, lxt_ems_in, NULL, NULL, lxt_ems_out, NULL, NULL, dev); + io_sethandler(io | 0x8000, 0x0002, lxt_ems_in, NULL, NULL, lxt_ems_out, NULL, NULL, dev); + io_sethandler(io | 0xc000, 0x0002, lxt_ems_in, NULL, NULL, lxt_ems_out, NULL, NULL, dev); + } + + dev->ram = (uint8_t *) calloc(mem, sizeof(uint8_t)); + dev->mem_size = mem; + + for (uint8_t i = 0; i < 4; i++) { + uint8_t *ptr = dev->ram + (i << 14); + + mem_mapping_add(&dev->ems[i].mapping, 0xe0000 + (i << 14), 0x4000, + lxt_ems_read, NULL, NULL, + lxt_ems_write, NULL, NULL, + ptr, 0, ptr); + mem_mapping_disable(&dev->ems[i].mapping); + + dev->ems[i].page = 0x7f; + dev->ems[i].ctrl = (i == 3) ? 0x00 : 0x80; + + dev->ems[i].parent = dev; + + ems_update_virt(&(dev->ems[i]), dev->ems[i].page); + } + } + + return dev; } static void -laserxt_init(int is_lxt3) +lxt_close(void *priv) { - if (mem_size > 640) { - io_sethandler(0x0208, 0x0002, laserxt_read, NULL, NULL, laserxt_write, NULL, NULL, NULL); - io_sethandler(0x4208, 0x0002, laserxt_read, NULL, NULL, laserxt_write, NULL, NULL, NULL); - io_sethandler(0x8208, 0x0002, laserxt_read, NULL, NULL, laserxt_write, NULL, NULL, NULL); - io_sethandler(0xc208, 0x0002, laserxt_read, NULL, NULL, laserxt_write, NULL, NULL, NULL); - mem_mapping_set_addr(&ram_low_mapping, 0, !is_lxt3 ? 0x70000 + (((mem_size + 64) & 255) << 10) : 0x30000 + (((mem_size + 320) & 511) << 10)); + lxt_t *dev = (lxt_t *) priv; + int ems_boards = (1 - dev->is_lxt3) + 1; + + for (int i = 0; i < ems_boards; i++) + if (dev->ems_boards[i] != NULL) { + if (dev->ems_boards[i]->ram != NULL) + free(dev->ems_boards[i]->ram); + free(dev->ems_boards[i]); + } + + free(dev); +} + +static void * +lxt_init(const device_t *info) +{ + lxt_t * dev = (lxt_t *) calloc(1, sizeof(lxt_t)); + int ems_boards = (1 - info->local) + 1; + int ems_en[2] = { 0 }; + uint16_t ems_io[2] = { 0 }; + uint32_t ems_mem[2] = { 0 }; + char conf_str[512] = { 0 }; + + dev->is_lxt3 = info->local; + + for (int i = 0; i < ems_boards; i++) { + sprintf(conf_str, "ems_%i_enable", i + 1); + ems_en[i] = device_get_config_int(conf_str); + + sprintf(conf_str, "ems_%i_base", i + 1); + ems_io[i] = device_get_config_hex16(conf_str); + + sprintf(conf_str, "ems_%i_mem_size", i + 1); + ems_mem[i] = device_get_config_int(conf_str) << 10; + + dev->ems_boards[i] = lxt_ems_init(dev, ems_en[i], ems_io[i], ems_mem[i]); } - for (uint8_t i = 0; i < 4; i++) { - laserxt_emspage[i] = 0x7F; - laserxt_emscontrol[i] = (i == 3) ? 0x00 : 0x80; - mem_mapping_add(&laserxt_ems_mapping[i], 0xE0000 + (i << 14), 0x4000, mem_read_laserxtems, NULL, NULL, mem_write_laserxtems, NULL, NULL, ram + 0xA0000 + (i << 14), 0, NULL); - mem_mapping_disable(&laserxt_ems_mapping[i]); - } mem_set_mem_state(0x0c0000, 0x40000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - laserxt_is_lxt3 = is_lxt3; + + return dev; } +static const device_config_t laserxt_config[] = { + { + .name = "ems_1_base", + .description = "EMS 1 Address", + .type = CONFIG_HEX16, + .default_string = NULL, + .default_int = 0, + .file_filter = NULL, + .spinner = { 0 }, + .selection = { + { .description = "Disabled", .value = 0 }, + { .description = "0x208", .value = 0x208 }, + { .description = "0x218", .value = 0x218 }, + { .description = "0x258", .value = 0x258 }, + { .description = "0x268", .value = 0x268 }, + { .description = "0x2A8", .value = 0x2a8 }, + { .description = "0x2B8", .value = 0x2b8 }, + { .description = "0x2E8", .value = 0x2e8 }, + { .description = "" } + }, + .bios = { { 0 } } + }, + { + .name = "ems_2_base", + .description = "EMS 2 Address", + .type = CONFIG_HEX16, + .default_string = NULL, + .default_int = 0, + .file_filter = NULL, + .spinner = { 0 }, + .selection = { + { .description = "Disabled", .value = 0 }, + { .description = "0x208", .value = 0x208 }, + { .description = "0x218", .value = 0x218 }, + { .description = "0x258", .value = 0x258 }, + { .description = "0x268", .value = 0x268 }, + { .description = "0x2A8", .value = 0x2a8 }, + { .description = "0x2B8", .value = 0x2b8 }, + { .description = "0x2E8", .value = 0x2e8 }, + { .description = "" } + }, + .bios = { { 0 } } + }, + { + .name = "ems_1_mem_size", + .description = "EMS 1 Memory Size", + .type = CONFIG_SPINNER, + .default_string = NULL, + .default_int = 0, + .file_filter = NULL, + .spinner = { + .min = 0, + .max = 512, + .step = 32 + }, + .selection = { { 0 } }, + .bios = { { 0 } } + }, + { + .name = "ems_2_mem_size", + .description = "EMS 2 Memory Size", + .type = CONFIG_SPINNER, + .default_string = NULL, + .default_int = 0, + .file_filter = NULL, + .spinner = { + .min = 0, + .max = 512, + .step = 32 + }, + .selection = { { 0 } }, + .bios = { { 0 } } + }, + { + .name = "ems_1_enable", + .description = "Enable EMS 1", + .type = CONFIG_BINARY, + .default_string = NULL, + .default_int = 0, + .file_filter = NULL, + .spinner = { 0 }, + .selection = { { 0 } }, + .bios = { { 0 } } + }, + { + .name = "ems_2_enable", + .description = "Enable EMS 2", + .type = CONFIG_BINARY, + .default_string = NULL, + .default_int = 0, + .file_filter = NULL, + .spinner = { 0 }, + .selection = { { 0 } }, + .bios = { { 0 } } + }, + { .name = "", .description = "", .type = CONFIG_END } +}; + +const device_t laserxt_device = { + .name = "VTech Laser Turbo XT", + .internal_name = "laserxt", + .flags = 0, + .local = 0, + .init = lxt_init, + .close = lxt_close, + .reset = NULL, + .available = NULL, + .speed_changed = NULL, + .force_redraw = NULL, + .config = laserxt_config +}; + +static const device_config_t lxt3_config[] = { + { + .name = "ems_1_base", + .description = "EMS Address", + .type = CONFIG_HEX16, + .default_string = NULL, + .default_int = 0, + .file_filter = NULL, + .spinner = { 0 }, + .selection = { + { .description = "Disabled", .value = 0 }, + { .description = "0x208", .value = 0x208 }, + { .description = "0x218", .value = 0x218 }, + { .description = "0x258", .value = 0x258 }, + { .description = "0x268", .value = 0x268 }, + { .description = "0x2A8", .value = 0x2a8 }, + { .description = "0x2B8", .value = 0x2b8 }, + { .description = "0x2E8", .value = 0x2e8 }, + { .description = "" } + }, + .bios = { { 0 } } + }, + { + .name = "ems_1_mem_size", + .description = "EMS Memory Size", + .type = CONFIG_SPINNER, + .default_string = NULL, + .default_int = 0, + .file_filter = NULL, + .spinner = { + .min = 0, + .max = 1024, + .step = 32 + }, + .selection = { { 0 } }, + .bios = { { 0 } } + }, + { + .name = "ems_1_enable", + .description = "Enable EMS", + .type = CONFIG_BINARY, + .default_string = NULL, + .default_int = 0, + .file_filter = NULL, + .spinner = { 0 }, + .selection = { { 0 } }, + .bios = { { 0 } } + }, + { .name = "", .description = "", .type = CONFIG_END } +}; + +const device_t lxt3_device = { + .name = "VTech Laser Turbo XT", + .internal_name = "laserxt", + .flags = 0, + .local = 1, + .init = lxt_init, + .close = lxt_close, + .reset = NULL, + .available = NULL, + .speed_changed = NULL, + .force_redraw = NULL, + .config = lxt3_config +}; + static void machine_xt_laserxt_common_init(const machine_t *model,int is_lxt3) { @@ -153,7 +440,7 @@ machine_xt_laserxt_common_init(const machine_t *model,int is_lxt3) nmi_init(); standalone_gameport_type = &gameport_device; - laserxt_init(is_lxt3); + device_add(is_lxt3 ? &lxt3_device : &laserxt_device); device_add(&keyboard_xt_lxt3_device); } diff --git a/src/machine/m_xt_zenith.c b/src/machine/m_xt_zenith.c index 6c5d556f2..62c6496d1 100644 --- a/src/machine/m_xt_zenith.c +++ b/src/machine/m_xt_zenith.c @@ -146,7 +146,8 @@ machine_xt_z184_init(const machine_t *model) lpt2_remove(); lpt1_setup(LPT2_ADDR); device_add(&ns8250_device); - serial_set_next_inst(SERIAL_MAX); /* So that serial_standalone_init() won't do anything. */ + /* So that serial_standalone_init() won't do anything. */ + serial_set_next_inst(SERIAL_MAX - 1); device_add(&cga_device); diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index 9c83f4b22..44e93f721 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -1709,7 +1709,6 @@ const machine_t machines[] = { .snd_device = NULL, .net_device = NULL }, -#ifdef USE_LASERXT { .name = "[8088] VTech Laser Turbo XT", .internal_name = "ltxt", @@ -1742,14 +1741,13 @@ const machine_t machines[] = { .kbc_p1 = 0xff, .gpio = 0xffffffff, .gpio_acpi = 0xffffffff, - .device = NULL, + .device = &laserxt_device, .fdc_device = NULL, .sio_device = NULL, .vid_device = NULL, .snd_device = NULL, .net_device = NULL }, -#endif /* USE_LASERXT */ /* Has a standard PS/2 KBC (so, use IBM PS/2 Type 1). */ { .name = "[8088] Xi8088", @@ -2612,8 +2610,6 @@ const machine_t machines[] = { .snd_device = NULL, .net_device = NULL }, - -#ifdef USE_LASERXT { .name = "[8086] VTech Laser XT3", .internal_name = "lxt3", @@ -2637,23 +2633,22 @@ const machine_t machines[] = { .bus_flags = MACHINE_PC, .flags = MACHINE_FLAGS_NONE, .ram = { - .min = 256, + .min = 512, .max = 640, - .step = 256 + .step = 64 }, .nvrmask = 0, .kbc_device = &keyboard_xt_lxt3_device, .kbc_p1 = 0xff, .gpio = 0xffffffff, .gpio_acpi = 0xffffffff, - .device = NULL, + .device = &lxt3_device, .fdc_device = NULL, .sio_device = NULL, .vid_device = NULL, .snd_device = NULL, .net_device = NULL }, -#endif /* USE_LASERXT */ /* 286 AT machines */ /* Has IBM AT KBC firmware. */ @@ -8156,7 +8151,10 @@ const machine_t machines[] = { .snd_device = NULL, .net_device = NULL }, - /* I'm going to assume this as an AMIKey-2 like the other two 486SP3's. */ + /* + This has an AMIKey (and an on-board NCR 53C810 PCI SCSI controller), thanks, eBay! + The keyboard port is AT. + */ { .name = "[i420TX] ASUS PCI/I-486SP3", .internal_name = "486sp3", @@ -10092,7 +10090,7 @@ const machine_t machines[] = { .max_multi = 1.5 }, .bus_flags = MACHINE_PS2_PCI, - .flags = MACHINE_IDE | MACHINE_SCSI | MACHINE_APM, + .flags = MACHINE_IDE /*| MACHINE_SCSI */ | MACHINE_APM, .ram = { .min = 2048, .max = 524288, @@ -14593,6 +14591,47 @@ const machine_t machines[] = { }, /* 440FX */ + /* Has a SM(S)C FDC37C935 Super I/O chip with on-chip KBC with Phoenix + MultiKey/42 (version 1.38) KBC firmware. */ + { + .name = "[i440FX] Acer V62X", + .internal_name = "acerv62x", + .type = MACHINE_TYPE_SLOT1, + .chipset = MACHINE_CHIPSET_INTEL_440FX, + .init = machine_at_acerv62x_init, + .p1_handler = NULL, + .gpio_handler = NULL, + .available_flag = MACHINE_AVAILABLE, + .gpio_acpi_handler = NULL, + .cpu = { + .package = CPU_PKG_SLOT1, + .block = CPU_BLOCK_NONE, + .min_bus = 60000000, + .max_bus = 83333333, + .min_voltage = 1800, + .max_voltage = 3500, + .min_multi = 1.5, + .max_multi = 8.0 + }, + .bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB, + .flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB, + .ram = { + .min = 8192, + .max = 786432, + .step = 8192 + }, + .nvrmask = 511, + .kbc_device = NULL, + .kbc_p1 = 0xff, + .gpio = 0xffffffff, + .gpio_acpi = 0xffffffff, + .device = NULL, + .fdc_device = NULL, + .sio_device = NULL, + .vid_device = NULL, + .snd_device = NULL, + .net_device = NULL + }, /* The base board has a Holtek HT6542B KBC with AMIKey-2 (updated 'H') KBC firmware. */ { .name = "[i440FX] ASUS P/I-P65UP5 (C-PKND)", diff --git a/src/sio/sio_fdc37c93x.c b/src/sio/sio_fdc37c93x.c index 8d8f76cb6..ebc500c96 100644 --- a/src/sio/sio_fdc37c93x.c +++ b/src/sio/sio_fdc37c93x.c @@ -15,8 +15,9 @@ * * Copyright 2016-2018 Miran Grca. */ -#include +#include #include +#include #include #include #include @@ -25,6 +26,7 @@ #include <86box/timer.h> #include <86box/device.h> #include <86box/pci.h> +#include <86box/pic.h> #include <86box/lpt.h> #include <86box/serial.h> #include <86box/hdc.h> @@ -37,20 +39,28 @@ #include <86box/apm.h> #include <86box/access_bus.h> #include <86box/acpi.h> -#include <86box/sio.h> +#include <86box/plat.h> #include <86box/plat_unused.h> +#include <86box/video.h> +#include <86box/sio.h> +#include "cpu.h" typedef struct fdc37c93x_t { uint8_t chip_id; uint8_t is_apm; uint8_t is_compaq; uint8_t has_nvr; + uint8_t max_ld; uint8_t tries; uint8_t port_370; - uint8_t gpio_regs[2]; + uint8_t gpio_reg; + uint8_t gpio_regs[256]; + uint8_t gpio_pulldn[8]; uint8_t auxio_reg; uint8_t regs[48]; + uint8_t alt_regs[3][8]; uint8_t ld_regs[11][256]; + uint16_t kbc_type; uint16_t superio_base; uint16_t fdc_base; uint16_t lpt_base; @@ -73,6 +83,15 @@ typedef struct fdc37c93x_t { static void fdc37c93x_write(uint16_t port, uint8_t val, void *priv); static uint8_t fdc37c93x_read(uint16_t port, void *priv); +static uint8_t gp_func_regs[8][8] = { { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, /* GP00-GP07 */ + { 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7 }, /* GP10-GP17 */ + { 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef }, /* GP20-GP27 */ + { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, /* GP30-GP37 */ + { 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7 }, /* GP40-GP47 */ + { 0xc8, 0xc9, 0xff, 0xcb, 0xcc, 0xff, 0xff, 0xff }, /* GP50-GP57 */ + { 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7 }, /* GP60-GP67 */ + { 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf } }; /* GP70-GP77 */ + static uint16_t make_port_superio(const fdc37c93x_t *dev) { @@ -122,14 +141,562 @@ fdc37c93x_auxio_write(UNUSED(uint16_t port), uint8_t val, void *priv) dev->auxio_reg = val; } +static __inline uint8_t +fdc37c93x_do_read_gp(fdc37c93x_t *dev, int reg, int bit) +{ + /* Update bit 2 on the Acer V35N according to the selected graphics card type. */ + if ((reg == 2) && (strstr(machine_get_internal_name(), "acer") != NULL)) + dev->gpio_pulldn[reg] = (dev->gpio_pulldn[reg] & 0xfb) | (video_is_mda() ? 0x00 : 0x04); + + return dev->gpio_regs[reg] & dev->gpio_pulldn[reg] & (1 << bit); +} + +static __inline uint8_t +fdc37c93x_do_read_alt(const fdc37c93x_t *dev, int alt, int reg, int bit) +{ + return dev->alt_regs[alt][reg] & (1 << bit); +} + +static uint8_t +fdc37c93x_read_gp(const fdc37c93x_t *dev, int reg, int bit) +{ + uint8_t gp_reg = gp_func_regs[reg][bit]; + uint8_t gp_func_reg = dev->ld_regs[0x08][gp_reg]; + uint8_t gp_func; + uint8_t ret = 1 << bit; + + if (gp_func_reg & 0x01) switch (reg) { + default: + /* Do nothing, this GP does not exist. */ + break; + case 1: + switch (bit) { + default: + gp_func = (gp_func_reg >> 3) & 0x01; + if (gp_func == 0x00) + ret = fdc37c93x_do_read_gp((fdc37c93x_t *) dev, reg, bit); + else + ret = fdc37c93x_do_read_alt(dev, 0, reg, bit); + break; + case 1: + gp_func = (gp_func_reg >> 3) & 0x03; + if (!(gp_func & 0x01)) { + if (gp_func & 0x02) + ret = fdc37c93x_do_read_alt(dev, 0, reg, bit); + else + ret = fdc37c93x_do_read_gp((fdc37c93x_t *) dev, reg, bit); + } + break; + case 3: + gp_func = (gp_func_reg >> 3) & 0x01; + if (gp_func == 0x01) + /* TODO: Write to power LED if it's ever implemented. */ + ret = fdc37c93x_do_read_alt(dev, 0, reg, bit); + else + ret = fdc37c93x_do_read_gp((fdc37c93x_t *) dev, reg, bit); + break; + case 6: + gp_func = (gp_func_reg >> 3) & 0x03; + switch (gp_func) { + case 0: + ret = fdc37c93x_do_read_gp((fdc37c93x_t *) dev, reg, bit); + break; + case 1 ... 3: + ret = fdc37c93x_do_read_alt(dev, gp_func - 1, reg, bit); + break; + } + break; + } + break; + case 2: + switch (bit) { + default: + gp_func = (gp_func_reg >> 3) & 0x01; + if (gp_func == 0x00) + ret = fdc37c93x_do_read_gp((fdc37c93x_t *) dev, reg, bit); + else + ret = fdc37c93x_do_read_alt(dev, 0, reg, bit); + break; + case 0: + gp_func = (gp_func_reg >> 3) & 0x03; + switch (gp_func) { + case 0: + ret = fdc37c93x_do_read_gp((fdc37c93x_t *) dev, reg, bit); + break; + case 1: + ret = fdc37c93x_do_read_alt(dev, 0, reg, bit); + break; + case 2: + ret = kbc_at_read_p(dev->kbc, 2, 0x01) ? (1 << bit) : 0x00; + break; + } + break; + case 1: case 2: + gp_func = (gp_func_reg >> 3) & 0x03; + switch (gp_func) { + case 0: + ret = fdc37c93x_do_read_gp((fdc37c93x_t *) dev, reg, bit); + break; + case 1: case 2: + ret = fdc37c93x_do_read_alt(dev, gp_func - 1, reg, bit); + break; + } + break; + case 5: + gp_func = (gp_func_reg >> 3) & 0x01; + if (gp_func == 0x00) + ret = fdc37c93x_do_read_gp((fdc37c93x_t *) dev, reg, bit); + else + ret = kbc_at_read_p(dev->kbc, 2, 0x02) ? (1 << bit) : 0x00; + break; + case 6: case 7: + /* Do nothing, these bits do not exist. */ + break; + } + break; + case 4: + gp_func = (gp_func_reg >> 3) & 0x03; + switch (bit) { + default: + switch (gp_func) { + case 0: + ret = fdc37c93x_do_read_alt(dev, 0, reg, bit); + break; + case 1: + ret = fdc37c93x_do_read_gp((fdc37c93x_t *) dev, reg, bit); + break; + } + break; + case 0: case 1: + switch (gp_func) { + case 0: + ret = fdc_get_media_id(dev->fdc, bit ^ 1) ? (1 << bit) : 0x00; + break; + case 1: + ret = fdc37c93x_do_read_gp((fdc37c93x_t *) dev, reg, bit); + break; + } + break; + case 6: + switch (gp_func) { + case 0: + ret = fdc37c93x_do_read_alt(dev, 0, reg, bit); + break; + case 1: + ret = fdc37c93x_do_read_gp((fdc37c93x_t *) dev, reg, bit); + break; + case 2: + /* TODO: Write to power LED if it's ever implemented. */ + ret = fdc37c93x_do_read_alt(dev, 1, reg, bit); + break; + case 3: + ret = fdc37c93x_do_read_alt(dev, 2, reg, bit); + break; + } + break; + case 7: + switch (gp_func) { + case 0: + ret = fdc37c93x_do_read_alt(dev, 0, reg, bit); + break; + case 1: + ret = fdc37c93x_do_read_gp((fdc37c93x_t *) dev, reg, bit); + break; + case 2: + ret = fdc37c93x_do_read_alt(dev, 1, reg, bit); + break; + } + break; + } + break; + case 5: + gp_func = (gp_func_reg >> 3) & 0x03; + switch (bit) { + default: + break; + case 0: case 3: case 4: + switch (gp_func) { + case 0: + ret = fdc37c93x_do_read_alt(dev, 0, reg, bit); + break; + case 1: + ret = fdc37c93x_do_read_gp((fdc37c93x_t *) dev, reg, bit); + break; + } + break; + case 1: + switch (gp_func) { + case 0: + ret = fdc37c93x_do_read_alt(dev, 0, reg, bit); + break; + case 1: + ret = fdc37c93x_do_read_gp((fdc37c93x_t *) dev, reg, bit); + break; + } + break; + } + break; + case 6: + gp_func = (gp_func_reg >> 3) & 0x03; + switch (bit) { + default: + switch (gp_func) { + case 0: + ret = fdc37c93x_do_read_alt(dev, 0, reg, bit); + break; + case 1: + ret = fdc37c93x_do_read_gp((fdc37c93x_t *) dev, reg, bit); + break; + case 2: + ret = kbc_at_read_p(dev->kbc, 1, 1 << bit); + break; + } + break; + case 0: + switch (gp_func) { + case 0: + ret = fdc37c93x_do_read_alt(dev, 0, reg, bit); + break; + case 1: + ret = fdc37c93x_do_read_gp((fdc37c93x_t *) dev, reg, bit); + break; + case 2: + /* TODO: Write to power LED if it's ever implemented. */ + ret = fdc37c93x_do_read_alt(dev, 1, reg, bit); + break; + } + break; + case 1: + switch (gp_func) { + case 0: + ret = fdc37c93x_do_read_alt(dev, 0, reg, bit); + break; + case 1: + ret = fdc37c93x_do_read_gp((fdc37c93x_t *) dev, reg, bit); + break; + case 2: + ret = fdc37c93x_do_read_alt(dev, 1, reg, bit); + break; + } + break; + } + break; + case 7: + gp_func = (gp_func_reg >> 3) & 0x03; + switch (bit) { + default: + switch (gp_func) { + case 0: + ret = fdc37c93x_do_read_alt(dev, 0, reg, bit); + break; + case 1: + ret = fdc37c93x_do_read_gp((fdc37c93x_t *) dev, reg, bit); + break; + } + break; + } + break; + } + + if (gp_func_reg & 0x02) + ret ^= (1 << bit); + + return ret; +} + +static __inline void +fdc37c93x_do_write_gp(fdc37c93x_t *dev, int reg, int bit, int set) +{ + dev->gpio_regs[reg] = (dev->gpio_regs[reg] & ~(1 << bit)) | + (set << bit); +} + +static __inline void +fdc37c93x_do_write_alt(fdc37c93x_t *dev, int alt, int reg, int bit, int set) +{ + dev->alt_regs[alt][reg] = (dev->alt_regs[alt][reg] & ~(1 << bit)) | + (set << bit); +} + +static void +fdc37c93x_write_gp(fdc37c93x_t *dev, int reg, int bit, int set) +{ + uint8_t gp_func_reg = dev->ld_regs[0x08][gp_func_regs[reg][bit]]; + uint8_t gp_func; + + if (gp_func_reg & 0x02) + set = !set; + + if (!(gp_func_reg & 0x01)) switch (reg) { + default: + /* Do nothing, this GP does not exist. */ + break; + case 1: + switch (bit) { + default: + gp_func = (gp_func_reg >> 3) & 0x01; + if (gp_func == 0x00) + fdc37c93x_do_write_gp(dev, reg, bit, set); + else + fdc37c93x_do_write_alt(dev, 0, reg, bit, set); + break; + case 1: + gp_func = (gp_func_reg >> 3) & 0x03; + if (!(gp_func & 0x01)) { + if (gp_func & 0x02) { + set ? picint(1 << 13) : picintc(1 << 13); + fdc37c93x_do_write_alt(dev, 0, reg, bit, set); + } else + fdc37c93x_do_write_gp(dev, reg, bit, set); + } + break; + case 3: + gp_func = (gp_func_reg >> 3) & 0x01; + if (gp_func == 0x01) + /* TODO: Write to power LED if it's ever implemented. */ + fdc37c93x_do_write_alt(dev, 0, reg, bit, set); + else + fdc37c93x_do_write_gp(dev, reg, bit, set); + break; + case 6: + gp_func = (gp_func_reg >> 3) & 0x03; + switch (gp_func) { + case 0: + fdc37c93x_do_write_gp(dev, reg, bit, set); + break; + case 1 ... 3: + fdc37c93x_do_write_alt(dev, gp_func - 1, reg, bit, set); + break; + } + break; + } + break; + case 2: + switch (bit) { + default: + gp_func = (gp_func_reg >> 3) & 0x01; + if (gp_func == 0x00) + fdc37c93x_do_write_gp(dev, reg, bit, set); + else + fdc37c93x_do_write_alt(dev, 0, reg, bit, set); + break; + case 0: + gp_func = (gp_func_reg >> 3) & 0x03; + switch (gp_func) { + case 0: + fdc37c93x_do_write_gp(dev, reg, bit, set); + break; + case 1: + fdc37c93x_do_write_alt(dev, 0, reg, bit, set); + break; + case 2: + kbc_at_write_p(dev->kbc, 2, 0xfe, set); + break; + } + break; + case 1: case 2: + gp_func = (gp_func_reg >> 3) & 0x03; + switch (gp_func) { + case 0: + fdc37c93x_do_write_gp(dev, reg, bit, set); + break; + case 1: case 2: + fdc37c93x_do_write_alt(dev, gp_func - 1, reg, bit, set); + break; + } + break; + case 5: + gp_func = (gp_func_reg >> 3) & 0x01; + if (gp_func == 0x00) + fdc37c93x_do_write_gp(dev, reg, bit, set); + else + kbc_at_write_p(dev->kbc, 2, 0xfd, set << 1); + break; + case 6: case 7: + /* Do nothing, these bits do not exist. */ + break; + } + break; + case 4: + gp_func = (gp_func_reg >> 3) & 0x03; + switch (bit) { + default: + switch (gp_func) { + case 0: + fdc37c93x_do_write_alt(dev, 0, reg, bit, set); + break; + case 1: + fdc37c93x_do_write_gp(dev, reg, bit, set); + break; + } + break; + case 0: case 1: + switch (gp_func) { + case 0: + fdc_set_media_id(dev->fdc, bit ^ 1, set); + break; + case 1: + fdc37c93x_do_write_gp(dev, reg, bit, set); + break; + } + break; + case 6: + switch (gp_func) { + case 0: + fdc37c93x_do_write_alt(dev, 0, reg, bit, set); + break; + case 1: + fdc37c93x_do_write_gp(dev, reg, bit, set); + break; + case 2: + /* TODO: Write to power LED if it's ever implemented. */ + fdc37c93x_do_write_alt(dev, 1, reg, bit, set); + break; + case 3: + fdc37c93x_do_write_alt(dev, 2, reg, bit, set); + break; + } + break; + case 7: + switch (gp_func) { + case 0: + fdc37c93x_do_write_alt(dev, 0, reg, bit, set); + break; + case 1: + fdc37c93x_do_write_gp(dev, reg, bit, set); + break; + case 2: + fdc37c93x_do_write_alt(dev, 1, reg, bit, set); + if (!set) + smi_raise(); + break; + } + break; + } + break; + case 5: + gp_func = (gp_func_reg >> 3) & 0x03; + switch (bit) { + default: + break; + case 0: case 3: case 4: + switch (gp_func) { + case 0: + fdc37c93x_do_write_alt(dev, 0, reg, bit, set); + break; + case 1: + fdc37c93x_do_write_gp(dev, reg, bit, set); + break; + } + break; + case 1: + switch (gp_func) { + case 0: + fdc37c93x_do_write_alt(dev, 0, reg, bit, set); + if (set) + plat_power_off(); + break; + case 1: + fdc37c93x_do_write_gp(dev, reg, bit, set); + break; + } + break; + } + break; + case 6: + gp_func = (gp_func_reg >> 3) & 0x03; + switch (bit) { + default: + switch (gp_func) { + case 0: + fdc37c93x_do_write_alt(dev, 0, reg, bit, set); + break; + case 1: + fdc37c93x_do_write_gp(dev, reg, bit, set); + break; + case 2: + kbc_at_write_p(dev->kbc, 1, ~(1 << bit), set << bit); + break; + } + break; + case 0: + switch (gp_func) { + case 0: + fdc37c93x_do_write_alt(dev, 0, reg, bit, set); + break; + case 1: + fdc37c93x_do_write_gp(dev, reg, bit, set); + break; + case 2: + /* TODO: Write to power LED if it's ever implemented. */ + fdc37c93x_do_write_alt(dev, 1, reg, bit, set); + break; + } + break; + case 1: + switch (gp_func) { + case 0: + fdc37c93x_do_write_alt(dev, 0, reg, bit, set); + break; + case 1: + fdc37c93x_do_write_gp(dev, reg, bit, set); + break; + case 2: + fdc37c93x_do_write_alt(dev, 1, reg, bit, set); + break; + } + break; + } + break; + case 7: + gp_func = (gp_func_reg >> 3) & 0x03; + switch (bit) { + default: + switch (gp_func) { + case 0: + fdc37c93x_do_write_alt(dev, 0, reg, bit, set); + break; + case 1: + fdc37c93x_do_write_gp(dev, reg, bit, set); + break; + } + break; + } + break; + } +} + static uint8_t fdc37c93x_gpio_read(uint16_t port, void *priv) { const fdc37c93x_t *dev = (fdc37c93x_t *) priv; uint8_t ret = 0xff; - if (strcmp(machine_get_internal_name(), "vectra54")) - ret = dev->gpio_regs[port & 1]; + if (dev->locked) { + if (dev->is_compaq) + ret = fdc37c93x_read(port & 0x0001, priv); + } else if (port & 0x0001) switch (dev->gpio_reg) { + case 0x01: case 0x02: + ret = 0x00; + for (uint8_t i = 0; i < 8; i++) + ret |= fdc37c93x_read_gp(dev, dev->gpio_reg, i); + break; + case 0x03: + ret = dev->ld_regs[0x08][0xf4]; + break; + case 0x04 ... 0x07: + if (dev->chip_id >= FDC37C93X_FR) { + ret = 0x00; + for (uint8_t i = 0; i < 8; i++) + ret |= fdc37c93x_read_gp(dev, dev->gpio_reg, i); + } + break; + case 0x08 ... 0x0f: + if (dev->chip_id >= FDC37C93X_FR) + ret = dev->ld_regs[0x08][0xb0 + dev->gpio_reg - 0x08]; + break; + } else + ret = dev->gpio_reg; return ret; } @@ -139,8 +706,52 @@ fdc37c93x_gpio_write(uint16_t port, uint8_t val, void *priv) { fdc37c93x_t *dev = (fdc37c93x_t *) priv; - if (!(port & 1)) - dev->gpio_regs[0] = (dev->gpio_regs[0] & 0xfc) | (val & 0x03); + if (dev->locked) { + if (dev->is_compaq) + fdc37c93x_write(port & 0x0001, val, priv); + } else if (port & 0x0001) switch (dev->gpio_reg) { + case 0x01: case 0x02: + for (uint8_t i = 0; i < 8; i++) + fdc37c93x_write_gp(dev, dev->gpio_reg, i, val & (1 << i)); + break; + case 0x03: + if (dev->chip_id >= FDC37C93X_FR) + dev->ld_regs[0x08][0xf4] = val & 0xef; + else + dev->ld_regs[0x08][0xf4] = val & 0x0f; + break; + case 0x04 ... 0x07: + if (dev->chip_id >= FDC37C93X_FR) + for (uint8_t i = 0; i < 8; i++) + fdc37c93x_write_gp(dev, dev->gpio_reg, i, val & (1 << i)); + break; + case 0x08: case 0x0a: + case 0x0c: case 0x0e: + if (dev->chip_id >= FDC37C93X_FR) + dev->ld_regs[0x08][0xb0 + dev->gpio_reg - 0x08] = val; + break; + case 0x09: + if (dev->chip_id >= FDC37C93X_FR) + dev->ld_regs[0x08][0xb0 + dev->gpio_reg - 0x08] = val & 0xd3; + break; + case 0x0b: + if (dev->chip_id >= FDC37C93X_FR) + dev->ld_regs[0x08][0xb0 + dev->gpio_reg - 0x08] = val & 0x17; + break; + case 0x0d: + if (dev->chip_id == FDC37C93X_APM) + dev->ld_regs[0x08][0xb0 + dev->gpio_reg - 0x08] = val; + else if (dev->chip_id == FDC37C93X_FR) + dev->ld_regs[0x08][0xb0 + dev->gpio_reg - 0x08] = val & 0xbf; + break; + case 0x0f: + if (dev->chip_id == FDC37C93X_APM) + dev->ld_regs[0x08][0xb0 + dev->gpio_reg - 0x08] = val & 0x7f; + else if (dev->chip_id == FDC37C93X_FR) + dev->ld_regs[0x08][0xb0 + dev->gpio_reg - 0x08] = val & 0x3f; + break; + } else + dev->gpio_reg = val; } static void @@ -226,7 +837,14 @@ fdc37c93x_serial_handler(fdc37c93x_t *dev, const int uart) serial_setup(dev->uart[uart], dev->uart_base[uart], dev->ld_regs[uart_no][0x70]); } - serial_irq(dev->uart[uart], dev->ld_regs[uart_no][0x70]); + /* + TODO: If UART 2's own IRQ pin is also enabled when shared, + it should also be asserted. + */ + if ((dev->chip_id >= FDC37C93X_FR) && (dev->ld_regs[4][0xf0] & 0x80)) + serial_irq(dev->uart[uart], dev->ld_regs[4][0x70]); + else + serial_irq(dev->uart[uart], dev->ld_regs[uart_no][0x70]); } static void @@ -304,7 +922,8 @@ fdc37c93x_auxio_handler(fdc37c93x_t *dev) static void fdc37c93x_gpio_handler(fdc37c93x_t *dev) { - const uint8_t local_enable = !dev->locked && !!(dev->regs[0x03] & 0x80); + const uint8_t local_enable = !!(dev->regs[0x03] & 0x80) || + (dev->is_compaq && dev->locked); const uint16_t old_base = dev->gpio_base; dev->gpio_base = 0x0000; @@ -383,23 +1002,15 @@ static void fdc37c93x_write(uint16_t port, uint8_t val, void *priv) { fdc37c93x_t *dev = (fdc37c93x_t *) priv; - uint8_t index = (port & 1) ? 0 : 1; + uint8_t index = !(port & 1); uint8_t valxor; - /* Compaq Presario 4500: Unlock at FB, Register at EA, Data at EB, Lock at F9. */ - if (port == 0xea) - index = 1; - else if (port == 0xeb) - index = 0; - - if (port == 0xfb) { + if (port == 0x00fb) { fdc37c93x_state_change(dev, 1); dev->tries = 0; - return; - } else if (port == 0xf9) { + } else if (port == 0x00f9) fdc37c93x_state_change(dev, 0); - return; - } else if (index) { + else if (index) { if ((!dev->is_compaq) && (val == 0x55) && !dev->locked) { if (dev->tries) { fdc37c93x_state_change(dev, 1); @@ -407,338 +1018,480 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv) } else dev->tries++; } else if (dev->locked) { - if ((!dev->is_compaq) && (val == 0xaa)) { + if ((!dev->is_compaq) && (val == 0xaa)) fdc37c93x_state_change(dev, 0); - return; - } - dev->cur_reg = val; + else + dev->cur_reg = val; } else if ((!dev->is_compaq) && dev->tries) dev->tries = 0; - return; - } else { - if (dev->locked) { - if (dev->cur_reg < 48) { - valxor = val ^ dev->regs[dev->cur_reg]; - if ((val == 0x20) || (val == 0x21)) - return; - dev->regs[dev->cur_reg] = val; - } else { - uint8_t keep = 0x00; + } else if (dev->locked) { + if (dev->cur_reg < 0x30) { + valxor = val ^ dev->regs[dev->cur_reg]; - valxor = val ^ dev->ld_regs[dev->regs[7]][dev->cur_reg]; - if (((dev->cur_reg & 0xF0) == 0x70) && (dev->regs[7] < 4)) - return; - /* Block writes to some logical devices. */ - if (dev->regs[7] > 0x0a) - return; - else - switch (dev->regs[7]) { - // case 0x01: - // case 0x02: - // return; - case 0x06: - if (!dev->has_nvr) - return; - /* Bits 0 to 3 of logical device 6 (RTC) register F0h must stay set - once they are set. */ - else if (dev->cur_reg == 0xf0) - keep = dev->ld_regs[dev->regs[7]][dev->cur_reg] & 0x0f; - break; - case 0x09: - /* If we're on the FDC37C935, return as this is not a valid - logical device there. */ - if (!dev->is_apm && (dev->chip_id == 0x02)) - return; - break; - case 0x0a: - /* If we're not on the FDC37C931APM, return as this is not a - valid logical device there. */ - if (!dev->is_apm) - return; - break; - - default: - break; - } - dev->ld_regs[dev->regs[7]][dev->cur_reg] = val | keep; - } - } else - return; - } - - if (dev->cur_reg < 48) { - switch (dev->cur_reg) { - case 0x02: - if (val == 0x02) - fdc37c93x_state_change(dev, 0); - break; - case 0x03: - dev->regs[0x03] &= 0x83; - break; - case 0x22: - if (valxor & 0x01) - fdc37c93x_fdc_handler(dev); - if (valxor & 0x08) - fdc37c93x_lpt_handler(dev); - if (valxor & 0x10) - fdc37c93x_serial_handler(dev, 0); - if (valxor & 0x20) - fdc37c93x_serial_handler(dev, 1); - if ((valxor & 0x40) && (dev->chip_id != 0x02)) - fdc37c93x_access_bus_handler(dev); - break; - - case 0x27: - if (dev->chip_id != 0x02) - fdc37c93x_superio_handler(dev); - break; - - default: - break; - } - - return; - } - - switch (dev->regs[7]) { - case 0: - /* FDD */ switch (dev->cur_reg) { - case 0x30: - case 0x60: - case 0x61: - if ((dev->cur_reg == 0x30) && (val & 0x01)) - dev->regs[0x22] |= 0x01; - if (valxor) - fdc37c93x_fdc_handler(dev); + case 0x02: + dev->regs[dev->cur_reg] = val; + if (val == 0x02) + fdc37c93x_state_change(dev, 0); break; - case 0xF0: + case 0x03: + dev->regs[dev->cur_reg] = val & 0x83; + break; + case 0x07: case 0x26: + case 0x2e ... 0x2f: + dev->regs[dev->cur_reg] = val; + break; + case 0x22: + if (dev->chip_id >= FDC37C93X_FR) + dev->regs[dev->cur_reg] = val & 0x7f; + else + dev->regs[dev->cur_reg] = val & 0x6f; + if (valxor & 0x01) - fdc_update_enh_mode(dev->fdc, val & 0x01); - if (valxor & 0x10) - fdc_set_swap(dev->fdc, (val & 0x10) >> 4); - break; - case 0xF1: - if (valxor & 0xC) - fdc_update_densel_force(dev->fdc, (val & 0xc) >> 2); - break; - case 0xF2: - if (valxor & 0xC0) - fdc_update_rwc(dev->fdc, 3, (val & 0xc0) >> 6); - if (valxor & 0x30) - fdc_update_rwc(dev->fdc, 2, (val & 0x30) >> 4); - if (valxor & 0x0C) - fdc_update_rwc(dev->fdc, 1, (val & 0x0c) >> 2); - if (valxor & 0x03) - fdc_update_rwc(dev->fdc, 0, (val & 0x03)); - break; - case 0xF4: - if (valxor & 0x18) - fdc_update_drvrate(dev->fdc, 0, (val & 0x18) >> 3); - break; - case 0xF5: - if (valxor & 0x18) - fdc_update_drvrate(dev->fdc, 1, (val & 0x18) >> 3); - break; - case 0xF6: - if (valxor & 0x18) - fdc_update_drvrate(dev->fdc, 2, (val & 0x18) >> 3); - break; - case 0xF7: - if (valxor & 0x18) - fdc_update_drvrate(dev->fdc, 3, (val & 0x18) >> 3); - break; - - default: - break; - } - break; - case 3: - /* Parallel port */ - switch (dev->cur_reg) { - case 0x30: - case 0x60: - case 0x61: - case 0x70: - if ((dev->cur_reg == 0x30) && (val & 0x01)) - dev->regs[0x22] |= 0x08; - if (valxor) + fdc37c93x_fdc_handler(dev); + if (valxor & 0x08) fdc37c93x_lpt_handler(dev); - break; - - default: - break; - } - break; - case 4: - /* Serial port 1 */ - switch (dev->cur_reg) { - case 0x30: - case 0x60: - case 0x61: - case 0x70: - if ((dev->cur_reg == 0x30) && (val & 0x01)) - dev->regs[0x22] |= 0x10; - if (valxor) + if (valxor & 0x10) fdc37c93x_serial_handler(dev, 0); - break; - - default: - break; - } - break; - case 5: - /* Serial port 2 */ - switch (dev->cur_reg) { - case 0x30: - case 0x60: - case 0x61: - case 0x70: - if ((dev->cur_reg == 0x30) && (val & 0x01)) - dev->regs[0x22] |= 0x20; - if (valxor) + if (valxor & 0x20) fdc37c93x_serial_handler(dev, 1); - break; - - default: - break; - } - break; - case 6: - /* RTC/NVR */ - if (!dev->has_nvr) - return; - switch (dev->cur_reg) { - case 0x30: - if (valxor) { - fdc37c93x_nvr_pri_handler(dev); - if (dev->chip_id != 0x02) - fdc37c93x_nvr_sec_handler(dev); - } - break; - case 0x62: - case 0x63: - if ((dev->chip_id != 0x02) && valxor) - fdc37c93x_nvr_sec_handler(dev); - break; - case 0xf0: - if (valxor) { - nvr_lock_set(0x80, 0x20, !!(dev->ld_regs[6][dev->cur_reg] & 0x01), dev->nvr); - nvr_lock_set(0xa0, 0x20, !!(dev->ld_regs[6][dev->cur_reg] & 0x02), dev->nvr); - nvr_lock_set(0xc0, 0x20, !!(dev->ld_regs[6][dev->cur_reg] & 0x04), dev->nvr); - nvr_lock_set(0xe0, 0x20, !!(dev->ld_regs[6][dev->cur_reg] & 0x08), dev->nvr); - if ((dev->chip_id == 0x02) && (dev->ld_regs[6][dev->cur_reg] & 0x80)) - nvr_bank_set(0, 1, dev->nvr); - else if ((dev->chip_id != 0x02) && (dev->ld_regs[6][dev->cur_reg] & 0x80)) - switch ((dev->ld_regs[6][dev->cur_reg] >> 4) & 0x07) { - default: - case 0x00: - nvr_bank_set(0, 0xff, dev->nvr); - nvr_bank_set(1, 1, dev->nvr); - break; - case 0x01: - nvr_bank_set(0, 0, dev->nvr); - nvr_bank_set(1, 1, dev->nvr); - break; - case 0x02: - case 0x04: - nvr_bank_set(0, 0xff, dev->nvr); - nvr_bank_set(1, 0xff, dev->nvr); - break; - case 0x03: - case 0x05: - nvr_bank_set(0, 0, dev->nvr); - nvr_bank_set(1, 0xff, dev->nvr); - break; - case 0x06: - nvr_bank_set(0, 0xff, dev->nvr); - nvr_bank_set(1, 2, dev->nvr); - break; - case 0x07: - nvr_bank_set(0, 0, dev->nvr); - nvr_bank_set(1, 2, dev->nvr); - break; - } - else { - nvr_bank_set(0, 0, dev->nvr); - if (dev->chip_id != 0x02) - nvr_bank_set(1, 0xff, dev->nvr); - } - - fdc37c93x_nvr_pri_handler(dev); - if (dev->chip_id != 0x02) - fdc37c93x_nvr_sec_handler(dev); - } - break; - - default: - break; - } - break; - case 7: - /* Keyboard */ - switch (dev->cur_reg) { - case 0x30: - if (valxor) - fdc37c93x_kbc_handler(dev); - break; - - default: - break; - } - break; - case 8: - /* Auxiliary I/O */ - switch (dev->cur_reg) { - case 0x30: - case 0x60: - case 0x61: - case 0x70: - if (valxor) - fdc37c93x_auxio_handler(dev); - break; - - default: - break; - } - break; - case 9: - /* Access bus (FDC37C932FR and FDC37C931APM only) */ - switch (dev->cur_reg) { - case 0x30: - case 0x60: - case 0x61: - case 0x70: - if ((dev->cur_reg == 0x30) && (val & 0x01)) - dev->regs[0x22] |= 0x40; - if (valxor) + if ((dev->chip_id >= FDC37C93X_FR) && (valxor & 0x40)) fdc37c93x_access_bus_handler(dev); break; + case 0x23: + if (dev->chip_id >= FDC37C93X_FR) + dev->regs[dev->cur_reg] = val & 0x7f; + else + dev->regs[dev->cur_reg] = val & 0x6f; + break; + case 0x24: + if (dev->chip_id >= FDC37C93X_FR) + dev->regs[dev->cur_reg] = val & 0xcf; + else + dev->regs[dev->cur_reg] = val & 0xcc; + + if ((dev->chip_id >= FDC37C93X_FR) && (valxor & 0x01)) { + serial_set_clock_src(dev->uart[0], (val & 0x01) ? + 48000000.0 : 24000000.0); + serial_set_clock_src(dev->uart[1], (val & 0x01) ? + 48000000.0 : 24000000.0); + } + break; + case 0x27: + if (dev->chip_id >= FDC37C93X_FR) { + dev->regs[dev->cur_reg] = val; + + fdc37c93x_superio_handler(dev); + } + break; + case 0x28: + if (dev->chip_id >= FDC37C93X_FR) + dev->regs[dev->cur_reg] = val & 0x1f; + break; default: break; } - break; - case 10: - /* Access bus (FDC37C931APM only) */ - switch (dev->cur_reg) { - case 0x30: - case 0x60: - case 0x61: - case 0x62: - case 0x63: - case 0x70: - if (valxor) - fdc37c93x_acpi_handler(dev); - break; + } else { + valxor = val ^ dev->ld_regs[dev->regs[7]][dev->cur_reg]; - default: + if ((dev->regs[7] <= dev->max_ld) && ((dev->regs[7] != 0x08) || + (dev->cur_reg < 0xb0) || (dev->cur_reg > 0xdf) || + (dev->chip_id >= FDC37C93X_FR))) switch (dev->regs[7]) { + case 0x00: /* FDD */ + switch (dev->cur_reg) { + case 0x30: + case 0x60: case 0x61: + case 0x70: + case 0x74: + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val; + + if ((dev->cur_reg == 0x30) && (val & 0x01)) + dev->regs[0x22] |= 0x01; + if (valxor) + fdc37c93x_fdc_handler(dev); + break; + case 0xf0: + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val & 0x1f; + + if (valxor & 0x01) + fdc_update_enh_mode(dev->fdc, val & 0x01); + if (valxor & 0x10) + fdc_set_swap(dev->fdc, (val & 0x10) >> 4); + break; + case 0xf1: + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val & 0xfc; + + if (valxor & 0x0c) + fdc_update_densel_force(dev->fdc, (val & 0xc) >> 2); + break; + case 0xf2: + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val; + + if (valxor & 0xc0) + fdc_update_rwc(dev->fdc, 3, (val & 0xc0) >> 6); + if (valxor & 0x30) + fdc_update_rwc(dev->fdc, 2, (val & 0x30) >> 4); + if (valxor & 0x0c) + fdc_update_rwc(dev->fdc, 1, (val & 0x0c) >> 2); + if (valxor & 0x03) + fdc_update_rwc(dev->fdc, 0, (val & 0x03)); + break; + case 0xf4 ... 0xf7: + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val & 0x5b; + + if (valxor & 0x18) + fdc_update_drvrate(dev->fdc, dev->cur_reg - 0xf4, + (val & 0x18) >> 3); + break; + } + break; + case 0x01: /* IDE1 */ + switch (dev->cur_reg) { + case 0x30: + case 0x60: case 0x61: + case 0x62: case 0x63: + case 0x70: + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val; + + if ((dev->cur_reg == 0x30) && (val & 0x01)) + dev->regs[0x22] |= 0x02; + break; + case 0xf0: case 0xf1: + if (dev->chip_id >= FDC37C93X_FR) + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val & 0x1f; + else if (dev->cur_reg == 0xf0) + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val; + break; + } + break; + case 0x02: /* IDE2 */ + switch (dev->cur_reg) { + case 0x30: + case 0x60: case 0x61: + case 0x62: case 0x63: + case 0x70: + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val; + + if ((dev->cur_reg == 0x30) && (val & 0x01)) + dev->regs[0x22] |= 0x04; + break; + case 0xf0: + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val & 0x01; + break; + } + break; + case 0x03: /* Parallel Port */ + switch (dev->cur_reg) { + case 0x30: + case 0x60: case 0x61: + case 0x70: + case 0x74: + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val; + + if ((dev->cur_reg == 0x30) && (val & 0x01)) + dev->regs[0x22] |= 0x08; + if (valxor) + fdc37c93x_lpt_handler(dev); + break; + case 0xf0: + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val; + break; + case 0xf1: + if (dev->chip_id >= FDC37C93X_FR) + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val & 0x03; + break; + } + break; + case 0x04: /* Serial port 1 */ + switch (dev->cur_reg) { + case 0x30: + case 0x60: case 0x61: + case 0x70: + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val; + + if ((dev->cur_reg == 0x30) && (val & 0x01)) + dev->regs[0x22] |= 0x10; + if (valxor) + fdc37c93x_serial_handler(dev, 0); + break; + /* TODO: Bit 0 = MIDI Mode, Bit 1 = High speed. */ + case 0xf0: + if (dev->chip_id >= FDC37C93X_FR) { + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val & 0x83; + } else + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val & 0x03; + + if (valxor & 0x83) { + fdc37c93x_serial_handler(dev, 0); + fdc37c93x_serial_handler(dev, 1); + } + break; + } + break; + case 0x05: /* Serial port 2 */ + switch (dev->cur_reg) { + case 0x30: + case 0x60: case 0x61: + case 0x62: case 0x63: + case 0x70: + case 0x74: + if (((dev->cur_reg != 0x62) && (dev->cur_reg != 0x63)) || + (dev->chip_id == FDC37C93X_FR)) { + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val; + + if ((dev->cur_reg == 0x30) && (val & 0x01)) + dev->regs[0x22] |= 0x20; + if (valxor) + fdc37c93x_serial_handler(dev, 1); + } + break; + /* TODO: Bit 0 = MIDI Mode, Bit 1 = High speed. */ + case 0xf0: + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val & 0x03; + + if (valxor & 0x03) { + fdc37c93x_serial_handler(dev, 0); + fdc37c93x_serial_handler(dev, 1); + } + break; + case 0xf1: + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val & 0x7f; + break; + case 0xf2: + if (dev->chip_id >= FDC37C93X_FR) + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val; + break; + } + break; + case 0x06: /* RTC */ + switch (dev->cur_reg) { + case 0x30: + // case 0x60: case 0x61: + case 0x62: case 0x63: + case 0x70: + if (((dev->cur_reg != 0x62) && (dev->cur_reg != 0x63)) || + (dev->chip_id >= FDC37C93X_FR)) { + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val; + + if (valxor) { + fdc37c93x_nvr_pri_handler(dev); + + if (dev->chip_id >= FDC37C93X_FR) + fdc37c93x_nvr_sec_handler(dev); + } + } + break; + case 0xf0: + if (dev->chip_id >= FDC37C93X_FR) + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val; + else + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val & 0x8f; + + if (valxor) { + nvr_lock_set(0x80, 0x20, !!(dev->ld_regs[6][dev->cur_reg] & 0x01), dev->nvr); + nvr_lock_set(0xa0, 0x20, !!(dev->ld_regs[6][dev->cur_reg] & 0x02), dev->nvr); + nvr_lock_set(0xc0, 0x20, !!(dev->ld_regs[6][dev->cur_reg] & 0x04), dev->nvr); + nvr_lock_set(0xe0, 0x20, !!(dev->ld_regs[6][dev->cur_reg] & 0x08), dev->nvr); + if (dev->ld_regs[6][dev->cur_reg] & 0x80) { + if (dev->chip_id == FDC37C93X_NORMAL) + nvr_bank_set(0, 1, dev->nvr); + else switch ((dev->ld_regs[6][dev->cur_reg] >> 4) & 0x07) { + case 0x00: + default: + nvr_bank_set(0, 0xff, dev->nvr); + nvr_bank_set(1, 1, dev->nvr); + break; + case 0x01: + nvr_bank_set(0, 0, dev->nvr); + nvr_bank_set(1, 1, dev->nvr); + break; + case 0x02: case 0x04: + nvr_bank_set(0, 0xff, dev->nvr); + nvr_bank_set(1, 0xff, dev->nvr); + break; + case 0x03: case 0x05: + nvr_bank_set(0, 0, dev->nvr); + nvr_bank_set(1, 0xff, dev->nvr); + break; + case 0x06: + nvr_bank_set(0, 0xff, dev->nvr); + nvr_bank_set(1, 2, dev->nvr); + break; + case 0x07: + nvr_bank_set(0, 0, dev->nvr); + nvr_bank_set(1, 2, dev->nvr); + break; + } + } else { + nvr_bank_set(0, 0, dev->nvr); + if (dev->chip_id >= FDC37C93X_FR) + nvr_bank_set(1, 0xff, dev->nvr); + } + + fdc37c93x_nvr_pri_handler(dev); + if (dev->chip_id >= FDC37C93X_FR) + fdc37c93x_nvr_sec_handler(dev); + } + break; + case 0xf1: + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val & 0x1f; + break; + case 0xf2: case 0xf3: + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val; + break; + case 0xf4: + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val & 0x83; + break; + } + break; + case 0x07: /* Keyboard */ + switch (dev->cur_reg) { + case 0x30: + case 0x70: case 0x71: + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val; + + if (valxor) + fdc37c93x_kbc_handler(dev); + break; + case 0xf0: + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val & 0x87; + break; + } + break; + case 0x08: /* Aux. I/O */ + switch (dev->cur_reg) { + case 0x30: + case 0x60: case 0x61: + case 0x62: case 0x63: + case 0x70: + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val; + + if (valxor) + fdc37c93x_auxio_handler(dev); + break; + case 0xb0: case 0xb2: + case 0xb4: case 0xb6: + case 0xe0: case 0xe1: + case 0xe9: case 0xf2: + case 0xf3: + case 0xc0 ... 0xc9: + case 0xcb ... 0xcc: + case 0xd0 ... 0xdf: + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val; + break; + case 0xb1: + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val & 0xd3; + break; + case 0xb3: + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val & 0x17; + break; + case 0xb5: + if (dev->chip_id == FDC37C93X_APM) + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val; + else + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val & 0xbf; + break; + case 0xb7: + if (dev->chip_id == FDC37C93X_APM) + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val & 0x7f; + else + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val & 0x3f; + break; + case 0xb8: + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val & 0x3f; + break; + case 0x18: + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val & 0x18; + break; + case 0xe2 ... 0xe5: + case 0xe7: + case 0xeb ... 0xed: + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val & 0x0f; + break; + case 0xe6: case 0xe8: + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val & 0x1f; + break; + case 0xea: + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val & 0x9f; + break; + case 0xef: + if (dev->chip_id >= FDC37C93X_FR) + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val & 0xf8; + break; + case 0xf1: + if (dev->chip_id >= FDC37C93X_FR) + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val & 0x83; + else + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val & 0x03; + break; + case 0xf4: + if (dev->chip_id >= FDC37C93X_FR) + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val & 0xef; + else + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val & 0x0f; + break; + case 0xf6: + if (dev->chip_id >= FDC37C93X_FR) + for (uint8_t i = 0; i < 8; i++) + fdc37c93x_write_gp(dev, 1, i, val & (1 << i)); + break; + case 0xf7: + if (dev->chip_id >= FDC37C93X_FR) + for (uint8_t i = 0; i < 8; i++) + fdc37c93x_write_gp(dev, 2, i, val & (1 << i)); + break; + case 0xf8: + if (dev->chip_id >= FDC37C93X_FR) + for (uint8_t i = 0; i < 8; i++) + fdc37c93x_write_gp(dev, 4, i, val & (1 << i)); + break; + case 0xf9: + if (dev->chip_id >= FDC37C93X_FR) + for (uint8_t i = 0; i < 8; i++) + fdc37c93x_write_gp(dev, 5, i, val & (1 << i)); + break; + case 0xfa: + if (dev->chip_id >= FDC37C93X_FR) + for (uint8_t i = 0; i < 8; i++) + fdc37c93x_write_gp(dev, 6, i, val & (1 << i)); + break; + case 0xfb: + if (dev->chip_id >= FDC37C93X_FR) + for (uint8_t i = 0; i < 8; i++) + fdc37c93x_write_gp(dev, 7, i, val & (1 << i)); + break; + } + break; + case 0x09: /* Access.Bus */ + switch (dev->cur_reg) { + case 0x30: + case 0x60: case 0x61: + case 0x70: + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val; + + if ((dev->cur_reg == 0x30) && (val & 0x01)) + dev->regs[0x22] |= 0x40; + if (valxor) + fdc37c93x_access_bus_handler(dev); + break; + } + break; + case 0x0a: /* ACPI */ + switch (dev->cur_reg) { + case 0x30: + case 0x60: case 0x61: + case 0x62: case 0x63: + case 0x70: + dev->ld_regs[dev->regs[7]][dev->cur_reg] = val; + + if (valxor) + fdc37c93x_acpi_handler(dev); + break; + } break; } - break; - - default: - break; + } } } @@ -764,11 +1517,58 @@ fdc37c93x_read(uint16_t port, void *priv) ret = dev->chip_id; else ret = dev->regs[dev->cur_reg]; - } else { - if ((dev->regs[7] == 0) && (dev->cur_reg == 0xF2)) { - ret = (fdc_get_rwc(dev->fdc, 0) | (fdc_get_rwc(dev->fdc, 1) << 2) | (fdc_get_rwc(dev->fdc, 2) << 4) | (fdc_get_rwc(dev->fdc, 3) << 6)); - } else + } else if (dev->regs[7] <= dev->max_ld) { + if ((dev->regs[7] == 0x00) && (dev->cur_reg == 0xf2)) + ret = (fdc_get_rwc(dev->fdc, 0) | (fdc_get_rwc(dev->fdc, 1) << 2) | + (fdc_get_rwc(dev->fdc, 2) << 4) | (fdc_get_rwc(dev->fdc, 3) << 6)); + else if ((dev->regs[7] != 0x06) || (dev->cur_reg != 0xf3)) ret = dev->ld_regs[dev->regs[7]][dev->cur_reg]; + else if ((dev->regs[7] == 0x08) && (dev->cur_reg >= 0xf6) && + (dev->cur_reg <= 0xfb) && + (dev->chip_id >= FDC37C93X_FR)) switch (dev->cur_reg) { + case 0xf6: + if (dev->chip_id >= FDC37C93X_FR) { + ret = 0x00; + for (uint8_t i = 0; i < 8; i++) + ret |= fdc37c93x_read_gp(dev, 1, i); + } + break; + case 0xf7: + if (dev->chip_id >= FDC37C93X_FR) { + ret = 0x00; + for (uint8_t i = 0; i < 8; i++) + ret |= fdc37c93x_read_gp(dev, 2, i); + } + break; + case 0xf8: + if (dev->chip_id >= FDC37C93X_FR) { + ret = 0x00; + for (uint8_t i = 0; i < 8; i++) + ret |= fdc37c93x_read_gp(dev, 4, i); + } + break; + case 0xf9: + if (dev->chip_id >= FDC37C93X_FR) { + ret = 0x00; + for (uint8_t i = 0; i < 8; i++) + ret |= fdc37c93x_read_gp(dev, 5, i); + } + break; + case 0xfa: + if (dev->chip_id >= FDC37C93X_FR) { + ret = 0x00; + for (uint8_t i = 0; i < 8; i++) + ret |= fdc37c93x_read_gp(dev, 6, i); + } + break; + case 0xfb: + if (dev->chip_id >= FDC37C93X_FR) { + ret = 0x00; + for (uint8_t i = 0; i < 8; i++) + ret |= fdc37c93x_read_gp(dev, 7, i); + } + break; + } } } } @@ -786,10 +1586,12 @@ fdc37c93x_reset(fdc37c93x_t *dev) dev->regs[0x21] = 0x01; dev->regs[0x22] = 0x39; dev->regs[0x24] = 0x04; - dev->regs[0x26] = dev->port_370 ? 0x70 : 0xf0; + if (dev->chip_id >= FDC37C93X_FR) + dev->regs[0x26] = dev->port_370 ? 0x70 : 0xf0; dev->regs[0x27] = 0x03; - memset(dev->ld_regs, 0x00, sizeof(dev->ld_regs)); + for (uint8_t i = 0; i <= 0x0a; i++) + memset(dev->ld_regs[i], 0x00, 256); /* Logical device 0: FDD */ dev->ld_regs[0x00][0x30] = 0x00; @@ -807,7 +1609,8 @@ fdc37c93x_reset(fdc37c93x_t *dev) dev->ld_regs[0x01][0x62] = 0x03; dev->ld_regs[0x01][0x63] = 0xf6; dev->ld_regs[0x01][0x70] = 0x0e; - dev->ld_regs[0x01][0xf0] = 0x0c; + if (dev->chip_id >= FDC37C93X_FR) + dev->ld_regs[0x01][0xf0] = 0x0c; /* Logical device 2: IDE2 */ dev->ld_regs[0x02][0x30] = 0x00; @@ -840,7 +1643,8 @@ fdc37c93x_reset(fdc37c93x_t *dev) dev->ld_regs[0x05][0x70] = 0x03; dev->ld_regs[0x05][0x74] = 0x04; dev->ld_regs[0x05][0xf1] = 0x02; - dev->ld_regs[0x05][0xf2] = 0x03; + if (dev->chip_id >= FDC37C93X_FR) + dev->ld_regs[0x05][0xf2] = 0x03; serial_irq(dev->uart[1], dev->ld_regs[5][0x70]); /* Logical device 6: RTC */ @@ -858,16 +1662,34 @@ fdc37c93x_reset(fdc37c93x_t *dev) dev->ld_regs[0x08][0x30] = 0x00; dev->ld_regs[0x08][0x60] = 0x00; dev->ld_regs[0x08][0x61] = 0x00; + if (dev->chip_id >= FDC37C93X_FR) { + dev->ld_regs[0x08][0xb1] = 0x80; + dev->ld_regs[0x08][0xc0] = 0x01; + dev->ld_regs[0x08][0xc1] = 0x01; + dev->ld_regs[0x08][0xc5] = 0x01; + dev->ld_regs[0x08][0xc6] = 0x01; + dev->ld_regs[0x08][0xc7] = 0x01; + dev->ld_regs[0x08][0xc8] = 0x01; + dev->ld_regs[0x08][0xc9] = 0x80; + dev->ld_regs[0x08][0xcb] = 0x01; + dev->ld_regs[0x08][0xcc] = 0x01; + memset(&(dev->ld_regs[0x08][0xd0]), 0x01, 16); + } + memset(&(dev->ld_regs[0x08][0xe0]), 0x01, 14); /* Logical device 9: ACCESS.bus */ - dev->ld_regs[0x09][0x30] = 0x00; - dev->ld_regs[0x09][0x60] = 0x00; - dev->ld_regs[0x09][0x61] = 0x00; + if (dev->chip_id >= FDC37C93X_FR) { + dev->ld_regs[0x09][0x30] = 0x00; + dev->ld_regs[0x09][0x60] = 0x00; + dev->ld_regs[0x09][0x61] = 0x00; + } /* Logical device A: ACPI */ - dev->ld_regs[0x0a][0x30] = 0x00; - dev->ld_regs[0x0a][0x60] = 0x00; - dev->ld_regs[0x0a][0x61] = 0x00; + if (dev->chip_id == FDC37C93X_APM) { + dev->ld_regs[0x0a][0x30] = 0x00; + dev->ld_regs[0x0a][0x60] = 0x00; + dev->ld_regs[0x0a][0x61] = 0x00; + } fdc37c93x_gpio_handler(dev); fdc37c93x_lpt_handler(dev); @@ -899,6 +1721,62 @@ fdc37c93x_reset(fdc37c93x_t *dev) if (dev->chip_id != 0x02) fdc37c93x_superio_handler(dev); + if (dev->chip_id >= FDC37C93X_FR) { + serial_set_clock_src(dev->uart[0], 24000000.0); + serial_set_clock_src(dev->uart[1], 24000000.0); + } + + memset(dev->gpio_regs, 0xff, 256); + memset(dev->gpio_pulldn, 0xff, 8); + + /* Acer V62X requires bit 0 to be clear to not be stuck in "clear password" mode. */ + if (!strcmp(machine_get_internal_name(), "vectra54")) { + dev->gpio_pulldn[1] = 0x40; + + /* + HP Vectra VL/5 Series 4 GPIO + (TODO: Find how multipliers > 3.0 are defined): + + Bit 6: 1 = can boot, 0 = no; + Bit 7, 1 = multiplier (00 = 2.5, 01 = 2.0, + 10 = 3.0, 11 = 1.5); + Bit 5, 4 = bus speed (00 = 50 MHz, 01 = 66 MHz, + 10 = 60 MHz, 11 = ????): + Bit 7, 5, 4, 1: 0000 = 125 MHz, 0010 = 166 MHz, + 0100 = 150 MHz, 0110 = ??? MHz; + 0001 = 100 MHz, 0011 = 133 MHz, + 0101 = 120 MHz, 0111 = ??? MHz; + 1000 = 150 MHz, 1010 = 200 MHz, + 1100 = 180 MHz, 1110 = ??? MHz; + 1001 = 75 MHz, 1011 = 100 MHz, + 1101 = 90 MHz, 1111 = ??? MHz + */ + if (cpu_busspeed <= 40000000) + dev->gpio_pulldn[1] |= 0x30; + else if ((cpu_busspeed > 40000000) && (cpu_busspeed <= 50000000)) + dev->gpio_pulldn[1] |= 0x00; + else if ((cpu_busspeed > 50000000) && (cpu_busspeed <= 60000000)) + dev->gpio_pulldn[1] |= 0x20; + else if (cpu_busspeed > 60000000) + dev->gpio_pulldn[1] |= 0x10; + + if (cpu_dmulti <= 1.5) + dev->gpio_pulldn[1] |= 0x82; + else if ((cpu_dmulti > 1.5) && (cpu_dmulti <= 2.0)) + dev->gpio_pulldn[1] |= 0x02; + else if ((cpu_dmulti > 2.0) && (cpu_dmulti <= 2.5)) + dev->gpio_pulldn[1] |= 0x00; + else if (cpu_dmulti > 2.5) + dev->gpio_pulldn[1] |= 0x80; + } else if (!strcmp(machine_get_internal_name(), "acerv62x")) + dev->gpio_pulldn[1] = 0xfe; + else + dev->gpio_pulldn[1] = (dev->chip_id == 0x30) ? 0xff : 0xfd; + + if (strstr(machine_get_internal_name(), "acer") != NULL) + /* Bit 2 on the Acer V35N is the text/graphics toggle, bits 1 and 3 = ????. */ + dev->gpio_pulldn[2] = 0x10; + dev->locked = 0; } @@ -920,41 +1798,59 @@ fdc37c93x_init(const device_t *info) dev->uart[0] = device_add_inst(&ns16550_device, 1); dev->uart[1] = device_add_inst(&ns16550_device, 2); - dev->chip_id = info->local & 0xff; - dev->is_apm = (info->local >> 8) & 0x01; - dev->is_compaq = (info->local >> 8) & 0x02; - dev->has_nvr = !((info->local >> 8) & 0x04); - dev->port_370 = ((info->local >> 8) & 0x08); + dev->chip_id = info->local & FDC37C93X_CHIP_ID; + dev->kbc_type = info->local & FDC37C93X_KBC; - dev->gpio_regs[0] = 0xff; -#if 0 - dev->gpio_regs[1] = (info->local == 0x0030) ? 0xff : 0xfd; -#endif - dev->gpio_regs[1] = (dev->chip_id == 0x30) ? 0xff : 0xfd; + dev->is_apm = (dev->chip_id == FDC37C93X_APM); + dev->is_compaq = (dev->kbc_type == FDC37C931); + + dev->has_nvr = !(info->local & FDC37C93X_NO_NVR); + dev->port_370 = !!(info->local & FDC37C93X_370); if (dev->has_nvr) { - dev->nvr = device_add(&at_nvr_device); + dev->nvr = device_add(&amstrad_megapc_nvr_device); nvr_bank_set(0, 0, dev->nvr); nvr_bank_set(1, 0xff, dev->nvr); } - if (dev->is_apm || (dev->chip_id == 0x03)) - dev->access_bus = device_add(&access_bus_device); + dev->max_ld = 8; - if (dev->is_apm) + if (dev->chip_id >= FDC37C93X_FR) { + dev->access_bus = device_add(&access_bus_device); + dev->max_ld++; + } + + if (dev->chip_id == FDC37C93X_APM) { dev->acpi = device_add(&acpi_smc_device); + dev->max_ld++; + } if (dev->is_compaq) { - io_sethandler(0x0ea, 0x0002, - fdc37c93x_read, NULL, NULL, fdc37c93x_write, NULL, NULL, dev); io_sethandler(0x0f9, 0x0001, fdc37c93x_read, NULL, NULL, fdc37c93x_write, NULL, NULL, dev); io_sethandler(0x0fb, 0x0001, fdc37c93x_read, NULL, NULL, fdc37c93x_write, NULL, NULL, dev); } - dev->kbc = device_add(&keyboard_ps2_ami_pci_device); + switch (dev->kbc_type) { + case FDC37C931: + dev->kbc = device_add(&keyboard_ps2_compaq_device); + break; + case FDC37C932: + dev->kbc = device_add(&keyboard_ps2_intel_ami_pci_device); + break; + case FDC37C933: + default: + dev->kbc = device_add(&keyboard_ps2_pci_device); + break; + case FDC37C935: + dev->kbc = device_add(&keyboard_ps2_phoenix_device); + break; + case FDC37C937: + dev->kbc = device_add(&keyboard_ps2_phoenix_pci_device); + break; + } /* Set the defaults here so the ports can be removed by fdc37c93x_reset(). */ dev->fdc_base = 0x03f0; @@ -978,109 +1874,11 @@ fdc37c93x_init(const device_t *info) return dev; } -const device_t fdc37c931apm_device = { - .name = "SMC FDC37C931APM Super I/O", - .internal_name = "fdc37c931apm", +const device_t fdc37c93x_device = { + .name = "SMC FDC37C93x Super I/O", + .internal_name = "fdc37c93x", .flags = 0, - .local = 0x130, /* Share the same ID with the 932QF. */ - .init = fdc37c93x_init, - .close = fdc37c93x_close, - .reset = NULL, - .available = NULL, - .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL -}; - -const device_t fdc37c931apm_compaq_device = { - .name = "SMC FDC37C931APM Super I/O (Compaq Presario 4500)", - .internal_name = "fdc37c931apm_compaq", - .flags = 0, - .local = 0x330, /* Share the same ID with the 932QF. */ - .init = fdc37c93x_init, - .close = fdc37c93x_close, - .reset = NULL, - .available = NULL, - .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL -}; - -const device_t fdc37c932_device = { - .name = "SMC FDC37C932 Super I/O", - .internal_name = "fdc37c932", - .flags = 0, - .local = 0x02, - .init = fdc37c93x_init, - .close = fdc37c93x_close, - .reset = NULL, - .available = NULL, - .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL -}; - -const device_t fdc37c932fr_device = { - .name = "SMC FDC37C932FR Super I/O", - .internal_name = "fdc37c932fr", - .flags = 0, - .local = 0x03, - .init = fdc37c93x_init, - .close = fdc37c93x_close, - .reset = NULL, - .available = NULL, - .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL -}; - -const device_t fdc37c932qf_device = { - .name = "SMC FDC37C932QF Super I/O", - .internal_name = "fdc37c932qf", - .flags = 0, - .local = 0x30, - .init = fdc37c93x_init, - .close = fdc37c93x_close, - .reset = NULL, - .available = NULL, - .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL -}; - -const device_t fdc37c935_device = { - .name = "SMC FDC37C935 Super I/O", - .internal_name = "fdc37c935", - .flags = 0, - .local = 0x02, - .init = fdc37c93x_init, - .close = fdc37c93x_close, - .reset = NULL, - .available = NULL, - .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL -}; - -const device_t fdc37c935_370_device = { - .name = "SMC FDC37C935 Super I/O (Port 370h)", - .internal_name = "fdc37c935_370", - .flags = 0, - .local = 0x802, - .init = fdc37c93x_init, - .close = fdc37c93x_close, - .reset = NULL, - .available = NULL, - .speed_changed = NULL, - .force_redraw = NULL, - .config = NULL -}; - -const device_t fdc37c935_no_nvr_device = { - .name = "SMC FDC37C935 Super I/O", - .internal_name = "fdc37c935", - .flags = 0, - .local = 0x402, + .local = 0, .init = fdc37c93x_init, .close = fdc37c93x_close, .reset = NULL,