claunia/86Box
1
0
Fork 0
Code Issues Pull Requests Actions 3 Packages Projects Releases Wiki Activity

DMA: Implemented autoinit mode in the PS/2 MCA side (although the bit is undocumented in said side, but documented in the ISA/PCI side).

Browse Source 
Networking: Added the WD8013EP/A MCA nic, which is more supported than the WD80x3ET/A plus an initial ram size configuration before POS configuration.
Sound: Added the Reply MCA OEM of SB16 with its own MCA POS ID and properly implemented the IRQ's and DMA's of the AdLib Gold in its EEPROM plus an initial configurable setting for them and an initial DRQ implementation into said card.
This commit is contained in:
TC1995
2022-07-23 23:54:42 +02:00
parent b20dcf2ee1
commit 02874f2ed2
8 changed files with 414 additions and 32 deletions
Download Patch File Download Diff File Expand all files Collapse all files

124
src/sound/snd_adlibgold.c
View File

@@ -20,6 +20,7 @@
typedef struct adgold_t {
int adgold_irq_status;
int irq, dma, hdma;
uint8_t adgold_eeprom[0x1a];
@@ -157,7 +158,7 @@ adgold_update_irq_status(adgold_t *adgold)
adgold->adgold_status = temp;
if ((adgold->adgold_status ^ 0xf) && !adgold->adgold_irq_status) {
picint(0x80);
picint(1 << adgold->irq);
}
adgold->adgold_irq_status = adgold->adgold_status ^ 0xf;
@@ -167,23 +168,26 @@ void
adgold_getsamp_dma(adgold_t *adgold, int channel)
{
int temp;
dma_set_drq(adgold->dma, 1);
if ((adgold->adgold_mma_regs[channel][0xc] & 0x60) && (((adgold->adgold_mma_fifo_end[channel] - adgold->adgold_mma_fifo_start[channel]) & 255) >= 127))
return;
temp = dma_channel_read(1);
if (temp == DMA_NODATA)
temp = dma_channel_read(adgold->dma);
if (temp == DMA_NODATA) {
return;
}
adgold->adgold_mma_fifo[channel][adgold->adgold_mma_fifo_end[channel]] = temp;
adgold->adgold_mma_fifo_end[channel] = (adgold->adgold_mma_fifo_end[channel] + 1) & 255;
adgold->adgold_mma_fifo_end[channel] = (adgold->adgold_mma_fifo_end[channel] + 1) & 255;
if (adgold->adgold_mma_regs[channel][0xc] & 0x60) {
temp = dma_channel_read(1);
temp = dma_channel_read(adgold->dma);
adgold->adgold_mma_fifo[channel][adgold->adgold_mma_fifo_end[channel]] = temp;
adgold->adgold_mma_fifo_end[channel] = (adgold->adgold_mma_fifo_end[channel] + 1) & 255;
adgold->adgold_mma_fifo_end[channel] = (adgold->adgold_mma_fifo_end[channel] + 1) & 255;
}
if (((adgold->adgold_mma_fifo_end[channel] - adgold->adgold_mma_fifo_start[channel]) & 255) >= adgold->adgold_mma_intpos[channel]) {
adgold->adgold_mma_status &= ~(0x01 << channel);
adgold_update_irq_status(adgold);
dma_set_drq(adgold->dma, 0);
}
}
@@ -335,10 +339,11 @@ adgold_write(uint16_t addr, uint8_t val, void *p)
break; /* 7350 Hz*/
}
if (val & 0x80) {
adgold->adgold_mma_enable[0] = 0;
adgold->adgold_mma_enable[0] = 0;
adgold->adgold_mma_fifo_end[0] = adgold->adgold_mma_fifo_start[0] = 0;
adgold->adgold_mma_status &= ~0x01;
adgold_update_irq_status(adgold);
dma_set_drq(adgold->dma, 0);
}
if ((val & 0x01)) /*Start playback*/
{
@@ -347,7 +352,7 @@ adgold_write(uint16_t addr, uint8_t val, void *p)
if (adgold->adgold_mma_regs[0][0xc] & 1) {
if (adgold->adgold_mma_regs[0][0xc] & 0x80) {
adgold->adgold_mma_enable[1] = 1;
adgold->adgold_mma_enable[1] = 1;
adgold->adgold_mma.voice_count[1] = adgold->adgold_mma.voice_latch[1];
while (((adgold->adgold_mma_fifo_end[0] - adgold->adgold_mma_fifo_start[0]) & 255) < 128) {
@@ -357,10 +362,12 @@ adgold_write(uint16_t addr, uint8_t val, void *p)
if (((adgold->adgold_mma_fifo_end[0] - adgold->adgold_mma_fifo_start[0]) & 255) >= adgold->adgold_mma_intpos[0]) {
adgold->adgold_mma_status &= ~0x01;
adgold_update_irq_status(adgold);
dma_set_drq(adgold->dma, 0);
}
if (((adgold->adgold_mma_fifo_end[1] - adgold->adgold_mma_fifo_start[1]) & 255) >= adgold->adgold_mma_intpos[1]) {
adgold->adgold_mma_status &= ~0x02;
adgold_update_irq_status(adgold);
dma_set_drq(adgold->dma, 0);
}
} else {
while (((adgold->adgold_mma_fifo_end[0] - adgold->adgold_mma_fifo_start[0]) & 255) < 128) {
@@ -369,6 +376,7 @@ adgold_write(uint16_t addr, uint8_t val, void *p)
if (((adgold->adgold_mma_fifo_end[0] - adgold->adgold_mma_fifo_start[0]) & 255) >= adgold->adgold_mma_intpos[0]) {
adgold->adgold_mma_status &= ~0x01;
adgold_update_irq_status(adgold);
dma_set_drq(adgold->dma, 0);
}
}
}
@@ -379,10 +387,11 @@ adgold_write(uint16_t addr, uint8_t val, void *p)
case 0xb:
if (((adgold->adgold_mma_fifo_end[0] - adgold->adgold_mma_fifo_start[0]) & 255) < 128) {
adgold->adgold_mma_fifo[0][adgold->adgold_mma_fifo_end[0]] = val;
adgold->adgold_mma_fifo_end[0] = (adgold->adgold_mma_fifo_end[0] + 1) & 255;
adgold->adgold_mma_fifo_end[0] = (adgold->adgold_mma_fifo_end[0] + 1) & 255;
if (((adgold->adgold_mma_fifo_end[0] - adgold->adgold_mma_fifo_start[0]) & 255) >= adgold->adgold_mma_intpos[0]) {
adgold->adgold_mma_status &= ~0x01;
adgold_update_irq_status(adgold);
dma_set_drq(adgold->dma, 0);
}
}
break;
@@ -457,6 +466,7 @@ adgold_write(uint16_t addr, uint8_t val, void *p)
adgold->adgold_mma_fifo_end[1] = adgold->adgold_mma_fifo_start[1] = 0;
adgold->adgold_mma_status &= ~0x02;
adgold_update_irq_status(adgold);
dma_set_drq(adgold->dma, 0);
}
if ((val & 0x01)) /*Start playback*/
{
@@ -479,6 +489,7 @@ adgold_write(uint16_t addr, uint8_t val, void *p)
if (((adgold->adgold_mma_fifo_end[1] - adgold->adgold_mma_fifo_start[1]) & 255) >= adgold->adgold_mma_intpos[1]) {
adgold->adgold_mma_status &= ~0x02;
adgold_update_irq_status(adgold);
dma_set_drq(adgold->dma, 0);
}
}
break;
@@ -525,6 +536,7 @@ adgold_read(uint16_t addr, void *p)
default:
temp = adgold->adgold_38x_regs[adgold->adgold_38x_addr];
break;
}
} else
temp = opl3_read(addr, &adgold->opl);
@@ -877,8 +889,9 @@ adgold_init(const device_t *info)
adgold_t *adgold = malloc(sizeof(adgold_t));
memset(adgold, 0, sizeof(adgold_t));
adgold->dma = device_get_config_int("dma");
adgold->irq = device_get_config_int("irq");
adgold->surround_enabled = device_get_config_int("surround");
adgold->gameport_enabled = device_get_config_int("gameport");
opl3_init(&adgold->opl);
@@ -912,9 +925,9 @@ adgold_init(const device_t *info)
adgold->adgold_eeprom[0x10] = 0xff;
adgold->adgold_eeprom[0x11] = 0x20;
adgold->adgold_eeprom[0x12] = 0x00;
adgold->adgold_eeprom[0x13] = 0x0b; /* IRQ 1, DMA1 */
adgold->adgold_eeprom[0x14] = 0x00; /* DMA2 */
adgold->adgold_eeprom[0x15] = 0x71; /* Port */
adgold->adgold_eeprom[0x13] = 0xa0;
adgold->adgold_eeprom[0x14] = 0x00;
adgold->adgold_eeprom[0x15] = 0x388 / 8; /*Present at 388-38f*/
adgold->adgold_eeprom[0x16] = 0x00;
adgold->adgold_eeprom[0x17] = 0x68;
adgold->adgold_eeprom[0x18] = 0x00; /* Surround */
@@ -927,25 +940,36 @@ adgold_init(const device_t *info)
fclose(f);
}
adgold->adgold_status = 0xf;
adgold->adgold_38x_addr = 0;
adgold->adgold_eeprom[0x13] = 3 | (1 << 3); /*IRQ 7, DMA 1*/
// adgold->adgold_eeprom[0x14] = 3 << 4; /*DMA 3 - Double check this */
adgold->adgold_eeprom[0x14] = 0x00; /*DMA ?*/
adgold->adgold_eeprom[0x15] = 0x388 / 8; /*Present at 388-38f*/
adgold->adgold_status = 0xf;
adgold->adgold_38x_addr = 0;
switch (adgold->irq) {
case 3:
adgold->adgold_eeprom[0x13] |= 0x00;
break;
case 4:
adgold->adgold_eeprom[0x13] |= 0x01;
break;
case 5:
adgold->adgold_eeprom[0x13] |= 0x02;
break;
case 7:
adgold->adgold_eeprom[0x13] |= 0x03;
break;
}
adgold->adgold_eeprom[0x13] |= (adgold->dma << 3);
memcpy(adgold->adgold_38x_regs, adgold->adgold_eeprom, 0x19);
adgold->vol_l = attenuation[adgold->adgold_eeprom[0x04] & 0x3f];
adgold->vol_r = attenuation[adgold->adgold_eeprom[0x05] & 0x3f];
adgold->bass = adgold->adgold_eeprom[0x06] & 0xf;
adgold->treble = adgold->adgold_eeprom[0x07] & 0xf;
adgold->fm_vol_l = (int) (int8_t) (adgold->adgold_eeprom[0x09] - 128);
adgold->fm_vol_r = (int) (int8_t) (adgold->adgold_eeprom[0x0a] - 128);
adgold->vol_l = attenuation[adgold->adgold_eeprom[0x04] & 0x3f];
adgold->vol_r = attenuation[adgold->adgold_eeprom[0x05] & 0x3f];
adgold->bass = adgold->adgold_eeprom[0x06] & 0xf;
adgold->treble = adgold->adgold_eeprom[0x07] & 0xf;
adgold->fm_vol_l = (int) (int8_t) (adgold->adgold_eeprom[0x09] - 128);
adgold->fm_vol_r = (int) (int8_t) (adgold->adgold_eeprom[0x0a] - 128);
adgold->samp_vol_l = (int) (int8_t) (adgold->adgold_eeprom[0x0b] - 128);
adgold->samp_vol_r = (int) (int8_t) (adgold->adgold_eeprom[0x0c] - 128);
adgold->aux_vol_l = (int) (int8_t) (adgold->adgold_eeprom[0x0d] - 128);
adgold->aux_vol_r = (int) (int8_t) (adgold->adgold_eeprom[0x0e] - 128);
adgold->adgold_mma_enable[0] = 0;
adgold->adgold_mma_enable[0] = 0;
adgold->adgold_mma_fifo_start[0] = adgold->adgold_mma_fifo_end[0] = 0;
/*388/389 are handled by adlib_init*/
@@ -982,6 +1006,54 @@ adgold_close(void *p)
static const device_config_t adgold_config[] = {
// clang-format off
{
.name = "irq",
.description = "IRQ",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 7,
.file_filter = "",
.spinner = { 0 },
.selection = {
{
.description = "IRQ 3",
.value = 3
},
{
.description = "IRQ 4",
.value = 4
},
{
.description = "IRQ 5",
.value = 5
},
{
.description = "IRQ 7",
.value = 7
},
{ .description = "" }
}
},
{
.name = "dma",
.description = "Low DMA channel",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 1,
.file_filter = "",
.spinner = { 0 },
.selection = {
{
.description = "DMA 1",
.value = 1
},
{
.description = "DMA 3",
.value = 3
},
{ .description = "" }
}
},
{
.name = "gameport",
.description = "Enable Game port",