diff --git a/src/CPU/386_common.h b/src/CPU/386_common.h
index 6042cc151..562c2445d 100644
--- a/src/CPU/386_common.h
+++ b/src/CPU/386_common.h
@@ -23,39 +23,15 @@ extern uint16_t ea_rseg;
 
 
 #define readmemb(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF)?readmemb386l(s,a): *(uint8_t *)(readlookup2[(uint32_t)((s)+(a))>>12] + (uint32_t)((s) + (a))) )
-#define readmemq(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF || (((s)+(a))&0xFFF)>0xFF8)?readmemql(s,a):*(uint64_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
+#define readmemq(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF || (((s)+(a)) & 7))?readmemql(s,a):*(uint64_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
 
 #define writememb(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF) writememb386l(s,a,v); else *(uint8_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
 
-#define writememw(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF || (((s)+(a))&0xFFF)>0xFFE) writememwl(s,a,v); else *(uint16_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
-#define writememl(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF || (((s)+(a))&0xFFF)>0xFFC) writememll(s,a,v); else *(uint32_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
-#define writememq(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF || (((s)+(a))&0xFFF)>0xFF8) writememql(s,a,v); else *(uint64_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
+#define writememw(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF || (((s)+(a)) & 1)) writememwl(s,a,v); else *(uint16_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
+#define writememl(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF || (((s)+(a)) & 3)) writememll(s,a,v); else *(uint32_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
+#define writememq(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF || (((s)+(a)) & 7)) writememql(s,a,v); else *(uint64_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
 
 
-#if 0
-#define check_io_perm(port) if (!IOPLp || (eflags&VM_FLAG)) \
-                        { \
-                                int tempi = checkio(port); \
-                                if (cpu_state.abrt) return 1; \
-                                if (tempi) \
-                                { \
-                                        x86gpf("check_io_perm(): no permission",0); \
-                                        return 1; \
-                                } \
-                        }
-
-#define checkio_perm(port) if (!IOPLp || (eflags&VM_FLAG)) \
-                        { \
-                                tempi = checkio(port); \
-                                if (cpu_state.abrt) break; \
-                                if (tempi) \
-                                { \
-                                        x86gpf("checkio_perm(): no permission",0); \
-                                        break; \
-                                } \
-                        }
-#endif
-
 #define check_io_perm(port) if (msw&1 && ((CPL > IOPL) || (eflags&VM_FLAG))) \
                         { \
                                 int tempi = checkio(port); \
@@ -153,8 +129,8 @@ static __inline uint16_t fastreadw(uint32_t a)
         uint16_t val;
         if ((a&0xFFF)>0xFFE)
         {
-                val = readmemb(0, a);
-                val |= (readmemb(0, a + 1) << 8);
+                val = fastreadb(a);
+                val |= (fastreadb(a + 1) << 8);
                 return val;
         }
         if ((a>>12)==pccache) return *((uint16_t *)&pccache2[a]);
@@ -184,10 +160,8 @@ static __inline uint32_t fastreadl(uint32_t a)
                 }
                 return *((uint32_t *)&pccache2[a]);
         }
-        val  =readmemb(0,a);
-        val |=(readmemb(0,a+1)<<8);
-        val |=(readmemb(0,a+2)<<16);
-        val |=(readmemb(0,a+3)<<24);
+        val  = fastreadw(a);
+        val |= (fastreadw(a + 2) << 16);
         return val;
 }
 
diff --git a/src/CPU/codegen_ops_x86-64.h b/src/CPU/codegen_ops_x86-64.h
index f08db0b31..e85f5315f 100644
--- a/src/CPU/codegen_ops_x86-64.h
+++ b/src/CPU/codegen_ops_x86-64.h
@@ -1066,16 +1066,14 @@ static void MEM_LOAD_ADDR_EA_W(x86seg *seg)
         addbyte(0x8d);
         addbyte(0x34);
         addbyte(0x08);
-        addbyte(0x67); /*LEA EDI, 1[ESI]*/
-        addbyte(0x8d);
-        addbyte(0x7e);
-        addbyte(0x01);
+        addbyte(0x89); /*MOV EDI, ESI*/
+        addbyte(0xf7);
         addbyte(0xc1); /*SHR ESI, 12*/
         addbyte(0xe8 | REG_ESI);
         addbyte(12);
-        addbyte(0xf7); /*TEST EDI, 0xfff*/
+        addbyte(0xf7); /*TEST EDI, 1*/
         addbyte(0xc7);
-        addlong(0xfff);
+        addlong(1);
 	if (IS_32_ADDR(readlookup2))
 	{
 	        addbyte(0x67); /*MOV RSI, readlookup2[ESI*8]*/
@@ -1095,18 +1093,17 @@ static void MEM_LOAD_ADDR_EA_W(x86seg *seg)
 		addbyte(0x34);
 		addbyte(0xf2);
 	}
-        addbyte(0x74); /*JE slowpath*/
-        addbyte(3+2+5+2);
+        addbyte(0x75); /*JNE slowpath*/
+        addbyte(3+2+4+2);
         addbyte(0x83); /*CMP ESI, -1*/
         addbyte(0xf8 | REG_ESI);
         addbyte(-1);
         addbyte(0x74); /*JE slowpath*/
-        addbyte(5+2);
-        addbyte(0x66); /*MOV AX,-1[RDI+RSI]*/
+        addbyte(4+2);
+        addbyte(0x66); /*MOV AX,[RDI+RSI]*/
         addbyte(0x8b);
-        addbyte(0x44);
+        addbyte(0x04);
         addbyte(REG_EDI | (REG_ESI << 3));
-        addbyte(-1);
         addbyte(0xeb); /*JMP done*/
         addbyte(2+2+12+4+6);
         /*slowpath:*/
@@ -1155,16 +1152,14 @@ static void MEM_LOAD_ADDR_EA_L(x86seg *seg)
         addbyte(0x8d);
         addbyte(0x34);
         addbyte(0x08);
-        addbyte(0x67); /*LEA EDI, 3[ESI]*/
-        addbyte(0x8d);
-        addbyte(0x7e);
-        addbyte(0x03);
+        addbyte(0x89); /*MOV EDI, ESI*/
+        addbyte(0xf7);
         addbyte(0xc1); /*SHR ESI, 12*/
         addbyte(0xe8 | REG_ESI);
         addbyte(12);
-        addbyte(0xf7); /*TEST EDI, 0xffc*/
+        addbyte(0xf7); /*TEST EDI, 3*/
         addbyte(0xc7);
-        addlong(0xffc);
+        addlong(3);
 	if (IS_32_ADDR(readlookup2))
 	{
 	        addbyte(0x67); /*MOV RSI, readlookup2[ESI*8]*/
@@ -1184,17 +1179,16 @@ static void MEM_LOAD_ADDR_EA_L(x86seg *seg)
 		addbyte(0x34);
 		addbyte(0xf2);
 	}
-        addbyte(0x74); /*JE slowpath*/
-        addbyte(3+2+4+2);
+        addbyte(0x75); /*JNE slowpath*/
+        addbyte(3+2+3+2);
         addbyte(0x83); /*CMP ESI, -1*/
         addbyte(0xf8 | REG_ESI);
         addbyte(-1);
         addbyte(0x74); /*JE slowpath*/
-        addbyte(4+2);
-        addbyte(0x8b); /*MOV EAX,-3[RDI+RSI]*/
-        addbyte(0x44);
+        addbyte(3+2);
+        addbyte(0x8b); /*MOV EAX,[RDI+RSI]*/
+        addbyte(0x04);
         addbyte(REG_EDI | (REG_ESI << 3));
-        addbyte(-3);
         addbyte(0xeb); /*JMP done*/
         addbyte(2+2+12+4+6);
         /*slowpath:*/
@@ -1236,16 +1230,14 @@ static void MEM_LOAD_ADDR_EA_Q(x86seg *seg)
         addbyte(0x8d);
         addbyte(0x34);
         addbyte(0x08);
-        addbyte(0x67); /*LEA EDI, 7[ESI]*/
-        addbyte(0x8d);
-        addbyte(0x7e);
-        addbyte(0x07);
+        addbyte(0x89); /*MOV EDI, ESI*/
+        addbyte(0xf7);
         addbyte(0xc1); /*SHR ESI, 12*/
         addbyte(0xe8 | REG_ESI);
         addbyte(12);
-        addbyte(0xf7); /*TEST EDI, 0xff8*/
+        addbyte(0xf7); /*TEST EDI, 7*/
         addbyte(0xc7);
-        addlong(0xff8);
+        addlong(7);
 	if (IS_32_ADDR(readlookup2))
 	{
 	        addbyte(0x67); /*MOV RSI, readlookup2[ESI*8]*/
@@ -1265,18 +1257,17 @@ static void MEM_LOAD_ADDR_EA_Q(x86seg *seg)
 		addbyte(0x34);
 		addbyte(0xf2);
 	}
-        addbyte(0x74); /*JE slowpath*/
-        addbyte(3+2+5+2);
+        addbyte(0x75); /*JNE slowpath*/
+        addbyte(3+2+4+2);
         addbyte(0x83); /*CMP ESI, -1*/
         addbyte(0xf8 | REG_ESI);
         addbyte(-1);
         addbyte(0x74); /*JE slowpath*/
-        addbyte(5+2);
-        addbyte(0x48); /*MOV RAX,-7[RDI+RSI]*/
+        addbyte(4+2);
+        addbyte(0x48); /*MOV RAX,[RDI+RSI]*/
         addbyte(0x8b);
-        addbyte(0x44);
+        addbyte(0x04);
         addbyte(REG_EDI | (REG_ESI << 3));
-        addbyte(-7);
         addbyte(0xeb); /*JMP done*/
         addbyte(2+2+12+4+6);
         /*slowpath:*/
@@ -1444,16 +1435,14 @@ static void MEM_STORE_ADDR_EA_W(x86seg *seg, int host_reg)
         addbyte(0x8d);
         addbyte(0x34);
         addbyte(0x08);
-        addbyte(0x67); /*LEA EDI, 1[ESI]*/
-        addbyte(0x8d);
-        addbyte(0x7e);
-        addbyte(0x01);
+        addbyte(0x89); /*MOV EDI, ESI*/
+        addbyte(0xf7);
         addbyte(0xc1); /*SHR ESI, 12*/
         addbyte(0xe8 | REG_ESI);
         addbyte(12);
-        addbyte(0xf7); /*TEST EDI, 0xfff*/
+        addbyte(0xf7); /*TEST EDI, 1*/
         addbyte(0xc7);
-        addlong(0xfff);
+        addlong(1);
 	if (IS_32_ADDR(writelookup2))
 	{
 	        addbyte(0x67); /*MOV RSI, writelookup2[ESI*8]*/
@@ -1473,29 +1462,27 @@ static void MEM_STORE_ADDR_EA_W(x86seg *seg, int host_reg)
 		addbyte(0x34);
 		addbyte(0xf2);
 	}
-        addbyte(0x74); /*JE slowpath*/
-        addbyte(3+2+((host_reg & 8) ? 6:5)+2);
+        addbyte(0x75); /*JNE slowpath*/
+        addbyte(3+2+((host_reg & 8) ? 5:4)+2);
         addbyte(0x83); /*CMP ESI, -1*/
         addbyte(0xf8 | REG_ESI);
         addbyte(-1);
         addbyte(0x74); /*JE slowpath*/
-        addbyte(((host_reg & 8) ? 6:5)+2);
+        addbyte(((host_reg & 8) ? 5:4)+2);
         if (host_reg & 8)
         {
-                addbyte(0x66); /*MOV -1[RDI+RSI],host_reg*/
+                addbyte(0x66); /*MOV [RDI+RSI],host_reg*/
                 addbyte(0x44);
                 addbyte(0x89);
-                addbyte(0x44 | ((host_reg & 7) << 3));
+                addbyte(0x04 | ((host_reg & 7) << 3));
                 addbyte(REG_EDI | (REG_ESI << 3));
-                addbyte(-1);
         }
         else
         {
-                addbyte(0x66); /*MOV -1[RDI+RSI],host_reg*/
+                addbyte(0x66); /*MOV [RDI+RSI],host_reg*/
                 addbyte(0x89);
-                addbyte(0x44 | (host_reg << 3));
+                addbyte(0x04 | (host_reg << 3));
                 addbyte(REG_EDI | (REG_ESI << 3));
-                addbyte(-1);
         }
         addbyte(0xeb); /*JMP done*/
         addbyte(2+2+3+12+4+6);
@@ -1539,16 +1526,14 @@ static void MEM_STORE_ADDR_EA_L(x86seg *seg, int host_reg)
         addbyte(0x8d);
         addbyte(0x34);
         addbyte(0x08);
-        addbyte(0x67); /*LEA EDI, 3[ESI]*/
-        addbyte(0x8d);
-        addbyte(0x7e);
-        addbyte(0x03);
+        addbyte(0x89); /*MOV EDI, ESI*/
+        addbyte(0xf7);
         addbyte(0xc1); /*SHR ESI, 12*/
         addbyte(0xe8 | REG_ESI);
         addbyte(12);
-        addbyte(0xf7); /*TEST EDI, 0xffc*/
+        addbyte(0xf7); /*TEST EDI, 3*/
         addbyte(0xc7);
-        addlong(0xffc);
+        addlong(3);
 	if (IS_32_ADDR(writelookup2))
 	{
 	        addbyte(0x67); /*MOV RSI, writelookup2[ESI*8]*/
@@ -1568,27 +1553,25 @@ static void MEM_STORE_ADDR_EA_L(x86seg *seg, int host_reg)
 		addbyte(0x34);
 		addbyte(0xf2);
 	}
-        addbyte(0x74); /*JE slowpath*/
-        addbyte(3+2+((host_reg & 8) ? 5:4)+2);
+        addbyte(0x75); /*JNE slowpath*/
+        addbyte(3+2+((host_reg & 8) ? 4:3)+2);
         addbyte(0x83); /*CMP ESI, -1*/
         addbyte(0xf8 | REG_ESI);
         addbyte(-1);
         addbyte(0x74); /*JE slowpath*/
-        addbyte(((host_reg & 8) ? 5:4)+2);
+        addbyte(((host_reg & 8) ? 4:3)+2);
         if (host_reg & 8)
         {
                 addbyte(0x44); /*MOV -3[RDI+RSI],host_reg*/
                 addbyte(0x89);
-                addbyte(0x44 | ((host_reg & 7) << 3));
+                addbyte(0x04 | ((host_reg & 7) << 3));
                 addbyte(REG_EDI | (REG_ESI << 3));
-                addbyte(-3);
         }
         else
         {
                 addbyte(0x89); /*MOV -3[RDI+RSI],host_reg*/
-                addbyte(0x44 | (host_reg << 3));
+                addbyte(0x04 | (host_reg << 3));
                 addbyte(REG_EDI | (REG_ESI << 3));
-                addbyte(-3);
         }
         addbyte(0xeb); /*JMP done*/
         addbyte(2+2+3+12+4+6);
@@ -1632,16 +1615,14 @@ static void MEM_STORE_ADDR_EA_Q(x86seg *seg, int host_reg, int host_reg2)
         addbyte(0x8d);
         addbyte(0x34);
         addbyte(0x08);
-        addbyte(0x67); /*LEA EDI, 7[ESI]*/
-        addbyte(0x8d);
-        addbyte(0x7e);
-        addbyte(0x07);
+        addbyte(0x89); /*MOV EDI, ESI*/
+        addbyte(0xf7);
         addbyte(0xc1); /*SHR ESI, 12*/
         addbyte(0xe8 | REG_ESI);
         addbyte(12);
-        addbyte(0xf7); /*TEST EDI, 0xff8*/
+        addbyte(0xf7); /*TEST EDI, 7*/
         addbyte(0xc7);
-        addlong(0xff8);
+        addlong(7);
 	if (IS_32_ADDR(writelookup2))
 	{
 	        addbyte(0x67); /*MOV RSI, writelookup2[ESI*8]*/
@@ -1661,28 +1642,26 @@ static void MEM_STORE_ADDR_EA_Q(x86seg *seg, int host_reg, int host_reg2)
 		addbyte(0x34);
 		addbyte(0xf2);
 	}
-        addbyte(0x74); /*JE slowpath*/
-        addbyte(3+2+5+2);
+        addbyte(0x75); /*JNE slowpath*/
+        addbyte(3+2+4+2);
         addbyte(0x83); /*CMP ESI, -1*/
         addbyte(0xf8 | REG_ESI);
         addbyte(-1);
         addbyte(0x74); /*JE slowpath*/
-        addbyte(5+2);
+        addbyte(4+2);
         if (host_reg & 8)
         {
-                addbyte(0x4c); /*MOV -7[RDI+RSI],host_reg*/
+                addbyte(0x4c); /*MOV [RDI+RSI],host_reg*/
                 addbyte(0x89);
-                addbyte(0x44 | ((host_reg & 7) << 3));
+                addbyte(0x04 | ((host_reg & 7) << 3));
                 addbyte(REG_EDI | (REG_ESI << 3));
-                addbyte(-7);
         }
         else
         {
-                addbyte(0x48); /*MOV -3[RDI+RSI],host_reg*/
+                addbyte(0x48); /*MOV [RDI+RSI],host_reg*/
                 addbyte(0x89);
-                addbyte(0x44 | (host_reg << 3));
+                addbyte(0x04 | (host_reg << 3));
                 addbyte(REG_EDI | (REG_ESI << 3));
-                addbyte(-7);
         }
         addbyte(0xeb); /*JMP done*/
         addbyte(2+2+3+12+4+6);
@@ -5818,16 +5797,14 @@ static int MEM_LOAD_ADDR_EA_W_NO_ABRT(x86seg *seg)
         addbyte(0x8d);
         addbyte(0x34);
         addbyte(0x08);
-        addbyte(0x67); /*LEA EDI, 1[ESI]*/
-        addbyte(0x8d);
-        addbyte(0x7e);
-        addbyte(0x01);
+        addbyte(0x89); /*MOV EDI, ESI*/
+        addbyte(0xf7);
         addbyte(0xc1); /*SHR ESI, 12*/
         addbyte(0xe8 | REG_ESI);
         addbyte(12);
-        addbyte(0xf7); /*TEST EDI, 0xfff*/
+        addbyte(0xf7); /*TEST EDI, 1*/
         addbyte(0xc7);
-        addlong(0xfff);
+        addlong(1);
 	if (IS_32_ADDR(readlookup2))
 	{
 	        addbyte(0x67); /*MOV RSI, readlookup2[ESI*8]*/
@@ -5847,18 +5824,17 @@ static int MEM_LOAD_ADDR_EA_W_NO_ABRT(x86seg *seg)
 		addbyte(0x34);
 		addbyte(0xf2);
 	}
-        addbyte(0x74); /*JE slowpath*/
-        addbyte(3+2+5+2);
+        addbyte(0x75); /*JE slowpath*/
+        addbyte(3+2+4+2);
         addbyte(0x83); /*CMP ESI, -1*/
         addbyte(0xf8 | REG_ESI);
         addbyte(-1);
         addbyte(0x74); /*JE slowpath*/
-        addbyte(5+2);
-        addbyte(0x66); /*MOV AX,-1[RDI+RSI]*/
+        addbyte(4+2);
+        addbyte(0x66); /*MOV AX,[RDI+RSI]*/
         addbyte(0x8b);
-        addbyte(0x44);
+        addbyte(0x04);
         addbyte(REG_EDI | (REG_ESI << 3));
-        addbyte(-1);
         addbyte(0xeb); /*JMP done*/
         addbyte(2+2+12);
         /*slowpath:*/
@@ -5899,16 +5875,14 @@ static int MEM_LOAD_ADDR_EA_L_NO_ABRT(x86seg *seg)
         addbyte(0x8d);
         addbyte(0x34);
         addbyte(0x08);
-        addbyte(0x67); /*LEA EDI, 3[ESI]*/
-        addbyte(0x8d);
-        addbyte(0x7e);
-        addbyte(0x03);
+        addbyte(0x89); /*MOV EDI, ESI*/
+        addbyte(0xf7);
         addbyte(0xc1); /*SHR ESI, 12*/
         addbyte(0xe8 | REG_ESI);
         addbyte(12);
-        addbyte(0xf7); /*TEST EDI, 0xffc*/
+        addbyte(0xf7); /*TEST EDI, 3*/
         addbyte(0xc7);
-        addlong(0xffc);
+        addlong(3);
 	if (IS_32_ADDR(readlookup2))
 	{
 	        addbyte(0x67); /*MOV RSI, readlookup2[ESI*8]*/
@@ -5928,17 +5902,16 @@ static int MEM_LOAD_ADDR_EA_L_NO_ABRT(x86seg *seg)
 		addbyte(0x34);
 		addbyte(0xf2);
 	}
-        addbyte(0x74); /*JE slowpath*/
-        addbyte(3+2+4+2);
+        addbyte(0x54); /*JNE slowpath*/
+        addbyte(3+2+3+2);
         addbyte(0x83); /*CMP ESI, -1*/
         addbyte(0xf8 | REG_ESI);
         addbyte(-1);
         addbyte(0x74); /*JE slowpath*/
-        addbyte(4+2);
+        addbyte(3+2);
         addbyte(0x8b); /*MOV EAX,-3[RDI+RSI]*/
-        addbyte(0x44);
+        addbyte(0x04);
         addbyte(REG_EDI | (REG_ESI << 3));
-        addbyte(-3);
         addbyte(0xeb); /*JMP done*/
         addbyte(2+2+12);
         /*slowpath:*/
@@ -6081,16 +6054,14 @@ static void MEM_STORE_ADDR_EA_W_NO_ABRT(x86seg *seg, int host_reg)
         addbyte(0x8d);
         addbyte(0x34);
         addbyte(0x18);
-        addbyte(0x67); /*LEA EDI, 1[ESI]*/
-        addbyte(0x8d);
-        addbyte(0x7e);
-        addbyte(0x01);
+        addbyte(0x89); /*MOV EDI, ESI*/
+        addbyte(0xf7);
         addbyte(0xc1); /*SHR ESI, 12*/
         addbyte(0xe8 | REG_ESI);
         addbyte(12);
-        addbyte(0xf7); /*TEST EDI, 0xfff*/
+        addbyte(0xf7); /*TEST EDI, 1*/
         addbyte(0xc7);
-        addlong(0xfff);
+        addlong(1);
 	if (IS_32_ADDR(writelookup2))
 	{
 	        addbyte(0x67); /*MOV RSI, writelookup2[ESI*8]*/
@@ -6110,29 +6081,27 @@ static void MEM_STORE_ADDR_EA_W_NO_ABRT(x86seg *seg, int host_reg)
 		addbyte(0x34);
 		addbyte(0xf2);
 	}
-        addbyte(0x74); /*JE slowpath*/
-        addbyte(3+2+((host_reg & 8) ? 6:5)+2);
+        addbyte(0x75); /*JNE slowpath*/
+        addbyte(3+2+((host_reg & 8) ? 5:4)+2);
         addbyte(0x83); /*CMP ESI, -1*/
         addbyte(0xf8 | REG_ESI);
         addbyte(-1);
         addbyte(0x74); /*JE slowpath*/
-        addbyte(((host_reg & 8) ? 6:5)+2);
+        addbyte(((host_reg & 8) ? 5:4)+2);
         if (host_reg & 8)
         {
-                addbyte(0x66); /*MOV -1[RDI+RSI],host_reg*/
+                addbyte(0x66); /*MOV [RDI+RSI],host_reg*/
                 addbyte(0x44);
                 addbyte(0x89);
-                addbyte(0x44 | ((host_reg & 7) << 3));
+                addbyte(0x04 | ((host_reg & 7) << 3));
                 addbyte(REG_EDI | (REG_ESI << 3));
-                addbyte(-1);
         }
         else
         {
-                addbyte(0x66); /*MOV -1[RDI+RSI],host_reg*/
+                addbyte(0x66); /*MOV [RDI+RSI],host_reg*/
                 addbyte(0x89);
-                addbyte(0x44 | (host_reg << 3));
+                addbyte(0x04 | (host_reg << 3));
                 addbyte(REG_EDI | (REG_ESI << 3));
-                addbyte(-1);
         }
         addbyte(0xeb); /*JMP done*/
         addbyte(2+2+3+12);
@@ -6170,16 +6139,14 @@ static void MEM_STORE_ADDR_EA_L_NO_ABRT(x86seg *seg, int host_reg)
         addbyte(0x8d);
         addbyte(0x34);
         addbyte(0x18);
-        addbyte(0x67); /*LEA EDI, 3[ESI]*/
-        addbyte(0x8d);
-        addbyte(0x7e);
-        addbyte(0x03);
+        addbyte(0x89); /*MOV EDI, ESI*/
+        addbyte(0xf7);
         addbyte(0xc1); /*SHR ESI, 12*/
         addbyte(0xe8 | REG_ESI);
         addbyte(12);
-        addbyte(0xf7); /*TEST EDI, 0xffc*/
+        addbyte(0xf7); /*TEST EDI, 3*/
         addbyte(0xc7);
-        addlong(0xffc);
+        addlong(3);
 	if (IS_32_ADDR(writelookup2))
 	{
 	        addbyte(0x67); /*MOV RSI, writelookup2[ESI*8]*/
@@ -6199,27 +6166,25 @@ static void MEM_STORE_ADDR_EA_L_NO_ABRT(x86seg *seg, int host_reg)
 		addbyte(0x34);
 		addbyte(0xf2);
 	}
-        addbyte(0x74); /*JE slowpath*/
-        addbyte(3+2+((host_reg & 8) ? 5:4)+2);
+        addbyte(0x75); /*JNE slowpath*/
+        addbyte(3+2+((host_reg & 8) ? 4:3)+2);
         addbyte(0x83); /*CMP ESI, -1*/
         addbyte(0xf8 | REG_ESI);
         addbyte(-1);
         addbyte(0x74); /*JE slowpath*/
-        addbyte(((host_reg & 8) ? 5:4)+2);
+        addbyte(((host_reg & 8) ? 4:3)+2);
         if (host_reg & 8)
         {
-                addbyte(0x44); /*MOV -3[RDI+RSI],host_reg*/
+                addbyte(0x44); /*MOV [RDI+RSI],host_reg*/
                 addbyte(0x89);
-                addbyte(0x44 | ((host_reg & 7) << 3));
+                addbyte(0x04 | ((host_reg & 7) << 3));
                 addbyte(REG_EDI | (REG_ESI << 3));
-                addbyte(-3);
         }
         else
         {
-                addbyte(0x89); /*MOV -3[RDI+RSI],host_reg*/
-                addbyte(0x44 | (host_reg << 3));
+                addbyte(0x89); /*MOV [RDI+RSI],host_reg*/
+                addbyte(0x04 | (host_reg << 3));
                 addbyte(REG_EDI | (REG_ESI << 3));
-                addbyte(-3);
         }
         addbyte(0xeb); /*JMP done*/
         addbyte(2+2+3+12);
diff --git a/src/CPU/codegen_x86.c b/src/CPU/codegen_x86.c
index 82b8e5575..a4f0ffe59 100644
--- a/src/CPU/codegen_x86.c
+++ b/src/CPU/codegen_x86.c
@@ -136,31 +136,29 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_W()
         addbyte(0xd6);
         addbyte(0x01); /*ADDL EDX, EAX*/
         addbyte(0xc2);
-        addbyte(0x8d); /*LEA EDI, 1[EDX]*/
-        addbyte(0x7a);
-        addbyte(0x01);
+        addbyte(0x89); /*MOV EDI, EDX*/
+        addbyte(0xd7);
         addbyte(0xc1); /*SHR EDX, 12*/
         addbyte(0xea);
         addbyte(12);
-        addbyte(0xf7); /*TEST EDI, 0xfff*/
+        addbyte(0xf7); /*TEST EDI, 1*/
         addbyte(0xc7);
-        addlong(0xfff);
+        addlong(1);
         addbyte(0x8b); /*MOV EDX, readlookup2[EDX*4]*/
         addbyte(0x14);
         addbyte(0x95);
         addlong((uint32_t)readlookup2);
-        addbyte(0x74); /*JE slowpath*/
-        addbyte(3+2+5+1);
+        addbyte(0x75); /*JNE slowpath*/
+        addbyte(3+2+4+1);
         addbyte(0x83); /*CMP EDX, -1*/
         addbyte(0xfa);
         addbyte(-1);
         addbyte(0x74); /*JE slowpath*/
-        addbyte(5+1);
-        addbyte(0x0f); /*MOVZX EAX, -1[EDX+EDI]W*/
+        addbyte(4+1);
+        addbyte(0x0f); /*MOVZX EAX, [EDX+EDI]W*/
         addbyte(0xb7);
-        addbyte(0x44);
+        addbyte(0x04);
         addbyte(0x3a);
-        addbyte(-1);
         addbyte(0xc3); /*RET*/
 
         addbyte(0x50); /*slowpath: PUSH EAX*/
@@ -193,30 +191,28 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_L()
         addbyte(0xd6);
         addbyte(0x01); /*ADDL EDX, EAX*/
         addbyte(0xc2);
-        addbyte(0x8d); /*LEA EDI, 3[EDX]*/
-        addbyte(0x7a);
-        addbyte(0x03);
+        addbyte(0x89); /*MOV EDI, EDX*/
+        addbyte(0xd7);
         addbyte(0xc1); /*SHR EDX, 12*/
         addbyte(0xea);
         addbyte(12);
-        addbyte(0xf7); /*TEST EDI, 0xffc*/
+        addbyte(0xf7); /*TEST EDI, 3*/
         addbyte(0xc7);
-        addlong(0xffc);
+        addlong(3);
         addbyte(0x8b); /*MOV EDX, readlookup2[EDX*4]*/
         addbyte(0x14);
         addbyte(0x95);
         addlong((uint32_t)readlookup2);
-        addbyte(0x74); /*JE slowpath*/
-        addbyte(3+2+4+1);
+        addbyte(0x75); /*JNE slowpath*/
+        addbyte(3+2+3+1);
         addbyte(0x83); /*CMP EDX, -1*/
         addbyte(0xfa);
         addbyte(-1);
         addbyte(0x74); /*JE slowpath*/
-        addbyte(4+1);
-        addbyte(0x8b); /*MOV EAX, -3[EDX+EDI]*/
-        addbyte(0x44);
+        addbyte(3+1);
+        addbyte(0x8b); /*MOV EAX, [EDX+EDI]*/
+        addbyte(0x04);
         addbyte(0x3a);
-        addbyte(-3);
         addbyte(0xc3); /*RET*/
 
         addbyte(0x50); /*slowpath: PUSH EAX*/
@@ -246,34 +242,32 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_Q()
         addbyte(0xd6);
         addbyte(0x01); /*ADDL EDX, EAX*/
         addbyte(0xc2);
-        addbyte(0x8d); /*LEA EDI, 7[EDX]*/
-        addbyte(0x7a);
-        addbyte(0x07);
+        addbyte(0x89); /*MOV EDI, EDX*/
+        addbyte(0xd7);
         addbyte(0xc1); /*SHR EDX, 12*/
         addbyte(0xea);
         addbyte(12);
-        addbyte(0xf7); /*TEST EDI, 0xff8*/
+        addbyte(0xf7); /*TEST EDI, 7*/
         addbyte(0xc7);
-        addlong(0xff8);
+        addlong(7);
         addbyte(0x8b); /*MOV EDX, readlookup2[EDX*4]*/
         addbyte(0x14);
         addbyte(0x95);
         addlong((uint32_t)readlookup2);
-        addbyte(0x74); /*JE slowpath*/
-        addbyte(3+2+4+4+1);
+        addbyte(0x75); /*JNE slowpath*/
+        addbyte(3+2+3+4+1);
         addbyte(0x83); /*CMP EDX, -1*/
         addbyte(0xfa);
         addbyte(-1);
         addbyte(0x74); /*JE slowpath*/
-        addbyte(4+4+1);
+        addbyte(3+4+1);
         addbyte(0x8b); /*MOV EAX, [EDX+EDI]*/
-        addbyte(0x44);
+        addbyte(0x04);
         addbyte(0x3a);
-        addbyte(-7);
         addbyte(0x8b); /*MOV EDX, [EDX+EDI+4]*/
         addbyte(0x54);
         addbyte(0x3a);
-        addbyte(-7+4);
+        addbyte(4);
         addbyte(0xc3); /*RET*/
 
         addbyte(0x50); /*slowpath: PUSH EAX*/
@@ -352,31 +346,29 @@ static uint32_t gen_MEM_STORE_ADDR_EA_W()
         addbyte(0xf3);
         addbyte(0x01); /*ADDL ESI, EAX*/
         addbyte(0xc0 | (REG_EAX << 3) | REG_ESI);
-        addbyte(0x8d); /*LEA EDI, 1[ESI]*/
-        addbyte(0x7e);
-        addbyte(0x01);
+        addbyte(0x89); /*MOV EDI, ESI*/
+        addbyte(0xf7);
         addbyte(0xc1); /*SHR ESI, 12*/
         addbyte(0xe8 | REG_ESI);
         addbyte(12);
-        addbyte(0xf7); /*TEST EDI, 0xfff*/
+        addbyte(0xf7); /*TEST EDI, 1*/
         addbyte(0xc7);
-        addlong(0xfff);
+        addlong(1);
         addbyte(0x8b); /*MOV ESI, readlookup2[ESI*4]*/
         addbyte(0x04 | (REG_ESI << 3));
         addbyte(0x85 | (REG_ESI << 3));
         addlong((uint32_t)writelookup2);
-        addbyte(0x74); /*JE slowpath*/
-        addbyte(3+2+5+1);
+        addbyte(0x75); /*JNE slowpath*/
+        addbyte(3+2+4+1);
         addbyte(0x83); /*CMP ESI, -1*/
         addbyte(0xf8 | REG_ESI);
         addbyte(-1);
         addbyte(0x74); /*JE slowpath*/
-        addbyte(5+1);
-        addbyte(0x66); /*MOV -1[EDI+ESI],CX*/
+        addbyte(4+1);
+        addbyte(0x66); /*MOV [EDI+ESI],CX*/
         addbyte(0x89);
-        addbyte(0x44 | (REG_CX << 3));
+        addbyte(0x04 | (REG_CX << 3));
         addbyte(REG_EDI | (REG_ESI << 3));
-        addbyte(-1);
         addbyte(0xc3); /*RET*/
 
         addbyte(0x51); /*slowpath: PUSH ECX*/
@@ -408,30 +400,28 @@ static uint32_t gen_MEM_STORE_ADDR_EA_L()
         addbyte(0xf3);
         addbyte(0x01); /*ADDL ESI, EAX*/
         addbyte(0xc0 | (REG_EAX << 3) | REG_ESI);
-        addbyte(0x8d); /*LEA EDI, 3[ESI]*/
-        addbyte(0x7e);
-        addbyte(0x03);
+        addbyte(0x89); /*MOV EDI, ESI*/
+        addbyte(0xf7);
         addbyte(0xc1); /*SHR ESI, 12*/
         addbyte(0xe8 | REG_ESI);
         addbyte(12);
-        addbyte(0xf7); /*TEST EDI, 0xffc*/
+        addbyte(0xf7); /*TEST EDI, 3*/
         addbyte(0xc7);
-        addlong(0xffc);
+        addlong(3);
         addbyte(0x8b); /*MOV ESI, readlookup2[ESI*4]*/
         addbyte(0x04 | (REG_ESI << 3));
         addbyte(0x85 | (REG_ESI << 3));
         addlong((uint32_t)writelookup2);
-        addbyte(0x74); /*JE slowpath*/
-        addbyte(3+2+4+1);
+        addbyte(0x75); /*JNE slowpath*/
+        addbyte(3+2+3+1);
         addbyte(0x83); /*CMP ESI, -1*/
         addbyte(0xf8 | REG_ESI);
         addbyte(-1);
         addbyte(0x74); /*JE slowpath*/
-        addbyte(4+1);
-        addbyte(0x89); /*MOV -3[EDI+ESI],ECX*/
-        addbyte(0x44 | (REG_ECX << 3));
+        addbyte(3+1);
+        addbyte(0x89); /*MOV [EDI+ESI],ECX*/
+        addbyte(0x04 | (REG_ECX << 3));
         addbyte(REG_EDI | (REG_ESI << 3));
-        addbyte(-3);
         addbyte(0xc3); /*RET*/
 
         addbyte(0x51); /*slowpath: PUSH ECX*/
@@ -463,34 +453,32 @@ static uint32_t gen_MEM_STORE_ADDR_EA_Q()
         addbyte(0xf2);
         addbyte(0x01); /*ADDL ESI, EAX*/
         addbyte(0xc0 | (REG_EAX << 3) | REG_ESI);
-        addbyte(0x8d); /*LEA EDI, 7[ESI]*/
-        addbyte(0x7e);
-        addbyte(0x07);
+        addbyte(0x89); /*MOV EDI, ESI*/
+        addbyte(0xf7);
         addbyte(0xc1); /*SHR ESI, 12*/
         addbyte(0xe8 | REG_ESI);
         addbyte(12);
-        addbyte(0xf7); /*TEST EDI, 0xff8*/
+        addbyte(0xf7); /*TEST EDI, 7*/
         addbyte(0xc7);
-        addlong(0xff8);
+        addlong(7);
         addbyte(0x8b); /*MOV ESI, readlookup2[ESI*4]*/
         addbyte(0x04 | (REG_ESI << 3));
         addbyte(0x85 | (REG_ESI << 3));
         addlong((uint32_t)writelookup2);
-        addbyte(0x74); /*JE slowpath*/
-        addbyte(3+2+4+4+1);
+        addbyte(0x75); /*JNE slowpath*/
+        addbyte(3+2+3+4+1);
         addbyte(0x83); /*CMP ESI, -1*/
         addbyte(0xf8 | REG_ESI);
         addbyte(-1);
         addbyte(0x74); /*JE slowpath*/
-        addbyte(4+4+1);
-        addbyte(0x89); /*MOV -7[EDI+ESI],EBX*/
-        addbyte(0x44 | (REG_EBX << 3));
+        addbyte(3+4+1);
+        addbyte(0x89); /*MOV [EDI+ESI],EBX*/
+        addbyte(0x04 | (REG_EBX << 3));
         addbyte(REG_EDI | (REG_ESI << 3));
-        addbyte(-7);
-        addbyte(0x89); /*MOV -7[EDI+ESI],EBX*/
+        addbyte(0x89); /*MOV 4[EDI+ESI],EBX*/
         addbyte(0x44 | (REG_ECX << 3));
         addbyte(REG_EDI | (REG_ESI << 3));
-        addbyte(-7+4);
+        addbyte(4);
         addbyte(0xc3); /*RET*/
 
         addbyte(0x51); /*slowpath: PUSH ECX*/
@@ -514,7 +502,9 @@ static uint32_t gen_MEM_STORE_ADDR_EA_Q()
         return addr;
 }
 
+#ifndef RELEASE_BUILD
 static char gen_MEM_LOAD_ADDR_EA_B_NO_ABRT_err[] = "gen_MEM_LOAD_ADDR_EA_B_NO_ABRT aborted\n";
+#endif
 static uint32_t gen_MEM_LOAD_ADDR_EA_B_NO_ABRT()
 {
         uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
@@ -576,7 +566,9 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_B_NO_ABRT()
         return addr;
 }
 
+#ifndef RELEASE_BUILD
 static char gen_MEM_LOAD_ADDR_EA_W_NO_ABRT_err[] = "gen_MEM_LOAD_ADDR_EA_W_NO_ABRT aborted\n";
+#endif
 static uint32_t gen_MEM_LOAD_ADDR_EA_W_NO_ABRT()
 {
         uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
@@ -585,31 +577,29 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_W_NO_ABRT()
         addbyte(0xd6);
         addbyte(0x01); /*ADDL EDX, EAX*/
         addbyte(0xc2);
-        addbyte(0x8d); /*LEA EDI, 1[EDX]*/
-        addbyte(0x7a);
-        addbyte(0x01);
+        addbyte(0x89); /*MOV EDI, EDX*/
+        addbyte(0xd7);
         addbyte(0xc1); /*SHR EDX, 12*/
         addbyte(0xea);
         addbyte(12);
-        addbyte(0xf7); /*TEST EDI, 0xfff*/
+        addbyte(0xf7); /*TEST EDI, 1*/
         addbyte(0xc7);
-        addlong(0xfff);
+        addlong(1);
         addbyte(0x8b); /*MOV EDX, readlookup2[EDX*4]*/
         addbyte(0x14);
         addbyte(0x95);
         addlong((uint32_t)readlookup2);
-        addbyte(0x74); /*JE slowpath*/
-        addbyte(3+2+5+1);
+        addbyte(0x75); /*JNE slowpath*/
+        addbyte(3+2+4+1);
         addbyte(0x83); /*CMP EDX, -1*/
         addbyte(0xfa);
         addbyte(-1);
         addbyte(0x74); /*JE slowpath*/
-        addbyte(5+1);
-        addbyte(0x0f); /*MOVZX EEX, -1[EDX+EDI]W*/
+        addbyte(4+1);
+        addbyte(0x0f); /*MOVZX ECX, [EDX+EDI]W*/
         addbyte(0xb7);
-        addbyte(0x4c);
+        addbyte(0x0c);
         addbyte(0x3a);
-        addbyte(-1);
         addbyte(0xc3); /*RET*/
 
         addbyte(0x50); /*slowpath: PUSH EAX*/
@@ -645,7 +635,9 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_W_NO_ABRT()
         return addr;
 }
 
+#ifndef RELEASE_BUILD
 static char gen_MEM_LOAD_ADDR_EA_L_NO_ABRT_err[] = "gen_MEM_LOAD_ADDR_EA_L_NO_ABRT aborted\n";
+#endif
 static uint32_t gen_MEM_LOAD_ADDR_EA_L_NO_ABRT()
 {
         uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
@@ -654,30 +646,28 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_L_NO_ABRT()
         addbyte(0xd6);
         addbyte(0x01); /*ADDL EDX, EAX*/
         addbyte(0xc2);
-        addbyte(0x8d); /*LEA EDI, 3[EDX]*/
-        addbyte(0x7a);
-        addbyte(0x03);
+        addbyte(0x89); /*MOV EDI, EDX*/
+        addbyte(0xd7);
         addbyte(0xc1); /*SHR EDX, 12*/
         addbyte(0xea);
         addbyte(12);
-        addbyte(0xf7); /*TEST EDI, 0xffc*/
+        addbyte(0xf7); /*TEST EDI, 3*/
         addbyte(0xc7);
-        addlong(0xffc);
+        addlong(3);
         addbyte(0x8b); /*MOV EDX, readlookup2[EDX*4]*/
         addbyte(0x14);
         addbyte(0x95);
         addlong((uint32_t)readlookup2);
-        addbyte(0x74); /*JE slowpath*/
-        addbyte(3+2+4+1);
+        addbyte(0x75); /*JNE slowpath*/
+        addbyte(3+2+3+1);
         addbyte(0x83); /*CMP EDX, -1*/
         addbyte(0xfa);
         addbyte(-1);
         addbyte(0x74); /*JE slowpath*/
-        addbyte(4+1);
-        addbyte(0x8b); /*MOV ECX, -3[EDX+EDI]*/
-        addbyte(0x4c);
+        addbyte(3+1);
+        addbyte(0x8b); /*MOV ECX, [EDX+EDI]*/
+        addbyte(0x0c);
         addbyte(0x3a);
-        addbyte(-3);
         addbyte(0xc3); /*RET*/
 
         addbyte(0x50); /*slowpath: PUSH EAX*/
@@ -713,7 +703,9 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_L_NO_ABRT()
         return addr;
 }
 
+#ifndef RELEASE_BUILD
 static char gen_MEM_STORE_ADDR_EA_B_NO_ABRT_err[] = "gen_MEM_STORE_ADDR_EA_B_NO_ABRT aborted\n";
+#endif
 static uint32_t gen_MEM_STORE_ADDR_EA_B_NO_ABRT()
 {
         uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
@@ -771,7 +763,9 @@ static uint32_t gen_MEM_STORE_ADDR_EA_B_NO_ABRT()
         return addr;
 }
 
+#ifndef RELEASE_BUILD
 static char gen_MEM_STORE_ADDR_EA_W_NO_ABRT_err[] = "gen_MEM_STORE_ADDR_EA_W_NO_ABRT aborted\n";
+#endif
 static uint32_t gen_MEM_STORE_ADDR_EA_W_NO_ABRT()
 {
         uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
@@ -781,31 +775,29 @@ static uint32_t gen_MEM_STORE_ADDR_EA_W_NO_ABRT()
         addbyte(0xf3);
         addbyte(0x01); /*ADDL ESI, EAX*/
         addbyte(0xc0 | (REG_EAX << 3) | REG_ESI);
-        addbyte(0x8d); /*LEA EDI, 1[ESI]*/
-        addbyte(0x7e);
-        addbyte(0x01);
+        addbyte(0x89); /*MOV EDI, ESI*/
+        addbyte(0xf7);
         addbyte(0xc1); /*SHR ESI, 12*/
         addbyte(0xe8 | REG_ESI);
         addbyte(12);
-        addbyte(0xf7); /*TEST EDI, 0xfff*/
+        addbyte(0xf7); /*TEST EDI, 1*/
         addbyte(0xc7);
-        addlong(0xfff);
+        addlong(1);
         addbyte(0x8b); /*MOV ESI, readlookup2[ESI*4]*/
         addbyte(0x04 | (REG_ESI << 3));
         addbyte(0x85 | (REG_ESI << 3));
         addlong((uint32_t)writelookup2);
-        addbyte(0x74); /*JE slowpath*/
-        addbyte(3+2+5+1);
+        addbyte(0x75); /*JNE slowpath*/
+        addbyte(3+2+4+1);
         addbyte(0x83); /*CMP ESI, -1*/
         addbyte(0xf8 | REG_ESI);
         addbyte(-1);
         addbyte(0x74); /*JE slowpath*/
-        addbyte(5+1);
-        addbyte(0x66); /*MOV -1[EDI+ESI],CX*/
+        addbyte(4+1);
+        addbyte(0x66); /*MOV [EDI+ESI],CX*/
         addbyte(0x89);
-        addbyte(0x44 | (REG_CX << 3));
+        addbyte(0x04 | (REG_CX << 3));
         addbyte(REG_EDI | (REG_ESI << 3));
-        addbyte(-1);
         addbyte(0xc3); /*RET*/
 
         addbyte(0x51); /*slowpath: PUSH ECX*/
@@ -837,7 +829,9 @@ static uint32_t gen_MEM_STORE_ADDR_EA_W_NO_ABRT()
         return addr;
 }
 
+#ifndef RELEASE_BUILD
 static char gen_MEM_STORE_ADDR_EA_L_NO_ABRT_err[] = "gen_MEM_STORE_ADDR_EA_L_NO_ABRT aborted\n";
+#endif
 static uint32_t gen_MEM_STORE_ADDR_EA_L_NO_ABRT()
 {
         uint32_t addr = (uint32_t)&codeblock[block_current].data[block_pos];
@@ -847,30 +841,28 @@ static uint32_t gen_MEM_STORE_ADDR_EA_L_NO_ABRT()
         addbyte(0xf3);
         addbyte(0x01); /*ADDL ESI, EAX*/
         addbyte(0xc0 | (REG_EAX << 3) | REG_ESI);
-        addbyte(0x8d); /*LEA EDI, 3[ESI]*/
-        addbyte(0x7e);
-        addbyte(0x03);
+        addbyte(0x89); /*MOV EDI, ESI*/
+        addbyte(0xf7);
         addbyte(0xc1); /*SHR ESI, 12*/
         addbyte(0xe8 | REG_ESI);
         addbyte(12);
-        addbyte(0xf7); /*TEST EDI, 0xffc*/
+        addbyte(0xf7); /*TEST EDI, 3*/
         addbyte(0xc7);
-        addlong(0xffc);
+        addlong(3);
         addbyte(0x8b); /*MOV ESI, readlookup2[ESI*4]*/
         addbyte(0x04 | (REG_ESI << 3));
         addbyte(0x85 | (REG_ESI << 3));
         addlong((uint32_t)writelookup2);
-        addbyte(0x74); /*JE slowpath*/
-        addbyte(3+2+4+1);
+        addbyte(0x75); /*JNE slowpath*/
+        addbyte(3+2+3+1);
         addbyte(0x83); /*CMP ESI, -1*/
         addbyte(0xf8 | REG_ESI);
         addbyte(-1);
         addbyte(0x74); /*JE slowpath*/
-        addbyte(4+1);
-        addbyte(0x89); /*MOV -3[EDI+ESI],ECX*/
-        addbyte(0x44 | (REG_ECX << 3));
+        addbyte(3+1);
+        addbyte(0x89); /*MOV [EDI+ESI],ECX*/
+        addbyte(0x04 | (REG_ECX << 3));
         addbyte(REG_EDI | (REG_ESI << 3));
-        addbyte(-3);
         addbyte(0xc3); /*RET*/
 
         addbyte(0x51); /*slowpath: PUSH ECX*/
diff --git a/src/CPU/cpu.c b/src/CPU/cpu.c
index 5f6f00b16..0f12a59f1 100644
--- a/src/CPU/cpu.c
+++ b/src/CPU/cpu.c
@@ -91,6 +91,7 @@ int cpu_hasrdtsc;
 int cpu_hasMMX, cpu_hasMSR;
 int cpu_hasCR4;
 int cpu_use_dynarec;
+int cpu_cyrix_alignment;
 
 int hasfpu;
 
@@ -152,6 +153,7 @@ int timing_iret_rm, timing_iret_v86, timing_iret_pm, timing_iret_pm_outer;
 int timing_call_rm, timing_call_pm, timing_call_pm_gate, timing_call_pm_gate_inner;
 int timing_retf_rm, timing_retf_pm, timing_retf_pm_outer;
 int timing_jmp_rm, timing_jmp_pm, timing_jmp_pm_gate;
+int timing_misaligned;
 
 static struct
 {
@@ -203,6 +205,15 @@ CPU cpus_pcjr[] =
         {"",             -1,        0, 0, 0, 0, 0,0,0,0}
 };
 
+CPU cpus_europc[] =
+{
+         /*8088 EuroPC*/
+         {"8088/4.77",    CPU_8088,  0,  4772728,   1, 0, 0, 0, 0, 0, 0,0,0,0},
+         {"8088/7.16",    CPU_8088,  1, 14318184/2, 1, 0, 0, 0, 0, 0, 0,0,0,0},
+         {"8088/9.54",    CPU_8088,  1,  4772728*2, 1, 0, 0, 0, 0, 0, 0,0,0,0},
+         {"",             -1,        0, 0, 0, 0}
+};
+
 CPU cpus_8086[] =
 {
         /*8086 standard*/
@@ -746,7 +757,10 @@ void cpu_set()
         }
 
         memset(&msr, 0, sizeof(msr));
-        
+
+        timing_misaligned = 0;
+        cpu_cyrix_alignment = 0;
+
         switch (cpu_s->cpu_type)
         {
                 case CPU_8088:
@@ -940,6 +954,7 @@ void cpu_set()
                 timing_jmp_rm      = 9;
                 timing_jmp_pm      = 26;
                 timing_jmp_pm_gate = 37;
+                timing_misaligned = 3;
                 break;
                 
                 case CPU_486DLC:
@@ -973,6 +988,7 @@ void cpu_set()
                 timing_jmp_rm      = 9;
                 timing_jmp_pm      = 26;
                 timing_jmp_pm_gate = 37;
+                timing_misaligned = 3;
                 break;
                 
                 case CPU_i486SX:
@@ -1006,6 +1022,7 @@ void cpu_set()
                 timing_jmp_rm      = 17;
                 timing_jmp_pm      = 19;
                 timing_jmp_pm_gate = 32;
+                timing_misaligned = 3;
                 break;
 
                 case CPU_Am486SX:
@@ -1040,6 +1057,7 @@ void cpu_set()
                 timing_jmp_rm      = 17;
                 timing_jmp_pm      = 19;
                 timing_jmp_pm_gate = 32;
+                timing_misaligned = 3;
                 break;
                 
                 case CPU_Cx486S:
@@ -1073,6 +1091,7 @@ void cpu_set()
                 timing_jmp_rm      = 9;
                 timing_jmp_pm      = 26;
                 timing_jmp_pm_gate = 37;
+                timing_misaligned = 3;
                 break;
                 
                 case CPU_Cx5x86:
@@ -1105,6 +1124,8 @@ void cpu_set()
                 timing_jmp_rm      = 5;
                 timing_jmp_pm      = 7;
                 timing_jmp_pm_gate = 17;
+                timing_misaligned = 2;
+                cpu_cyrix_alignment = 1;
                 break;
 
                 case CPU_WINCHIP:
@@ -1143,6 +1164,8 @@ void cpu_set()
                 timing_jmp_pm      = 7;
                 timing_jmp_pm_gate = 17;
                 codegen_timing_set(&codegen_timing_winchip);
+                timing_misaligned = 2;
+                cpu_cyrix_alignment = 1;
                 break;
 
                 case CPU_PENTIUM:
@@ -1175,6 +1198,7 @@ void cpu_set()
                 timing_jmp_rm      = 3;
                 timing_jmp_pm      = 3;
                 timing_jmp_pm_gate = 18;
+                timing_misaligned = 3;
                 cpu_hasrdtsc = 1;
                 msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) |  (1 << 16) | (1 << 19) | (1 << 21);
                 cpu_hasMMX = 0;
@@ -1214,6 +1238,7 @@ void cpu_set()
                 timing_jmp_rm      = 3;
                 timing_jmp_pm      = 3;
                 timing_jmp_pm_gate = 18;
+                timing_misaligned = 3;
                 cpu_hasrdtsc = 1;
                 msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) |  (1 << 16) | (1 << 19) | (1 << 21);
                 cpu_hasMMX = 1;
@@ -1252,6 +1277,8 @@ void cpu_set()
                 timing_jmp_rm      = 1;
                 timing_jmp_pm      = 4;
                 timing_jmp_pm_gate = 14;
+                timing_misaligned = 2;
+                cpu_cyrix_alignment = 1;
                 cpu_hasrdtsc = 1;
                 msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) |  (1 << 16) | (1 << 19) | (1 << 21);
                 cpu_hasMMX = 0;
@@ -1290,6 +1317,8 @@ void cpu_set()
                 timing_jmp_rm      = 1;
                 timing_jmp_pm      = 4;
                 timing_jmp_pm_gate = 14;
+                timing_misaligned = 2;
+                cpu_cyrix_alignment = 1;
                 cpu_hasrdtsc = 1;
                 msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) |  (1 << 16) | (1 << 19) | (1 << 21);
                 cpu_hasMMX = 0;
@@ -1311,6 +1340,8 @@ void cpu_set()
                 timing_mml = 2;
                 timing_bt  = 5-1; /*branch taken*/
                 timing_bnt = 1; /*branch not taken*/
+                timing_misaligned = 2;
+                cpu_cyrix_alignment = 1;
                 cpu_hasrdtsc = 1;
                 msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) |  (1 << 16) | (1 << 19) | (1 << 21);
                 cpu_hasMMX = 0;
@@ -1362,6 +1393,8 @@ void cpu_set()
                 timing_jmp_rm      = 1;
                 timing_jmp_pm      = 4;
                 timing_jmp_pm_gate = 14;
+                timing_misaligned = 2;
+                cpu_cyrix_alignment = 1;
                 cpu_hasrdtsc = 1;
                 msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) |  (1 << 16) | (1 << 19) | (1 << 21);
                 cpu_hasMMX = 1;
@@ -1384,6 +1417,7 @@ void cpu_set()
                 timing_mml = 3;
                 timing_bt  = 0; /*branch taken*/
                 timing_bnt = 1; /*branch not taken*/
+                timing_misaligned = 3;
                 cpu_hasrdtsc = 1;
                 msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) |  (1 << 16) | (1 << 19) | (1 << 21);
                 cpu_hasMMX = 1;
@@ -1403,6 +1437,7 @@ void cpu_set()
                 timing_mml = 3;
                 timing_bt  = 0; /*branch taken*/
                 timing_bnt = 1; /*branch not taken*/
+                timing_misaligned = 3;
                 cpu_hasrdtsc = 1;
                 msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) |  (1 << 16) | (1 << 19) | (1 << 21);
                 cpu_hasMMX = 1;
@@ -1435,6 +1470,7 @@ void cpu_set()
                 timing_mml = 1;
                 timing_bt  = 0; /*branch taken*/
                 timing_bnt = 1; /*branch not taken*/
+                timing_misaligned = 3;
                 cpu_hasrdtsc = 1;
                 msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) |  (1 << 16) | (1 << 19) | (1 << 21);
                 cpu_hasMMX = 0;
@@ -1468,6 +1504,7 @@ void cpu_set()
                 timing_mml = 1;
                 timing_bt  = 0; /*branch taken*/
                 timing_bnt = 1; /*branch not taken*/
+                timing_misaligned = 3;
                 cpu_hasrdtsc = 1;
                 msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) |  (1 << 16) | (1 << 19) | (1 << 21);
                 cpu_hasMMX = 1;
@@ -1501,6 +1538,7 @@ void cpu_set()
                 timing_mml = 1;
                 timing_bt  = 0; /*branch taken*/
                 timing_bnt = 1; /*branch not taken*/
+                timing_misaligned = 3;
                 cpu_hasrdtsc = 1;
                 msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) |  (1 << 16) | (1 << 19) | (1 << 21);
                 cpu_hasMMX = 1;
diff --git a/src/CPU/cpu.h b/src/CPU/cpu.h
index ce0955b7f..b792b36b8 100644
--- a/src/CPU/cpu.h
+++ b/src/CPU/cpu.h
@@ -82,6 +82,8 @@ extern int timing_call_rm, timing_call_pm, timing_call_pm_gate, timing_call_pm_g
 extern int timing_retf_rm, timing_retf_pm, timing_retf_pm_outer;
 extern int timing_jmp_rm, timing_jmp_pm, timing_jmp_pm_gate;
 
+extern int timing_misaligned;
+
 
 typedef struct
 {
@@ -124,6 +126,7 @@ extern CPU cpus_Pentium2[];
 extern CPU cpus_Pentium2D[];
 
 extern CPU cpus_pcjr[];
+extern CPU cpus_europc[];
 extern CPU cpus_pc1512[];
 extern CPU cpus_ibmat[];
 extern CPU cpus_ps1_m2011[];
@@ -134,6 +137,8 @@ extern int cpu_iscyrix;
 extern int cpu_16bitbus;
 extern int cpu_busspeed;
 extern int cpu_multi;
+/*Cyrix 5x86/6x86 only has data misalignment penalties when crossing 8-byte boundaries*/
+extern int cpu_cyrix_alignment;
 
 extern int cpu_hasrdtsc;
 extern int cpu_hasMSR;
diff --git a/src/ibm.h b/src/ibm.h
index 4291d095e..a95d3635e 100644
--- a/src/ibm.h
+++ b/src/ibm.h
@@ -36,8 +36,8 @@ extern int writelnext;
 extern int mmu_perm;
 
 #define readmemb(a) ((readlookup2[(a)>>12]==-1)?readmembl(a):*(uint8_t *)(readlookup2[(a) >> 12] + (a)))
-#define readmemw(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF || (((s)+(a))&0xFFF)>0xFFE)?readmemwl(s,a):*(uint16_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
-#define readmeml(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF || (((s)+(a))&0xFFF)>0xFFC)?readmemll(s,a):*(uint32_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
+#define readmemw(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF || (((s)+(a)) & 1))?readmemwl(s,a):*(uint16_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
+#define readmeml(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF || (((s)+(a)) & 3))?readmemll(s,a):*(uint32_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
 
 extern uint8_t	readmembl(uint32_t addr);
 extern void	writemembl(uint32_t addr, uint8_t val);
diff --git a/src/mem.c b/src/mem.c
index bbf4e57d8..17b564a9e 100644
--- a/src/mem.c
+++ b/src/mem.c
@@ -1281,25 +1281,29 @@ void writememb386l(uint32_t seg, uint32_t addr, uint8_t val)
 uint16_t readmemwl(uint32_t seg, uint32_t addr)
 {
         uint32_t addr2 = mem_logical_addr = seg + addr;
-        if ((addr2&0xFFF)>0xFFE)
-        {
-                if (addr2 < 0x100000 && ram_mapped_addr[addr2 >> 14] && ram_mapped_addr[(addr2+1) >> 14])
-                {
-                        return readmembl(seg+addr)|(readmembl(seg+addr+1)<<8);
-                }
-                if (cr0>>31)
-                {
-                        if (mmutranslate_read(addr2)   == 0xffffffff) return 0xffff;
-                        if (mmutranslate_read(addr2+1) == 0xffffffff) return 0xffff;
-                }
-                if (is386) return readmemb386l(seg,addr)|(readmemb386l(seg,addr+1)<<8);
-                else       return readmembl(seg+addr)|(readmembl(seg+addr+1)<<8);
-        }
+
         if (seg==-1)
         {
                 x86gpf("NULL segment", 0);
                 return -1;
         }
+        if (addr2 & 1)
+        {
+                if (!cpu_cyrix_alignment || (addr2 & 7) == 7)
+                        cycles -= timing_misaligned;
+                if ((addr2 & 0xFFF) > 0xFFE)
+                {
+                        if (cr0 >> 31)
+                        {
+                                if (mmutranslate_read(addr2)   == 0xffffffff) return 0xffff;
+                                if (mmutranslate_read(addr2+1) == 0xffffffff) return 0xffff;
+                        }
+                        if (is386) return readmemb386l(seg,addr)|(readmemb386l(seg,addr+1)<<8);
+                        else       return readmembl(seg+addr)|(readmembl(seg+addr+1)<<8);
+                }
+                else if (readlookup2[addr2 >> 12] != -1)
+                        return *(uint16_t *)(readlookup2[addr2 >> 12] + addr2);
+        }
         if (addr2 < 0x100000 && ram_mapped_addr[addr2 >> 14])
         {
                 addr = (ram_mapped_addr[addr2 >> 14] & MEM_MAP_TO_SHADOW_RAM_MASK) ? addr2 : (ram_mapped_addr[addr2 >> 14] & ~0x3FFF) + (addr2 & 0x3FFF);
@@ -1327,31 +1331,6 @@ uint16_t readmemwl(uint32_t seg, uint32_t addr)
 void writememwl(uint32_t seg, uint32_t addr, uint16_t val)
 {
         uint32_t addr2 = mem_logical_addr = seg + addr;
-        if ((addr2&0xFFF)>0xFFE)
-        {
-                if (addr2 < 0x100000 && ram_mapped_addr[addr2 >> 14])
-                {
-                        writemembl(seg+addr,val);
-                        writemembl(seg+addr+1,val>>8);
-                        return;
-                }
-                if (cr0>>31)
-                {
-                        if (mmutranslate_write(addr2)   == 0xffffffff) return;
-                        if (mmutranslate_write(addr2+1) == 0xffffffff) return;
-                }
-                if (is386)
-                {
-                        writememb386l(seg,addr,val);
-                        writememb386l(seg,addr+1,val>>8);
-                }
-                else
-                {
-                        writemembl(seg+addr,val);
-                        writemembl(seg+addr+1,val>>8);
-                }
-                return;
-        }
 
         if (seg==-1)
         {
@@ -1364,6 +1343,37 @@ void writememwl(uint32_t seg, uint32_t addr, uint16_t val)
                 if(addr < mem_size * 1024) *((uint16_t *)&ram[addr]) = val;
                 return;
         }
+
+        if (addr2 & 1)
+        {
+                if (!cpu_cyrix_alignment || (addr2 & 7) == 7)
+                        cycles -= timing_misaligned;
+                if ((addr2 & 0xFFF) > 0xFFE)
+                {
+                        if (cr0 >> 31)
+                        {
+                                if (mmutranslate_write(addr2)   == 0xffffffff) return;
+                                if (mmutranslate_write(addr2+1) == 0xffffffff) return;
+                        }
+                        if (is386)
+                        {
+                                writememb386l(seg,addr,val);
+                                writememb386l(seg,addr+1,val>>8);
+                        }
+                        else
+                        {
+                                writemembl(seg+addr,val);
+                                writemembl(seg+addr+1,val>>8);
+                        }
+                        return;
+                }
+                else if (writelookup2[addr2 >> 12] != -1)
+                {
+                        *(uint16_t *)(writelookup2[addr2 >> 12] + addr2) = val;
+                        return;
+                }
+        }
+
         if (page_lookup[addr2>>12])
         {
                 page_lookup[addr2>>12]->write_w(addr2, val, page_lookup[addr2>>12]);
@@ -1397,19 +1407,6 @@ void writememwl(uint32_t seg, uint32_t addr, uint16_t val)
 uint32_t readmemll(uint32_t seg, uint32_t addr)
 {
         uint32_t addr2 = mem_logical_addr = seg + addr;
-        if ((addr2&0xFFF)>0xFFC)
-        {
-                if (addr2 < 0x100000 && (ram_mapped_addr[addr2 >> 14] || ram_mapped_addr[(addr2+3) >> 14]))
-                {
-                        return readmemwl(seg,addr)|(readmemwl(seg,addr+2)<<16);
-                }
-                if (cr0>>31)
-                {
-                        if (mmutranslate_read(addr2)   == 0xffffffff) return 0xffffffff;
-                        if (mmutranslate_read(addr2+3) == 0xffffffff) return 0xffffffff;
-                }
-                return readmemwl(seg,addr)|(readmemwl(seg,addr+2)<<16);
-        }
 
         if (seg==-1)
         {
@@ -1423,6 +1420,24 @@ uint32_t readmemll(uint32_t seg, uint32_t addr)
                 if(addr < mem_size * 1024) return *((uint32_t *)&ram[addr]);
                 return 0xFFFFFFFF;
         }
+
+        if (addr2 & 3)
+        {
+                if (!cpu_cyrix_alignment || (addr2 & 7) > 4)
+                        cycles -= timing_misaligned;
+                if ((addr2&0xFFF)>0xFFC)
+                {
+                        if (cr0>>31)
+                        {
+                                if (mmutranslate_read(addr2)   == 0xffffffff) return 0xffffffff;
+                                if (mmutranslate_read(addr2+3) == 0xffffffff) return 0xffffffff;
+                        }
+                        return readmemwl(seg,addr)|(readmemwl(seg,addr+2)<<16);
+                }
+                else if (readlookup2[addr2 >> 12] != -1)
+                        return *(uint32_t *)(readlookup2[addr2 >> 12] + addr2);
+        }
+
         if (cr0>>31)
         {
                 addr2 = mmutranslate_read(addr2);
@@ -1444,17 +1459,6 @@ void writememll(uint32_t seg, uint32_t addr, uint32_t val)
 {
         uint32_t addr2 = mem_logical_addr = seg + addr;
 
-        if ((addr2&0xFFF)>0xFFC)
-        {
-                if (cr0>>31)
-                {
-                        if (mmutranslate_write(addr2)   == 0xffffffff) return;
-                        if (mmutranslate_write(addr2+3) == 0xffffffff) return;
-                }
-                writememwl(seg,addr,val);
-                writememwl(seg,addr+2,val>>16);
-                return;
-        }
         if (seg==-1)
         {
                 x86gpf("NULL segment", 0);
@@ -1466,6 +1470,27 @@ void writememll(uint32_t seg, uint32_t addr, uint32_t val)
                 if(addr < mem_size * 1024) *((uint32_t *)&ram[addr]) = val;
                 return;
         }
+        if (addr2 & 3)
+        {
+                if (!cpu_cyrix_alignment || (addr2 & 7) > 4)
+                        cycles -= timing_misaligned;
+                if ((addr2 & 0xFFF) > 0xFFC)
+                {
+                        if (cr0>>31)
+                        {
+                                if (mmutranslate_write(addr2)   == 0xffffffff) return;
+                                if (mmutranslate_write(addr2+3) == 0xffffffff) return;
+                        }
+                        writememwl(seg,addr,val);
+                        writememwl(seg,addr+2,val>>16);
+                        return;
+                }
+                else if (writelookup2[addr2 >> 12] != -1)
+                {
+                        *(uint32_t *)(writelookup2[addr2 >> 12] + addr2) = val;
+                        return;
+                }
+        }
         if (page_lookup[addr2>>12])
         {
                 page_lookup[addr2>>12]->write_l(addr2, val, page_lookup[addr2>>12]);
@@ -1503,15 +1528,6 @@ void writememll(uint32_t seg, uint32_t addr, uint32_t val)
 uint64_t readmemql(uint32_t seg, uint32_t addr)
 {
         uint32_t addr2 = mem_logical_addr = seg + addr;
-        if ((addr2&0xFFF)>0xFF8)
-        {
-                if (cr0>>31)
-                {
-                        if (mmutranslate_read(addr2)   == 0xffffffff) return 0xffffffff;
-                        if (mmutranslate_read(addr2+7) == 0xffffffff) return 0xffffffff;
-                }
-                return readmemll(seg,addr)|((uint64_t)readmemll(seg,addr+4)<<32);
-        }
 
         if (seg==-1)
         {
@@ -1525,6 +1541,23 @@ uint64_t readmemql(uint32_t seg, uint32_t addr)
                 if(addr < mem_size * 1024) return *((uint64_t *)&ram[addr]);
                 return -1;
         }
+
+        if (addr2 & 7)
+        {
+                cycles -= timing_misaligned;
+                if ((addr2 & 0xFFF) > 0xFF8)
+                {
+                        if (cr0>>31)
+                        {
+                                if (mmutranslate_read(addr2)   == 0xffffffff) return 0xffffffff;
+                                if (mmutranslate_read(addr2+7) == 0xffffffff) return 0xffffffff;
+                        }
+                        return readmemll(seg,addr)|((uint64_t)readmemll(seg,addr+4)<<32);
+                }
+                else if (readlookup2[addr2 >> 12] != -1)
+                        return *(uint64_t *)(readlookup2[addr2 >> 12] + addr2);
+        }
+        
         if (cr0>>31)
         {
                 addr2 = mmutranslate_read(addr2);
@@ -1544,17 +1577,6 @@ void writememql(uint32_t seg, uint32_t addr, uint64_t val)
 {
         uint32_t addr2 = mem_logical_addr = seg + addr;
 
-        if ((addr2 & 0xFFF) > 0xFF8)
-        {
-                if (cr0>>31)
-                {
-                        if (mmutranslate_write(addr2)   == 0xffffffff) return;
-                        if (mmutranslate_write(addr2+7) == 0xffffffff) return;
-                }
-                writememll(seg, addr, val);
-                writememll(seg, addr+4, val >> 32);
-                return;
-        }
         if (seg==-1)
         {
                 x86gpf("NULL segment", 0);
@@ -1566,6 +1588,26 @@ void writememql(uint32_t seg, uint32_t addr, uint64_t val)
                 if(addr < mem_size * 1024) *((uint64_t *)&ram[addr]) = val;
                 return;
         }
+        if (addr2 & 7)
+        {
+                cycles -= timing_misaligned;
+                if ((addr2 & 0xFFF) > 0xFF8)
+                {
+                        if (cr0>>31)
+                        {
+                                if (mmutranslate_write(addr2)   == 0xffffffff) return;
+                                if (mmutranslate_write(addr2+7) == 0xffffffff) return;
+                        }
+                        writememll(seg, addr, val);
+                        writememll(seg, addr+4, val >> 32);
+                        return;
+                }
+                else if (writelookup2[addr2 >> 12] != -1)
+                {
+                        *(uint64_t *)(writelookup2[addr2 >> 12] + addr2) = val;
+                        return;
+                }
+        }
         if (page_lookup[addr2>>12])
         {
                 page_lookup[addr2>>12]->write_l(addr2, val, page_lookup[addr2>>12]);
diff --git a/src/model.c b/src/model.c
index b08d3a01f..9e4dc6b7e 100644
--- a/src/model.c
+++ b/src/model.c
@@ -173,7 +173,7 @@ MODEL models[] =
         {"Tandy 1000 SL/2",		ROM_TANDY1000SL2,	"tandy1000sl2",		{ "",      cpus_8086,        "",    NULL,         "",      NULL,        "",      NULL,     "",      NULL}, 1, 0,						512,  768, 128,     tandy1ksl2_init, NULL},
         {"Amstrad PC1512",		ROM_PC1512,		"pc1512",		{ "",      cpus_pc1512,      "",    NULL,         "",      NULL,        "",      NULL,     "",      NULL}, 1, MODEL_AMSTRAD,					512,  640, 128,            ams_init, NULL},
         {"Sinclair PC200",		ROM_PC200,		"pc200",		{ "",      cpus_8086,        "",    NULL,         "",      NULL,        "",      NULL,     "",      NULL}, 1, MODEL_AMSTRAD,					512,  640, 128,            ams_init, NULL},
-        {"Euro PC",			ROM_EUROPC,		"europc",		{ "",      cpus_8086,        "",    NULL,         "",      NULL,        "",      NULL,     "",      NULL}, 0, 0,						512,  640, 128,         europc_init, NULL},
+        {"Schneider EuroPC",		ROM_EUROPC,		"europc",		{ "",      cpus_europc,      "",    NULL,         "",      NULL,        "",      NULL,     "",      NULL}, 0, 0,						512,  640, 128,         europc_init, NULL},
         {"Olivetti M24",		ROM_OLIM24,		"olivetti_m24",		{ "",      cpus_8086,        "",    NULL,         "",      NULL,        "",      NULL,     "",      NULL}, 1, MODEL_OLIM24,					128,  640, 128,         olim24_init, NULL},
         {"Amstrad PC1640",		ROM_PC1640,		"pc1640",		{ "",      cpus_8086,        "",    NULL,         "",      NULL,        "",      NULL,     "",      NULL}, 1, MODEL_AMSTRAD,					640,  640,   0,            ams_init, NULL},
         {"Amstrad PC2086",		ROM_PC2086,		"pc2086",		{ "",      cpus_8086,        "",    NULL,         "",      NULL,        "",      NULL,     "",      NULL}, 1, MODEL_AMSTRAD,					640,  640,   0,            ams_init, NULL},