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Merge branch 'master' into master

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This commit is contained in:
Miran Grča
2021-04-06 07:24:30 +02:00
committed by GitHub
parent 8edf104668 afa73c5bd6
commit 091b45c104
23 changed files with 522 additions and 122 deletions
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8
src/chipset/CMakeLists.txt
View File

@@ -13,8 +13,8 @@
# Copyright 2020,2021 David Hrdlička.
#
add_library(chipset OBJECT acc2168.c cs8230.c ali1217.c ali1429.c headland.c intel_82335.c
cs4031.c intel_420ex.c intel_4x0.c intel_sio.c intel_piix.c ../ioapic.c
add_library(chipset OBJECT acc2168.c cs8230.c ali1217.c ali1429.c ali1489.c headland.c
intel_82335.c cs4031.c intel_420ex.c intel_4x0.c intel_sio.c intel_piix.c ../ioapic.c
neat.c opti283.c opti291.c opti495.c opti822.c opti895.c opti5x7.c scamp.c scat.c
sis_85c310.c sis_85c4xx.c sis_85c496.c sis_85c50x.c
umc_8886.c umc_8890.c umc_hb4.c
@@ -27,10 +27,6 @@ if(I450KX)
target_sources(chipset PRIVATE intel_i450kx.c)
endif()
if(M1489)
target_sources(chipset PRIVATE ali1489.c)
endif()
if(M154X)
target_sources(chipset PRIVATE ali1531.c)
target_sources(chipset PRIVATE ali1543.c)

38
src/chipset/via_vt82c49x.c
View File

@@ -25,14 +25,10 @@
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/mem.h>
#include <86box/smram.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/pic.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
@@ -237,6 +233,8 @@ vt82c49x_write(uint16_t addr, uint8_t val, void *priv)
ide_set_side(0, (val & 0x40) ? 0x376 : 0x3f6);
if (val & 0x01)
ide_pri_enable();
pclog("VT82C496 IDE now %sabled as %sary\n", (val & 0x01) ? "en": "dis",
(val & 0x40) ? "second" : "prim");
}
break;
}
@@ -257,7 +255,7 @@ vt82c49x_read(uint16_t addr, void *priv)
ret = pic_elcr_read(dev->index, &pic2) | (dev->regs[dev->index] & 0x01);
else if (dev->index == 0x62)
ret = pic_elcr_read(dev->index, &pic) | (dev->regs[dev->index] & 0x07);
else
else if (dev->index < 0x80)
ret = dev->regs[dev->index];
break;
}
@@ -266,6 +264,16 @@ vt82c49x_read(uint16_t addr, void *priv)
}
static void
vt82c49x_reset(void *priv)
{
uint8_t i;
for (i = 0; i < 256; i++)
vt82c49x_write(i, 0x00, priv);
}
static void
vt82c49x_close(void *priv)
{
@@ -316,6 +324,16 @@ const device_t via_vt82c49x_device = {
};
const device_t via_vt82c49x_pci_device = {
"VIA VT82C49X PCI",
DEVICE_PCI,
0,
vt82c49x_init, vt82c49x_close, vt82c49x_reset,
{ NULL }, NULL, NULL,
NULL
};
const device_t via_vt82c49x_ide_device = {
"VIA VT82C49X (With IDE)",
0,
@@ -324,3 +342,13 @@ const device_t via_vt82c49x_ide_device = {
{ NULL }, NULL, NULL,
NULL
};
const device_t via_vt82c49x_pci_ide_device = {
"VIA VT82C49X PCI (With IDE)",
DEVICE_PCI,
1,
vt82c49x_init, vt82c49x_close, vt82c49x_reset,
{ NULL }, NULL, NULL,
NULL
};

141
src/chipset/via_vt82c505.c
View File

@@ -32,55 +32,85 @@
typedef struct vt82c505_t
{
uint8_t pci_conf[256];
uint8_t index;
uint8_t pci_conf[256];
} vt82c505_t;
static void
vt82c505_write(int func, int addr, uint8_t val, void *priv)
{
vt82c505_t *dev = (vt82c505_t *) priv;
uint8_t irq;
const uint8_t irq_array[8] = { 0, 5, 9, 10, 11, 14, 15, 0 };
/* Read-Only Registers */
switch (addr) {
case 0x00: case 0x01:
case 0x02: case 0x03:
return;
}
pclog("vt82c505_write(%02X, %02X, %02X)\n", func, addr, val);
if (func != 0)
return;
switch(addr) {
/* RX00-07h: Mandatory header field */
case 0x04:
dev->pci_conf[0x04] = (dev->pci_conf[0x04] & ~0x07) | (val & 0x07);
dev->pci_conf[addr] = (dev->pci_conf[addr] & 0xbf) | (val & 0x40);
break;
case 0x07:
dev->pci_conf[0x07] &= ~(val & 0x90);
dev->pci_conf[addr] &= ~(val & 0x90);
break;
case 0x90:
if ((dev->pci_conf[0x90] & 0x08) && ((val & 0x07) != 0))
pci_set_irq_routing(PCI_INTC, val & 0x07);
/* RX80-9F: VT82C505 internal configuration registers */
case 0x80:
dev->pci_conf[addr] = (dev->pci_conf[addr] & 0x0f) | (val & 0xf0);
break;
case 0x81: case 0x84: case 0x85: case 0x87:
case 0x88: case 0x89: case 0x8a: case 0x8b:
case 0x8c: case 0x8d: case 0x8e: case 0x8f:
case 0x92: case 0x94:
dev->pci_conf[addr] = val;
break;
case 0x82:
dev->pci_conf[addr] = val & 0xdb;
break;
case 0x83:
dev->pci_conf[addr] = val & 0xf9;
break;
case 0x86:
dev->pci_conf[addr] = val & 0xef;
/* Bit 7 switches between the two PCI configuration mechanisms:
0 = configuration mechanism 1, 1 = configuration mechanism 2 */
pci_set_pmc(!(val & 0x80));
break;
case 0x90:
dev->pci_conf[addr] = val;
irq = irq_array[val & 0x07];
if ((val & 0x08) && (irq != 0))
pci_set_irq_routing(PCI_INTC, irq);
else
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
if ((dev->pci_conf[0x90] & 0x80) && (((val & 0x07) << 4) != 0))
pci_set_irq_routing(PCI_INTD, ((val & 0x07) << 4));
irq = irq_array[(val & 0x70) >> 4];
if ((val & 0x80) && (irq != 0))
pci_set_irq_routing(PCI_INTD, irq);
else
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
break;
case 0x91:
if ((dev->pci_conf[0x91] & 0x08) && ((val & 0x07) != 0))
pci_set_irq_routing(PCI_INTA, val & 0x07);
dev->pci_conf[addr] = val;
irq = irq_array[val & 0x07];
if ((val & 0x08) && (irq != 0))
pci_set_irq_routing(PCI_INTA, irq);
else
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
if ((dev->pci_conf[0x91] & 0x80) && (((val & 0x07) << 4) != 0))
pci_set_irq_routing(PCI_INTB, ((val & 0x07) << 4));
irq = irq_array[(val & 0x70) >> 4];
if ((val & 0x80) && (irq != 0))
pci_set_irq_routing(PCI_INTB, irq);
else
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
break;
case 0x93:
dev->pci_conf[addr] = val & 0xe0;
break;
}
}
@@ -91,8 +121,42 @@ vt82c505_read(int func, int addr, void *priv)
vt82c505_t *dev = (vt82c505_t *) priv;
uint8_t ret = 0xff;
if (func != 0)
return ret;
ret = dev->pci_conf[addr];
pclog("vt82c505_read(%02X, %02X) = %02X\n", func, addr, ret);
return ret;
}
static void
vt82c505_out(uint16_t addr, uint8_t val, void *priv)
{
vt82c505_t *dev = (vt82c505_t *) priv;
pclog("vt82c505_out(%04X, %02X)\n", addr, val);
if (addr == 0xa8)
dev->index = val;
else if ((addr == 0xa9) && (dev->index >= 0x80) && (dev->index <= 0x9f))
vt82c505_write(0, dev->index, val, priv);
}
static uint8_t
vt82c505_in(uint16_t addr, void *priv)
{
vt82c505_t *dev = (vt82c505_t *) priv;
uint8_t ret = 0xff;
if ((addr == 0xa9) && (dev->index >= 0x80) && (dev->index <= 0x9f))
ret = vt82c505_read(0, dev->index, priv);
pclog("vt82c505_in(%04X) = %02X\n", addr, ret);
return ret;
}
@@ -100,10 +164,28 @@ vt82c505_read(int func, int addr, void *priv)
static void
vt82c505_reset(void *priv)
{
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
vt82c505_t *dev = (vt82c505_t *) malloc(sizeof(vt82c505_t));
int i;
dev->pci_conf[0x04] = 0x07;
dev->pci_conf[0x07] = 0x00;
for (i = 0x80; i <= 0x9f; i++) {
switch (i) {
case 0x81:
vt82c505_write(0, i, 0x01, priv);
break;
case 0x84:
vt82c505_write(0, i, 0x03, priv);
break;
case 0x93:
vt82c505_write(0, i, 0x40, priv);
break;
default:
vt82c505_write(0, i, 0x00, priv);
break;
}
}
pic_reset();
}
@@ -128,19 +210,16 @@ vt82c505_init(const device_t *info)
dev->pci_conf[0x00] = 0x06;
dev->pci_conf[0x01] = 0x11;
dev->pci_conf[0x02] = 0x05;
dev->pci_conf[0x03] = 0x05;
dev->pci_conf[0x04] = 0x07;
dev->pci_conf[0x07] = 0x90;
dev->pci_conf[0x07] = 0x00;
dev->pci_conf[0x81] = 0x01;
dev->pci_conf[0x84] = 0x03;
dev->pci_conf[0x93] = 0x40;
io_sethandler(0x0a8, 0x0002, vt82c505_in, NULL, NULL, vt82c505_out, NULL, NULL, dev);
return dev;
}