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Added a second set of physical address byte read and write functions in mem.c that are now used by dma.c so that DMA reads and writes do not go through the CPU's paging mechanism anymore - fixes Adaptec and BusLogic SCSI drivers in NT 3.1;

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Applied some more of greatpsycho's CPU patches;
Reworked the PS/2 Model 80 split memory block handling and removed the top 256k remap from it (that's what the split memory block is for) - fixes OS/2 2.x on that machine.
This commit is contained in:
OBattler
2017-12-11 19:41:58 +01:00
parent 19c5e93a3c
commit 0a11a6d3b4
7 changed files with 243 additions and 176 deletions
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16
src/cpu/x86seg.c
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@@ -24,6 +24,7 @@
#include <wchar.h>
#include "../86box.h"
#include "cpu.h"
#include "../machine/machine.h"
#include "../mem.h"
#include "../nvr.h"
#include "x86.h"
@@ -78,6 +79,19 @@ static void seg_reset(x86seg *s)
s->limit = 0xFFFF;
s->limit_low = 0;
s->limit_high = 0xffff;
if(s == &_cs)
{
// TODO - When the PC is reset, initialization of the CS descriptor must be like the annotated line below.
//s->base = AT ? (cpu_16bitbus ? 0xFF0000 : 0xFFFF0000) : 0xFFFF0;
s->base = AT ? 0xF0000 : 0xFFFF0;
s->seg = AT ? 0xF000 : 0xFFFF;
}
else
{
s->base = 0;
s->seg = 0;
}
}
void x86seg_reset()
@@ -124,7 +138,7 @@ void x86_doabrt(int x86_abrt)
return;
}
if (cpu_state.abrt) return;
if (cpu_state.abrt || x86_was_reset) return;
if (intgatesize == 16)
{