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Ported the ISA RTC and Memory expansion cards from VARCem's.

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Bunch of improvements in the device, memory and MMU handling.
Re-worked the NEAT 286 chipset (ported from VARCem).
Re-worked the ATI 28800 a bit, added Sierra SC1502x ramdac to VGA Wonder XL (Compaq) since it supports such.
Top 384K memory handling improvements (256K top memory too)
Added MCA version of MPU-401 (not tested much, however).
Re-worked the SCAT 286 chipset.
This commit is contained in:
TC1995
2018-09-03 13:55:09 +02:00
parent 0e96d5d7a4
commit 0d2ee0a57d
29 changed files with 3605 additions and 422 deletions
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75
src/machine/m_at.c
View File

@@ -1,3 +1,41 @@
/*
* VARCem Virtual ARchaeological Computer EMulator.
* An emulator of (mostly) x86-based PC systems and devices,
* using the ISA,EISA,VLB,MCA and PCI system buses, roughly
* spanning the era between 1981 and 1995.
*
* This file is part of the VARCem Project.
*
* Standard PC/AT implementation.
*
* Version: @(#)m_at.c 1.0.0 2018/09/02
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <tommowalker@tommowalker.co.uk>
*
* Copyright 2017,2018 Fred N. van Kempen.
* Copyright 2016-2018 Miran Grca.
* Copyright 2008-2018 Sarah Walker.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the:
*
* Free Software Foundation, Inc.
* 59 Temple Place - Suite 330
* Boston, MA 02111-1307
* USA.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
@@ -46,6 +84,16 @@ machine_at_init(const machine_t *model)
}
void
machine_at_ibm_init(const machine_t *model)
{
machine_at_init(model);
mem_remap_top(384);
device_add(&fdc_at_device);
}
void
machine_at_ps2_init(const machine_t *model)
{
@@ -80,30 +128,3 @@ machine_at_ps2_ide_init(const machine_t *model)
device_add(&ide_isa_2ch_opt_device);
}
void
machine_at_top_remap_init(const machine_t *model)
{
machine_at_init(model);
mem_remap_top_384k();
}
void
machine_at_ide_top_remap_init(const machine_t *model)
{
machine_at_ide_init(model);
mem_remap_top_384k();
}
void
machine_at_ibm_init(const machine_t *model)
{
machine_at_top_remap_init(model);
device_add(&fdc_at_device);
}

44
src/machine/m_at_commodore.c
View File

@@ -1,3 +1,41 @@
/*
* VARCem Virtual ARchaeological Computer EMulator.
* An emulator of (mostly) x86-based PC systems and devices,
* using the ISA,EISA,VLB,MCA and PCI system buses, roughly
* spanning the era between 1981 and 1995.
*
* This file is part of the VARCem Project.
*
* Implementation of the Commodore PC3 system.
*
* Version: @(#)m_at_commodore.c 1.0.0 2018/09/02
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <tommowalker@tommowalker.co.uk>
*
* Copyright 2017,2018 Fred N. van Kempen.
* Copyright 2016-2018 Miran Grca.
* Copyright 2008-2018 Sarah Walker.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the:
*
* Free Software Foundation, Inc.
* 59 Temple Place - Suite 330
* Boston, MA 02111-1307
* USA.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
@@ -5,6 +43,7 @@
#include "../86box.h"
#include "../device.h"
#include "../io.h"
#include "../mem.h"
#include "../lpt.h"
#include "../serial.h"
#include "../floppy/fdd.h"
@@ -48,7 +87,10 @@ static void cbm_io_init()
void
machine_at_cmdpc_init(const machine_t *model)
{
machine_at_ide_top_remap_init(model);
machine_at_ide_init(model);
mem_remap_top(384);
device_add(&fdc_at_device);
cbm_io_init();

7
src/machine/m_at_compaq.c
View File

@@ -8,7 +8,7 @@
*
* Emulation of various Compaq PC's.
*
* Version: @(#)m_at_compaq.c 1.0.5 2018/03/18
* Version: @(#)m_at_compaq.c 1.0.6 2018/09/02
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -100,7 +100,10 @@ write_raml(uint32_t addr, uint32_t val, void *priv)
void
machine_at_compaq_init(const machine_t *model)
{
machine_at_top_remap_init(model);
machine_at_init(model);
mem_remap_top(384);
device_add(&fdc_at_device);
mem_mapping_add(&ram_mapping, 0xfa0000, 0x60000,

3
src/machine/m_at_headland.c
View File

@@ -523,9 +523,6 @@ headland_init(void)
mem_mapping_disable(&headland_ems_mapping[i]);
}
for(i=4; i<10; i++)
isram[i] = 0;
headland_memmap_state_update();
}

892
src/machine/m_at_neat.c
View File

@@ -1,89 +1,851 @@
/* Copyright holders: Sarah Walker
see COPYING for more details
/*
* VARCem Virtual ARchaeological Computer EMulator.
* An emulator of (mostly) x86-based PC systems and devices,
* using the ISA,EISA,VLB,MCA and PCI system buses, roughly
* spanning the era between 1981 and 1995.
*
* This file is part of the VARCem Project.
*
* Emulation of C&T CS8121 ("NEAT") 82C206/211/212/215 chipset.
*
* Note: The datasheet mentions that the chipset supports up to 8MB
* of DRAM. This is intepreted as 'being able to refresh up to
* 8MB of DRAM chips', because it works fine with bus-based
* memory expansion.
*
* Version: @(#)m_at_neat.c 1.0.1 2018/07/22
*
* Author: Fred N. van Kempen, <decwiz@yahoo.com>
*
* Copyright 2018 Fred N. van Kempen.
*
* Redistribution and use in source and binary forms, with
or without modification, are permitted provided that the
* following conditions are met:
*
* 1. Redistributions of source code must retain the entire
* above notice, this list of conditions and the following
* disclaimer.
*
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names
* of its contributors may be used to endorse or promote
* products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*This is the chipset used in the AMI 286 clone model*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include "../86box.h"
#include "../device.h"
#include "../io.h"
#include "../keyboard.h"
#include "../cpu/cpu.h"
#include "../cpu/x86.h"
#include "../floppy/fdd.h"
#include "../floppy/fdc.h"
#include "../keyboard.h"
#include "../io.h"
#include "../mem.h"
#include "../nmi.h"
#include "../rom.h"
#include "machine.h"
static uint8_t neat_regs[256];
static int neat_index;
static int neat_emspage[4];
#define NEAT_DEBUG 0
static void neat_write(uint16_t port, uint8_t val, void *priv)
#define EMS_MAXPAGE 4
#define EMS_PGSIZE 16384
/* CS8221 82C211 controller registers. */
#define REG_RA0 0x60 /* PROCCLK selector */
# define RA0_MASK 0x34 /* RR11 X1XR */
# define RA0_READY 0x01 /* local bus READY timeout */
# define RA0_RDYNMIEN 0x04 /* local bus READY tmo NMI enable */
# define RA0_PROCCLK 0x10 /* PROCCLK=BCLK (1) or CLK2IN (0) */
# define RA0_ALTRST 0x20 /* alternate CPU reset (1) */
# define RA0_REV 0xc0 /* chip revision ID */
# define RA0_REV_SH 6
# define RA0_REV_ID 2 /* faked revision# for 82C211 */
#define REG_RA1 0x61 /* Command Delay */
# define RA1_MASK 0xff /* 1111 1111 */
# define RA1_BUSDLY 0x03 /* AT BUS command delay */
# define RA1_BUSDLY_SH 0
# define RA1_BUS8DLY 0x0c /* AT BUS 8bit command delay */
# define RA1_BUS8DLY_SH 2
# define RA1_MEMDLY 0x30 /* AT BUS 16bit memory delay */
# define RA1_MEMDLY_SH 4
# define RA1_QUICKEN 0x40 /* Quick Mode enable */
# define RA1_HOLDDLY 0x80 /* Hold Time Delay */
#define REG_RA2 0x62 /* Wait State / BCLK selector */
# define RA2_MASK 0x3f /* XX11 1111 */
# define RA2_BCLK 0x03 /* BCLK select */
# define RA2_BCLK_SH 0
# define BCLK_IN2 0 /* BCLK = CLK2IN/2 */
# define BCLK_IN 1 /* BCLK = CLK2IN */
# define BCLK_AT 2 /* BCLK = ATCLK */
# define RA2_AT8WS 0x0c /* AT 8-bit wait states */
# define RA2_AT8WS_SH 2
# define AT8WS_2 0 /* 2 wait states */
# define AT8WS_3 1 /* 3 wait states */
# define AT8WS_4 2 /* 4 wait states */
# define AT8WS_5 4 /* 5 wait states */
# define RA2_ATWS 0x30 /* AT 16-bit wait states */
# define RA2_ATWS_SH 4
# define ATWS_2 0 /* 2 wait states */
# define ATWS_3 1 /* 3 wait states */
# define ATWS_4 2 /* 4 wait states */
# define ATWS_5 4 /* 5 wait states */
/* CS8221 82C212 controller registers. */
#define REG_RB0 0x64 /* Version ID */
# define RB0_MASK 0x60 /* R11X XXXX */
# define RB0_REV 0x60 /* Chip revsion number */
# define RB0_REV_SH 5
# define RB0_REV_ID 2 /* faked revision# for 82C212 */
# define RB0_VERSION 0x80 /* Chip version (0=82C212) */
#define REG_RB1 0x65 /* ROM configuration */
# define RB1_MASK 0xff /* 1111 1111 */
# define RB1_ROMF0 0x01 /* ROM F0000 enabled (0) */
# define RB1_ROME0 0x02 /* ROM E0000 disabled (1) */
# define RB1_ROMD0 0x04 /* ROM D0000 disabled (1) */
# define RB1_ROMC0 0x08 /* ROM C0000 disabled (1) */
# define RB1_SHADOWF0 0x10 /* Shadow F0000 R/W (0) */
# define RB1_SHADOWE0 0x20 /* Shadow E0000 R/W (0) */
# define RB1_SHADOWD0 0x40 /* Shadow D0000 R/W (0) */
# define RB1_SHADOWC0 0x80 /* Shadow C0000 R/W (0) */
#define REG_RB2 0x66 /* Memory Enable 1 */
# define RB2_MASK 0x80 /* 1XXX XXXX */
# define RB2_TOP128 0x80 /* top 128K is on sysboard (1) */
#define REG_RB3 0x67 /* Memory Enable 2 */
# define RB3_MASK 0xff /* 1111 1111 */
# define RB3_SHENB0 0x01 /* enable B0000-B3FFF shadow (1) */
# define RB3_SHENB4 0x02 /* enable B4000-B7FFF shadow (1) */
# define RB3_SHENB8 0x04 /* enable B8000-BBFFF shadow (1) */
# define RB3_SHENBC 0x08 /* enable BC000-BFFFF shadow (1) */
# define RB3_SHENA0 0x10 /* enable A0000-A3FFF shadow (1) */
# define RB3_SHENA4 0x20 /* enable A4000-A7FFF shadow (1) */
# define RB3_SHENA8 0x40 /* enable A8000-ABFFF shadow (1) */
# define RB3_SHENAC 0x80 /* enable AC000-AFFFF shadow (1) */
#define REG_RB4 0x68 /* Memory Enable 3 */
# define RB4_MASK 0xff /* 1111 1111 */
# define RB4_SHENC0 0x01 /* enable C0000-C3FFF shadow (1) */
# define RB4_SHENC4 0x02 /* enable C4000-C7FFF shadow (1) */
# define RB4_SHENC8 0x04 /* enable C8000-CBFFF shadow (1) */
# define RB4_SHENCC 0x08 /* enable CC000-CFFFF shadow (1) */
# define RB4_SHEND0 0x10 /* enable D0000-D3FFF shadow (1) */
# define RB4_SHEND4 0x20 /* enable D4000-D7FFF shadow (1) */
# define RB4_SHEND8 0x40 /* enable D8000-DBFFF shadow (1) */
# define RB4_SHENDC 0x80 /* enable DC000-DFFFF shadow (1) */
#define REG_RB5 0x69 /* Memory Enable 4 */
# define RB5_MASK 0xff /* 1111 1111 */
# define RB5_SHENE0 0x01 /* enable E0000-E3FFF shadow (1) */
# define RB5_SHENE4 0x02 /* enable E4000-E7FFF shadow (1) */
# define RB5_SHENE8 0x04 /* enable E8000-EBFFF shadow (1) */
# define RB5_SHENEC 0x08 /* enable EC000-EFFFF shadow (1) */
# define RB5_SHENF0 0x10 /* enable F0000-F3FFF shadow (1) */
# define RB5_SHENF4 0x20 /* enable F4000-F7FFF shadow (1) */
# define RB5_SHENF8 0x40 /* enable F8000-FBFFF shadow (1) */
# define RB5_SHENFC 0x80 /* enable FC000-FFFFF shadow (1) */
#define REG_RB6 0x6a /* Bank 0/1 Enable */
# define RB6_MASK 0xe0 /* 111R RRRR */
# define RB6_BANKS 0x20 /* #banks used (1=two) */
# define RB6_RTYPE 0xc0 /* DRAM chip size used */
# define RTYPE_SH 6
# define RTYPE_NONE 0 /* Disabled */
# define RTYPE_MIXED 1 /* 64K/256K mixed (for 640K) */
# define RTYPE_256K 2 /* 256K (default) */
# define RTYPE_1M 3 /* 1M */
#define REG_RB7 0x6b /* DRAM configuration */
# define RB7_MASK 0xff /* 1111 1111 */
# define RB7_ROMWS 0x03 /* ROM access wait states */
# define RB7_ROMWS_SH 0
# define ROMWS_0 0 /* 0 wait states */
# define ROMWS_1 1 /* 1 wait states */
# define ROMWS_2 2 /* 2 wait states */
# define ROMWS_3 3 /* 3 wait states (default) */
# define RB7_EMSWS 0x0c /* EMS access wait states */
# define RB7_EMSWS_SH 2
# define EMSWS_0 0 /* 0 wait states */
# define EMSWS_1 1 /* 1 wait states */
# define EMSWS_2 2 /* 2 wait states */
# define EMSWS_3 3 /* 3 wait states (default) */
# define RB7_EMSEN 0x10 /* enable EMS (1=on) */
# define RB7_RAMWS 0x20 /* RAM access wait state (1=1ws) */
# define RB7_UMAREL 0x40 /* relocate 640-1024K to 1M */
# define RB7_PAGEEN 0x80 /* enable Page/Interleaved mode */
#define REG_RB8 0x6c /* Bank 2/3 Enable */
# define RB8_MASK 0xf0 /* 1111 RRRR */
# define RB8_4WAY 0x10 /* enable 4-way interleave mode */
# define RB8_BANKS 0x20 /* enable 2 banks (1) */
# define RB8_RTYPE 0xc0 /* DRAM chip size used */
# define RB8_RTYPE_SH 6
#define REG_RB9 0x6d /* EMS base address */
# define RB9_MASK 0xff /* 1111 1111 */
# define RB9_BASE 0x0f /* I/O base address selection */
# define RB9_BASE_SH 0
# define RB9_FRAME 0xf0 /* frame address selection */
# define RB9_FRAME_SH 4
#define REG_RB10 0x6e /* EMS address extension */
# define RB10_MASK 0xff /* 1111 1111 */
# define RB10_P3EXT 0x03 /* page 3 extension */
# define RB10_P3EXT_SH 0
# define PEXT_0M 0 /* page is at 0-2M */
# define PEXT_2M 1 /* page is at 2-4M */
# define PEXT_4M 2 /* page is at 4-6M */
# define PEXT_6M 3 /* page is at 6-8M */
# define RB10_P2EXT 0x0c /* page 2 extension */
# define RB10_P2EXT_SH 2
# define RB10_P1EXT 0x30 /* page 1 extension */
# define RB10_P1EXT_SH 4
# define RB10_P0EXT 0xc0 /* page 0 extension */
# define RB10_P0EXT_SH 6
#define REG_RB11 0x6f /* Miscellaneous */
# define RB11_MASK 0xe6 /* 111R R11R */
# define RB11_GA20 0x02 /* gate for A20 */
# define RB11_RASTMO 0x04 /* enable RAS timeout counter */
# define RB11_EMSLEN 0xe0 /* EMS memory chunk size */
# define RB11_EMSLEN_SH 5
typedef struct {
int8_t enabled; /* 1=ENABLED */
char pad;
uint16_t page; /* selected page in EMS block */
uint32_t start; /* start of EMS in RAM */
uint8_t *addr; /* start addr in EMS RAM */
mem_mapping_t mapping; /* mapping entry for page */
} emspage_t;
typedef struct {
uint8_t regs[128]; /* all the CS8221 registers */
uint8_t indx; /* programmed index into registers */
char pad;
uint16_t ems_base, /* configured base address */
ems_oldbase;
uint32_t ems_frame, /* configured frame address */
ems_oldframe;
uint16_t ems_size, /* EMS size in KB */
ems_pages; /* EMS size in pages */
emspage_t ems[EMS_MAXPAGE]; /* EMS page registers */
} neat_t;
/* Read one byte from paged RAM. */
static uint8_t
ems_readb(uint32_t addr, void *priv)
{
switch (port)
{
case 0x22:
neat_index = val;
break;
case 0x23:
neat_regs[neat_index] = val;
switch (neat_index)
{
case 0x6E: /*EMS page extension*/
neat_emspage[3] = (neat_emspage[3] & 0x7F) | (( val & 3) << 7);
neat_emspage[2] = (neat_emspage[2] & 0x7F) | (((val >> 2) & 3) << 7);
neat_emspage[1] = (neat_emspage[1] & 0x7F) | (((val >> 4) & 3) << 7);
neat_emspage[0] = (neat_emspage[0] & 0x7F) | (((val >> 6) & 3) << 7);
break;
}
break;
mem_mapping_t *map = (mem_mapping_t *)priv;
neat_t *dev = (neat_t *)map->dev;
uint8_t ret = 0xff;
int vpage;
case 0x0208: case 0x0209: case 0x4208: case 0x4209:
case 0x8208: case 0x8209: case 0xC208: case 0xC209:
neat_emspage[port >> 14] = (neat_emspage[port >> 14] & 0x180) | (val & 0x7F);
break;
}
/* Get the viewport page number. */
vpage = ((addr & 0xffff) / EMS_PGSIZE);
/* Grab the data. */
ret = *(uint8_t *)(dev->ems[vpage].addr + (addr - map->base));
return(ret);
}
static uint8_t neat_read(uint16_t port, void *priv)
/* Read one word from paged RAM. */
static uint16_t
ems_readw(uint32_t addr, void *priv)
{
switch (port)
{
case 0x22:
return neat_index;
case 0x23:
return neat_regs[neat_index];
}
return 0xff;
mem_mapping_t *map = (mem_mapping_t *)priv;
neat_t *dev = (neat_t *)map->dev;
uint16_t ret = 0xffff;
int vpage;
/* Get the viewport page number. */
vpage = ((addr & 0xffff) / EMS_PGSIZE);
/* Grab the data. */
ret = *(uint16_t *)(dev->ems[vpage].addr + (addr - map->base));
return(ret);
}
#if NOT_USED
static void neat_writeems(uint32_t addr, uint8_t val)
/* Write one byte to paged RAM. */
static void
ems_writeb(uint32_t addr, uint8_t val, void *priv)
{
ram[(neat_emspage[(addr >> 14) & 3] << 14) + (addr & 0x3FFF)] = val;
mem_mapping_t *map = (mem_mapping_t *)priv;
neat_t *dev = (neat_t *)map->dev;
int vpage;
/* Get the viewport page number. */
vpage = ((addr & 0xffff) / EMS_PGSIZE);
/* Write the data. */
*(uint8_t *)(dev->ems[vpage].addr + (addr - map->base)) = val;
}
static uint8_t neat_readems(uint32_t addr)
/* Write one word to paged RAM. */
static void
ems_writew(uint32_t addr, uint16_t val, void *priv)
{
return ram[(neat_emspage[(addr >> 14) & 3] << 14) + (addr & 0x3FFF)];
mem_mapping_t *map = (mem_mapping_t *)priv;
neat_t *dev = (neat_t *)map->dev;
int vpage;
/* Get the viewport page number. */
vpage = ((addr & 0xffff) / EMS_PGSIZE);
/* Write the data. */
*(uint16_t *)(dev->ems[vpage].addr + (addr - map->base)) = val;
}
/* Re-calculate the active-page physical address. */
static void
ems_recalc(neat_t *dev, emspage_t *ems)
{
if (ems->page >= dev->ems_pages) {
/* That page does not exist. */
ems->enabled = 0;
}
/* Pre-calculate the page address in EMS RAM. */
ems->addr = ram + ems->start + (ems->page * EMS_PGSIZE);
if (ems->enabled) {
/* Update the EMS RAM address for this page. */
mem_mapping_set_exec(&ems->mapping, ems->addr);
/* Enable this page. */
mem_mapping_enable(&ems->mapping);
#if NEAT_DEBUG > 1
pclog("NEAT EMS: page %d set to %08lx, %sabled)\n",
ems->page, ems->addr-ram, ems->enabled?"en":"dis");
#endif
} else {
/* Disable this page. */
mem_mapping_disable(&ems->mapping);
}
}
static void
ems_write(uint16_t port, uint8_t val, void *priv)
{
neat_t *dev = (neat_t *)priv;
emspage_t *ems;
int vpage;
#if NEAT_DEBUG > 1
pclog("NEAT: ems_write(%04x, %02x)\n", port, val);
#endif
/* Get the viewport page number. */
vpage = (port / EMS_PGSIZE);
ems = &dev->ems[vpage];
static void neat_init(void)
switch(port & 0x000f) {
case 0x0008:
case 0x0009:
ems->enabled = !!(val & 0x80);
ems->page &= 0x0180; /* clear lower bits */
ems->page |= (val & 0x7f); /* add new bits */
ems_recalc(dev, ems);
break;
}
}
static uint8_t
ems_read(uint16_t port, void *priv)
{
io_sethandler(0x0022, 0x0002, neat_read, NULL, NULL, neat_write, NULL, NULL, NULL);
io_sethandler(0x0208, 0x0002, neat_read, NULL, NULL, neat_write, NULL, NULL, NULL);
io_sethandler(0x4208, 0x0002, neat_read, NULL, NULL, neat_write, NULL, NULL, NULL);
io_sethandler(0x8208, 0x0002, neat_read, NULL, NULL, neat_write, NULL, NULL, NULL);
io_sethandler(0xc208, 0x0002, neat_read, NULL, NULL, neat_write, NULL, NULL, NULL);
neat_t *dev = (neat_t *)priv;
uint8_t ret = 0xff;
int vpage;
/* Get the viewport page number. */
vpage = (port / EMS_PGSIZE);
switch(port & 0x000f) {
case 0x0008: /* page number register */
ret = dev->ems[vpage].page & 0x7f;
if (dev->ems[vpage].enabled)
ret |= 0x80;
break;
}
#if NEAT_DEBUG > 1
pclog("NEAT: ems_read(%04x) = %02x\n", port, ret);
#endif
return(ret);
}
/* Initialize the EMS module. */
static void
ems_init(neat_t *dev, int en)
{
int i;
/* Remove if needed. */
if (! en) {
if (dev->ems_base > 0) for (i = 0; i < EMS_MAXPAGE; i++) {
/* Disable for now. */
mem_mapping_disable(&dev->ems[i].mapping);
/* Remove I/O handler. */
io_removehandler(dev->ems_base + (i * EMS_PGSIZE), 2,
ems_read,NULL,NULL, ems_write,NULL,NULL, dev);
}
pclog("NEAT: EMS disabled\n");
return;
}
/* Get configured I/O address. */
i = (dev->regs[REG_RB9] & RB9_BASE) >> RB9_BASE_SH;
dev->ems_base = 0x0208 + (0x10 * i);
/* Get configured frame address. */
i = (dev->regs[REG_RB9] & RB9_FRAME) >> RB9_FRAME_SH;
dev->ems_frame = 0xC0000 + (EMS_PGSIZE * i);
/*
* For each supported page (we can have a maximum of 4),
* create, initialize and disable the mappings, and set
* up the I/O control handler.
*/
for (i = 0; i < EMS_MAXPAGE; i++) {
/* Create and initialize a page mapping. */
mem_mapping_add(&dev->ems[i].mapping,
dev->ems_frame + (EMS_PGSIZE*i), EMS_PGSIZE,
ems_readb, ems_readw, NULL,
ems_writeb, ems_writew, NULL,
ram, MEM_MAPPING_EXTERNAL,
&dev->ems[i].mapping);
mem_mapping_set_dev(&dev->ems[i].mapping, dev);
/* Disable for now. */
mem_mapping_disable(&dev->ems[i].mapping);
/* Set up an I/O port handler. */
io_sethandler(dev->ems_base + (i * EMS_PGSIZE), 2,
ems_read,NULL,NULL, ems_write,NULL,NULL, dev);
/*
* TODO: update the 'high_mem' mapping to reflect that we now
* have NN MB less extended memory available..
*/
}
pclog("NEAT: EMS enabled, I/O=%04xH, Frame=%05XH\n",
dev->ems_base, dev->ems_frame);
}
static void
neat_write(uint16_t port, uint8_t val, void *priv)
{
neat_t *dev = (neat_t *)priv;
uint8_t xval, *reg;
int i;
#if NEAT_DEBUG > 2
pclog("NEAT: write(%04x, %02x)\n", port, val);
#endif
switch (port) {
case 0x22:
dev->indx = val;
break;
case 0x23:
reg = &dev->regs[dev->indx];
xval = *reg ^ val;
switch (dev->indx) {
case REG_RA0:
val &= RA0_MASK;
*reg = (*reg & ~RA0_MASK) | val | \
(RA0_REV_ID << RA0_REV_SH);
#if NEAT_DEBUG > 1
pclog("NEAT: RA0=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RA1:
val &= RA1_MASK;
*reg = (*reg & ~RA1_MASK) | val;
#if NEAT_DEBUG > 1
pclog("NEAT: RA1=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RA2:
val &= RA2_MASK;
*reg = (*reg & ~RA2_MASK) | val;
#if NEAT_DEBUG > 1
pclog("NEAT: RA2=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RB0:
val &= RB0_MASK;
*reg = (*reg & ~RB0_MASK) | val | \
(RB0_REV_ID << RB0_REV_SH);
#if NEAT_DEBUG > 1
pclog("NEAT: RB0=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RB1:
val &= RB1_MASK;
*reg = (*reg & ~RB1_MASK) | val;
#if NEAT_DEBUG > 1
pclog("NEAT: RB1=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RB2:
val &= RB2_MASK;
*reg = (*reg & ~RB2_MASK) | val;
#if NEAT_DEBUG > 1
pclog("NEAT: RB2=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RB3:
val &= RB3_MASK;
*reg = (*reg & ~RB3_MASK) | val;
#if NEAT_DEBUG > 1
pclog("NEAT: RB3=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RB4:
val &= RB4_MASK;
*reg = (*reg & ~RB4_MASK) | val;
#if NEAT_DEBUG > 1
pclog("NEAT: RB4=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RB5:
val &= RB5_MASK;
*reg = (*reg & ~RB5_MASK) | val;
#if NEAT_DEBUG > 1
pclog("NEAT: RB5=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RB6:
val &= RB6_MASK;
*reg = (*reg & ~RB6_MASK) | val;
#if NEAT_DEBUG > 1
pclog("NEAT: RB6=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RB7:
val &= RB7_MASK;
*reg = (*reg & ~RB7_MASK) | val;
#if NEAT_DEBUG > 1
pclog("NEAT: RB7=%02x(%02x)\n", val, *reg);
#endif
if (val & RB7_EMSEN)
ems_init(dev, 1);
else if (xval & RB7_EMSEN)
ems_init(dev, 0);
if (xval & RB7_UMAREL) {
if (val & RB7_UMAREL)
mem_remap_top(384);
else
mem_remap_top(0);
}
break;
case REG_RB8:
val &= RB8_MASK;
*reg = (*reg & ~RB8_MASK) | val;
#if NEAT_DEBUG > 1
pclog("NEAT: RB8=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RB9:
val &= RB9_MASK;
*reg = (*reg & ~RB9_MASK) | val;
#if NEAT_DEBUG > 1
pclog("NEAT: RB9=%02x(%02x)\n", val, *reg);
#endif
if (dev->regs[REG_RB7] & RB7_EMSEN) {
ems_init(dev, 0);
ems_init(dev, 1);
}
break;
case REG_RB10:
val &= RB10_MASK;
*reg = (*reg & ~RB10_MASK) | val;
#if NEAT_DEBUG > 1
pclog("NEAT: RB10=%02x(%02x)\n", val, *reg);
#endif
dev->ems[3].start = ((val & RB10_P3EXT) >> RB10_P3EXT_SH) << 21;
dev->ems[2].start = ((val & RB10_P2EXT) >> RB10_P2EXT_SH) << 21;
dev->ems[1].start = ((val & RB10_P1EXT) >> RB10_P1EXT_SH) << 21;
dev->ems[0].start = ((val & RB10_P0EXT) >> RB10_P0EXT_SH) << 21;
for (i = 0; i < EMS_MAXPAGE; i++)
ems_recalc(dev, &dev->ems[i]);
break;
case REG_RB11:
val &= RB11_MASK;
*reg = (*reg & ~RB11_MASK) | val;
#if NEAT_DEBUG > 1
pclog("NEAT: RB11=%02x(%02x)\n", val, *reg);
#endif
i = (val & RB11_EMSLEN) >> RB11_EMSLEN_SH;
switch(i) {
case 0: /* "less than 2MB" */
dev->ems_size = 512;
break;
case 1: /* 1 MB */
case 2: /* 2 MB */
case 3: /* 3 MB */
case 4: /* 4 MB */
case 5: /* 5 MB */
case 6: /* 6 MB */
case 7: /* 7 MB */
dev->ems_size = i << 10;
break;
}
dev->ems_pages = (dev->ems_size << 10) / EMS_PGSIZE;
if (dev->regs[REG_RB7] & RB7_EMSEN)
pclog("NEAT: EMS %iKB (%i pages)\n",
dev->ems_size, dev->ems_pages);
break;
default:
pclog("NEAT: inv write to reg %02x (%02x)\n",
dev->indx, val);
break;
}
break;
}
}
static uint8_t
neat_read(uint16_t port, void *priv)
{
neat_t *dev = (neat_t *)priv;
uint8_t ret = 0xff;
switch (port) {
case 0x22:
ret = dev->indx;
break;
case 0x23:
ret = dev->regs[dev->indx];
break;
default:
break;
}
#if NEAT_DEBUG > 2
pclog("NEAT: read(%04x) = %02x\n", port, ret);
#endif
return(ret);
}
static void
neat_init(void)
{
neat_t *dev;
int i;
/* Create an instance. */
dev = (neat_t *)malloc(sizeof(neat_t));
memset(dev, 0x00, sizeof(neat_t));
/* Initialize some of the registers to specific defaults. */
for (i = REG_RA0; i <= REG_RB11; i++) {
dev->indx = i;
neat_write(0x0023, 0x00, dev);
}
/*
* Based on the value of mem_size, we have to set up
* a proper DRAM configuration (so that EMS works.)
*
* TODO: We might also want to set 'valid' waitstate
* bits, based on our cpu speed.
*/
i = 0;
switch(mem_size) {
case 512: /* 512KB */
/* 256K, 0, 0, 0 */
dev->regs[REG_RB6] &= ~RB6_BANKS; /* one bank */
dev->regs[REG_RB6] |= (RTYPE_256K<<RTYPE_SH); /* 256K */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_NONE<<RTYPE_SH); /* NONE */
i = 2;
break;
case 640: /* 640KB */
/* 256K, 64K, 0, 0 */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_MIXED<<RTYPE_SH); /* mixed */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_NONE<<RTYPE_SH); /* NONE */
i = 4;
break;
case 1024: /* 1MB */
/* 256K, 256K, 0, 0 */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_256K<<RTYPE_SH); /* 256K */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_NONE<<RTYPE_SH); /* NONE */
i = 5;
break;
case 1536: /* 1.5MB */
/* 256K, 256K, 256K, 0 */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_256K<<RTYPE_SH); /* 256K */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_256K<<RTYPE_SH); /* 256K */
i = 7;
break;
case 1664: /* 1.64MB */
/* 256K, 64K, 256K, 256K */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_MIXED<<RTYPE_SH); /* mixed */
dev->regs[REG_RB8] |= RB8_BANKS; /* two banks */
dev->regs[REG_RB8] |= (RTYPE_256K<<RTYPE_SH); /* 256K */
i = 10;
break;
case 2048: /* 2MB */
#if 1
/* 256K, 256K, 256K, 256K */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_256K<<RTYPE_SH); /* 256K */
dev->regs[REG_RB8] |= RB8_BANKS; /* two banks */
dev->regs[REG_RB8] |= (RTYPE_256K<<RTYPE_SH); /* 256K */
dev->regs[REG_RB8] |= RB8_4WAY; /* 4way intl */
i = 11;
#else
/* 1M, 0, 0, 0 */
dev->regs[REG_RB6] &= ~RB6_BANKS; /* one bank */
dev->regs[REG_RB6] |= (RTYPE_1M<<RTYPE_SH); /* 1M */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_NONE<<RTYPE_SH); /* NONE */
i = 3;
#endif
break;
case 3072: /* 3MB */
/* 256K, 256K, 1M, 0 */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_256K<<RTYPE_SH); /* 256K */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_1M<<RTYPE_SH); /* 1M */
i = 8;
break;
case 4096: /* 4MB */
/* 1M, 1M, 0, 0 */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_1M<<RTYPE_SH); /* 1M */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_NONE<<RTYPE_SH); /* NONE */
i = 6;
break;
case 4224: /* 4.64MB */
/* 256K, 64K, 1M, 1M */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_MIXED<<RTYPE_SH); /* mixed */
dev->regs[REG_RB8] |= RB8_BANKS; /* two banks */
dev->regs[REG_RB8] |= (RTYPE_1M<<RTYPE_SH); /* 1M */
i = 12;
break;
case 5120: /* 5MB */
/* 256K, 256K, 1M, 1M */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_256K<<RTYPE_SH); /* 256K */
dev->regs[REG_RB8] |= RB8_BANKS; /* two banks */
dev->regs[REG_RB8] |= (RTYPE_1M<<RTYPE_SH); /* 1M */
i = 13;
break;
case 6144: /* 6MB */
/* 1M, 1M, 1M, 0 */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_1M<<RTYPE_SH); /* 1M */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_1M<<RTYPE_SH); /* 1M */
i = 9;
break;
case 8192: /* 8MB */
/* 1M, 1M, 1M, 1M */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_1M<<RTYPE_SH); /* 1M */
dev->regs[REG_RB8] |= RB8_BANKS; /* two banks */
dev->regs[REG_RB8] |= (RTYPE_1M<<RTYPE_SH); /* 1M */
dev->regs[REG_RB8] |= RB8_4WAY; /* 4way intl */
i = 14;
break;
default:
pclog("NEAT: **INVALID DRAM SIZE %iKB !**\n", mem_size);
}
if (i > 0)
pclog("NEAT: using DRAM mode #%i (mem=%iKB)\n", i, mem_size);
/* Set up an I/O handler for the chipset. */
io_sethandler(0x0022, 2,
neat_read,NULL,NULL, neat_write,NULL,NULL, dev);
}
@@ -91,9 +853,10 @@ void
machine_at_neat_init(const machine_t *model)
{
machine_at_init(model);
device_add(&fdc_at_device);
neat_init();
neat_init();
device_add(&fdc_at_device);
}
@@ -102,8 +865,9 @@ machine_at_neat_ami_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&keyboard_at_ami_device);
device_add(&fdc_at_device);
neat_init();
neat_init();
device_add(&keyboard_at_ami_device);
device_add(&fdc_at_device);
}

6
src/machine/m_at_scat.c
View File

@@ -10,7 +10,7 @@
*
* Re-worked version based on the 82C235 datasheet and errata.
*
* Version: @(#)m_at_scat.c 1.0.15 2018/04/29
* Version: @(#)m_at_scat.c 1.0.16 2018/09/02
*
* Authors: Original by GreatPsycho for PCem.
* Fred N. van Kempen, <decwiz@yahoo.com>
@@ -1259,7 +1259,6 @@ scat_init()
scat_port_92 = 0;
mem_mapping_disable(&ram_low_mapping);
mem_mapping_disable(&ram_mid_mapping);
mem_mapping_disable(&ram_high_mapping);
for (i = 0; i < 4; i++)
mem_mapping_disable(&bios_mapping[i]);
@@ -1282,8 +1281,6 @@ scat_init()
mem_mapping_add(&scat_ems_mapping[i], (i + (i >= 24 ? 28 : 16)) << 14, 0x04000, mem_read_scatb, mem_read_scatw, mem_read_scatl, mem_write_scatb, mem_write_scatw, mem_write_scatl, ram + ((i + (i >= 24 ? 28 : 16)) << 14), 0, &scat_stat[i]);
}
for(i=4;i<10;i++) isram[i] = 0;
for (i = (scat_regs[SCAT_VERSION] < 4 ? 0 : 8); i < 16; i++) {
mem_mapping_add(&scat_high_mapping[i], (i << 14) + 0xFC0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + ((i << 14) & biosmask), 0, NULL);
mem_mapping_enable(&scat_high_mapping[i]);
@@ -1333,7 +1330,6 @@ scatsx_init()
scat_port_92 = 0;
mem_mapping_disable(&ram_low_mapping);
mem_mapping_disable(&ram_mid_mapping);
mem_mapping_disable(&ram_high_mapping);
for (i = 0; i < 4; i++)
mem_mapping_disable(&bios_mapping[i]);

4
src/machine/m_ps1.c
View File

@@ -28,7 +28,7 @@
* boot. Sometimes, they do, and then it shows an "Incorrect
* DOS" error message?? --FvK
*
* Version: @(#)m_ps1.c 1.0.9 2018/04/26
* Version: @(#)m_ps1.c 1.0.10 2018/09/02
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -512,7 +512,7 @@ ps1_common_init(const machine_t *model)
{
machine_common_init(model);
mem_remap_top_384k();
mem_remap_top(384);
pit_set_out_func(&pit, 1, pit_refresh_timer_at);

45
src/machine/m_ps2_mca.c
View File

@@ -1,3 +1,41 @@
/*
* VARCem Virtual ARchaeological Computer EMulator.
* An emulator of (mostly) x86-based PC systems and devices,
* using the ISA,EISA,VLB,MCA and PCI system buses, roughly
* spanning the era between 1981 and 1995.
*
* This file is part of the VARCem Project.
*
* Implementation of MCA-based PS/2 machines.
*
* Version: @(#)m_ps2_mca.c 1.0.0 2018/09/02
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <tommowalker@tommowalker.co.uk>
*
* Copyright 2017,2018 Fred N. van Kempen.
* Copyright 2016-2018 Miran Grca.
* Copyright 2008-2018 Sarah Walker.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the:
*
* Free Software Foundation, Inc.
* 59 Temple Place - Suite 330
* Boston, MA 02111-1307
* USA.
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
@@ -830,7 +868,7 @@ static void ps2_mca_board_model_50_init()
{
ps2_mca_board_common_init();
mem_remap_top_384k();
mem_remap_top(384);
mca_init(4);
ps2.planar_read = model_50_read;
@@ -864,7 +902,7 @@ static void ps2_mca_board_model_55sx_init()
NULL);
mem_remap_top_256k();
mem_remap_top(256);
ps2.option[3] = 0x10;
memset(ps2.memory_bank, 0xf0, 8);
@@ -1019,10 +1057,13 @@ static void mem_encoding_write_cached(uint16_t addr, uint8_t val, void *p)
ps2.pending_cache_miss = 1;
if ((val & 0x21) == 0x01 && (old & 0x21) != 0x01)
ps2_cache_clean();
#if 1
// FIXME: Look into this!!!
if (val & 0x01)
ram_mid_mapping.flags |= MEM_MAPPING_ROM;
else
ram_mid_mapping.flags &= ~MEM_MAPPING_ROM;
#endif
break;
}
ps2_mca_log("mem_encoding_write: addr=%02x val=%02x %04x:%04x %02x %02x\n", addr, val, CS,cpu_state.pc, ps2.mem_regs[1],ps2.mem_regs[2]);

7
src/machine/machine.h
View File

@@ -8,7 +8,7 @@
*
* Handling of the emulated machines.
*
* Version: @(#)machine.h 1.0.26 2018/08/16
* Version: @(#)machine.h 1.0.27 2018/09/02
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -96,14 +96,11 @@ extern void machine_common_init(const machine_t *);
extern void machine_at_common_init(const machine_t *);
extern void machine_at_init(const machine_t *);
extern void machine_at_ibm_init(const machine_t *);
extern void machine_at_ps2_init(const machine_t *);
extern void machine_at_common_ide_init(const machine_t *);
extern void machine_at_ide_init(const machine_t *);
extern void machine_at_ps2_ide_init(const machine_t *);
extern void machine_at_top_remap_init(const machine_t *);
extern void machine_at_ide_top_remap_init(const machine_t *);
extern void machine_at_ibm_init(const machine_t *);
extern void machine_at_t3100e_init(const machine_t *);

58
src/machine/machine_table.c
View File

@@ -11,7 +11,7 @@
* NOTES: OpenAT wip for 286-class machine with open BIOS.
* PS2_M80-486 wip, pending receipt of TRM's for machine.
*
* Version: @(#)machine_table.c 1.0.33 2018/08/16
* Version: @(#)machine_table.c 1.0.35 2018/09/02
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -34,37 +34,37 @@
const machine_t machines[] = {
{ "[8088] AMI XT clone", ROM_AMIXT, "amixt", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, machine_xt_init, NULL },
{ "[8088] Compaq Portable", ROM_PORTABLE, "portable", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VIDEO, 128, 640, 128, 0, machine_xt_compaq_init, NULL },
{ "[8088] DTK XT clone", ROM_DTKXT, "dtk", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, machine_xt_init, NULL },
{ "[8088] IBM PC", ROM_IBMPC, "ibmpc", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 32, 0, machine_xt_init, NULL },
{ "[8088] IBM PCjr", ROM_IBMPCJR, "ibmpcjr", {{"", cpus_pcjr}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO, 128, 640, 128, 0, machine_pcjr_init, pcjr_get_device },
{ "[8088] IBM XT", ROM_IBMXT, "ibmxt", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, machine_xt_init, NULL },
{ "[8088] Generic XT clone", ROM_GENXT, "genxt", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, machine_xt_init, NULL },
{ "[8088] Juko XT clone", ROM_JUKOPC, "jukopc", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, machine_xt_init, NULL },
{ "[8088] Phoenix XT clone", ROM_PXXT, "pxxt", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, machine_xt_init, NULL },
{ "[8088] Schneider EuroPC", ROM_EUROPC, "europc", {{"Siemens",cpus_europc}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_HDC | MACHINE_VIDEO | MACHINE_MOUSE, 512, 640, 128, 15, machine_europc_init, NULL },
{ "[8088] Tandy 1000", ROM_TANDY, "tandy", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA, 128, 640, 128, 0, machine_tandy1k_init, tandy1k_get_device },
{ "[8088] Tandy 1000 HX", ROM_TANDY1000HX, "tandy1000hx", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA, 256, 640, 128, 0, machine_tandy1k_init, tandy1k_hx_get_device },
{ "[8088] Toshiba T1000", ROM_T1000, "t1000", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VIDEO, 512, 1280, 768, 63, machine_xt_t1000_init, t1000_get_device },
{ "[8088] AMI XT clone", ROM_AMIXT, "amixt", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, machine_xt_init, NULL },
{ "[8088] Compaq Portable", ROM_PORTABLE, "portable", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VIDEO, 128, 640, 128, 0, machine_xt_compaq_init, NULL },
{ "[8088] DTK XT clone", ROM_DTKXT, "dtk", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, machine_xt_init, NULL },
{ "[8088] IBM PC", ROM_IBMPC, "ibmpc", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 32, 0, machine_xt_init, NULL },
{ "[8088] IBM PCjr", ROM_IBMPCJR, "ibmpcjr", {{"Intel", cpus_pcjr}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO, 128, 640, 128, 0, machine_pcjr_init, pcjr_get_device },
{ "[8088] IBM XT", ROM_IBMXT, "ibmxt", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, machine_xt_init, NULL },
{ "[8088] Generic XT clone", ROM_GENXT, "genxt", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, machine_xt_init, NULL },
{ "[8088] Juko XT clone", ROM_JUKOPC, "jukopc", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, machine_xt_init, NULL },
{ "[8088] Phoenix XT clone", ROM_PXXT, "pxxt", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 64, 640, 64, 0, machine_xt_init, NULL },
{ "[8088] Schneider EuroPC", ROM_EUROPC, "europc", {{"Siemens", cpus_europc}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_HDC | MACHINE_VIDEO | MACHINE_MOUSE, 512, 640, 128, 15, machine_europc_init, NULL },
{ "[8088] Tandy 1000", ROM_TANDY, "tandy", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA, 128, 640, 128, 0, machine_tandy1k_init, tandy1k_get_device },
{ "[8088] Tandy 1000 HX", ROM_TANDY1000HX, "tandy1000hx", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA, 256, 640, 128, 0, machine_tandy1k_init, tandy1k_hx_get_device },
{ "[8088] Toshiba T1000", ROM_T1000, "t1000", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VIDEO, 512, 1280, 768, 63, machine_xt_t1000_init, t1000_get_device },
#if defined(DEV_BRANCH) && defined(USE_LASERXT)
{ "[8088] VTech Laser Turbo XT", ROM_LTXT, "ltxt", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 512, 512, 256, 0, machine_xt_laserxt_init, NULL },
{ "[8088] VTech Laser Turbo XT", ROM_LTXT, "ltxt", {{"Intel", cpus_8088}, {"", NULL},, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 512, 512, 256, 0, machine_xt_laserxt_init, NULL },
#endif
{ "[8088] Xi8088", ROM_XI8088, "xi8088", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_PS2, 64, 1024, 128, 127, machine_xt_xi8088_init, NULL },
{ "[8088] Xi8088", ROM_XI8088, "xi8088", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_PS2, 64, 1024, 128, 127, machine_xt_xi8088_init, NULL },
{ "[8086] Amstrad PC1512", ROM_PC1512, "pc1512", {{"", cpus_pc1512}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 512, 640, 128, 63, machine_amstrad_init, NULL },
{ "[8086] Amstrad PC1640", ROM_PC1640, "pc1640", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 640, 640, 0, 63, machine_amstrad_init, NULL },
{ "[8086] Amstrad PC2086", ROM_PC2086, "pc2086", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 640, 640, 0, 63, machine_amstrad_init, NULL },
{ "[8086] Amstrad PC3086", ROM_PC3086, "pc3086", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 640, 640, 0, 63, machine_amstrad_init, NULL },
{ "[8086] Amstrad PC20(0)", ROM_PC200, "pc200", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 512, 640, 128, 63, machine_amstrad_init, NULL },
{ "[8086] Olivetti M24", ROM_OLIM24, "olivetti_m24", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 128, 640, 128, 0, machine_olim24_init, NULL },
{ "[8086] Tandy 1000 SL/2", ROM_TANDY1000SL2, "tandy1000sl2", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA, 512, 768, 128, 0, machine_tandy1k_init, NULL },
{ "[8086] Toshiba T1200", ROM_T1200, "t1200", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VIDEO, 1024, 2048,1024, 63, machine_xt_t1200_init, t1200_get_device },
{ "[8086] Amstrad PC1512", ROM_PC1512, "pc1512", {{"Intel", cpus_pc1512}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 512, 640, 128, 63, machine_amstrad_init, NULL },
{ "[8086] Amstrad PC1640", ROM_PC1640, "pc1640", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 640, 640, 0, 63, machine_amstrad_init, NULL },
{ "[8086] Amstrad PC2086", ROM_PC2086, "pc2086", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 640, 640, 0, 63, machine_amstrad_init, NULL },
{ "[8086] Amstrad PC3086", ROM_PC3086, "pc3086", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 640, 640, 0, 63, machine_amstrad_init, NULL },
{ "[8086] Amstrad PC20(0)", ROM_PC200, "pc200", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 512, 640, 128, 63, machine_amstrad_init, NULL },
{ "[8086] Olivetti M24", ROM_OLIM24, "olivetti_m24", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_VIDEO | MACHINE_MOUSE, 128, 640, 128, 0, machine_olim24_init, NULL },
{ "[8086] Tandy 1000 SL/2", ROM_TANDY1000SL2, "tandy1000sl2", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA, 512, 768, 128, 0, machine_tandy1k_init, NULL },
{ "[8086] Toshiba T1200", ROM_T1200, "t1200", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VIDEO, 1024, 2048,1024, 63, machine_xt_t1200_init, t1200_get_device },
#if defined(DEV_BRANCH) && defined(USE_LASERXT)
{ "[8086] VTech Laser XT3", ROM_LXT3, "lxt3", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 256, 512, 256, 0, machine_xt_laserxt_init, NULL },
{ "[8086] VTech Laser XT3", ROM_LXT3, "lxt3", {{"Intel", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA, 256, 512, 256, 0, machine_xt_laserxt_init, NULL },
#endif
{ "[286 ISA] AMI 286 clone", ROM_AMI286, "ami286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_neat_ami_init, NULL },
{ "[286 ISA] AMI 286 clone", ROM_AMI286, "ami286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 512,8192, 128, 127, machine_at_neat_ami_init, NULL },
{ "[286 ISA] Award 286 clone", ROM_AWARD286, "award286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_scat_init, NULL },
{ "[286 ISA] Commodore PC 30 III", ROM_CMDPC30, "cmdpc30", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 640,16384, 128, 127, machine_at_cmdpc_init, NULL },
{ "[286 ISA] Compaq Portable II", ROM_PORTABLEII, "portableii", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 640,16384, 128, 127, machine_at_compaq_init, NULL },
@@ -87,11 +87,11 @@ const machine_t machines[] = {
{ "[286 MCA] IBM PS/2 model 50", ROM_IBMPS2_M50, "ibmps2_m50", {{"", cpus_ps2_m30_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2 | MACHINE_VIDEO, 1, 10, 1, 63, machine_ps2_model_50_init, NULL },
{ "[386SX ISA] AMA-932J", ROM_AMA932J, "ama932j", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO, 512, 8192, 128, 127, machine_at_headland_init, at_ama932j_get_device },
{ "[386SX ISA] AMA-932J", ROM_AMA932J, "ama932j", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO, 512, 8192, 128, 127, machine_at_headland_init, at_ama932j_get_device },
{ "[386SX ISA] AMI 386SX clone", ROM_AMI386SX, "ami386", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512,16384, 128, 127, machine_at_headland_init, NULL },
{ "[386SX ISA] Amstrad MegaPC", ROM_MEGAPC, "megapc", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO | MACHINE_HDC, 1, 16, 1, 127, machine_at_wd76c10_init, NULL },
{ "[386SX ISA] Award 386SX clone", ROM_AWARD386SX_OPTI495, "award386sx", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_opti495_init, NULL },
{ "[386SX ISA] DTK 386SX clone", ROM_DTK386, "dtk386", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512,16384, 128, 127, machine_at_neat_init, NULL },
{ "[386SX ISA] DTK 386SX clone", ROM_DTK386, "dtk386", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512,8192, 128, 127, machine_at_neat_init, NULL },
{ "[386SX ISA] IBM PS/1 model 2121", ROM_IBMPS1_2121, "ibmps1_2121", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 1, 6, 1, 63, machine_ps1_m2121_init, NULL },
{ "[386SX ISA] IBM PS/1 m.2121+ISA", ROM_IBMPS1_2121_ISA, "ibmps1_2121_isa", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 1, 6, 1, 63, machine_ps1_m2121_init, NULL },
{ "[386SX ISA] KMX-C-02", ROM_KMXC02, "kmxc02", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT, 512,16384, 512, 127, machine_at_scatsx_init, NULL },
@@ -101,7 +101,7 @@ const machine_t machines[] = {
{ "[386DX ISA] AMI 386DX clone", ROM_AMI386DX_OPTI495, "ami386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_opti495_ami_init, NULL },
{ "[386DX ISA] Amstrad MegaPC 386DX", ROM_MEGAPCDX, "megapcdx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 1, 32, 1, 127, machine_at_wd76c10_init, NULL },
{ "[386DX ISA] Award 386DX clone", ROM_AWARD386DX_OPTI495, "award386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_opti495_init, NULL },
{ "[386DX ISA] MR 386DX clone", ROM_MR386DX_OPTI495, "mr386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_opti495_ami_init, NULL },
{ "[386DX ISA] MR 386DX clone", ROM_MR386DX_OPTI495, "mr386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_opti495_ami_init, NULL },
#if defined(DEV_BRANCH) && defined(USE_PORTABLE3)
{ "[386DX ISA] Compaq Portable III (386)", ROM_PORTABLEIII386, "portableiii386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 1, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO, 1, 14, 1, 127, machine_at_compaq_init, NULL },
#endif