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Upgrade to softfloat3e.

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This should solve licensing problems as well.
This commit is contained in:
TC1995
2024-06-09 23:08:46 +02:00
parent 4b77ef6823
commit 0f29bcddf1
271 changed files with 25882 additions and 10441 deletions
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128
src/cpu/x87.h
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@@ -60,89 +60,80 @@ void x87_settag(uint16_t new_tag);
void codegen_set_rounding_mode(int mode);
/* Status Word */
#define FPU_SW_Backward (0x8000) /* backward compatibility */
#define FPU_SW_C3 (0x4000) /* condition bit 3 */
#define FPU_SW_Top (0x3800) /* top of stack */
#define FPU_SW_C2 (0x0400) /* condition bit 2 */
#define FPU_SW_C1 (0x0200) /* condition bit 1 */
#define FPU_SW_C0 (0x0100) /* condition bit 0 */
#define FPU_SW_Summary (0x0080) /* exception summary */
#define FPU_SW_Stack_Fault (0x0040) /* stack fault */
#define FPU_SW_Precision (0x0020) /* loss of precision */
#define FPU_SW_Underflow (0x0010) /* underflow */
#define FPU_SW_Overflow (0x0008) /* overflow */
#define FPU_SW_Zero_Div (0x0004) /* divide by zero */
#define FPU_SW_Denormal_Op (0x0002) /* denormalized operand */
#define FPU_SW_Invalid (0x0001) /* invalid operation */
#define FPU_SW_Backward (0x8000) /* backward compatibility */
#define FPU_SW_C3 (0x4000) /* condition bit 3 */
#define FPU_SW_Top (0x3800) /* top of stack */
#define FPU_SW_C2 (0x0400) /* condition bit 2 */
#define FPU_SW_C1 (0x0200) /* condition bit 1 */
#define FPU_SW_C0 (0x0100) /* condition bit 0 */
#define FPU_SW_Summary (0x0080) /* exception summary */
#define FPU_SW_Stack_Fault (0x0040) /* stack fault */
#define FPU_SW_Precision (0x0020) /* loss of precision */
#define FPU_SW_Underflow (0x0010) /* underflow */
#define FPU_SW_Overflow (0x0008) /* overflow */
#define FPU_SW_Zero_Div (0x0004) /* divide by zero */
#define FPU_SW_Denormal_Op (0x0002) /* denormalized operand */
#define FPU_SW_Invalid (0x0001) /* invalid operation */
#define C0 (1 << 8)
#define C1 (1 << 9)
#define C2 (1 << 10)
#define C3 (1 << 14)
#define FPU_SW_CC (FPU_SW_C0|FPU_SW_C1|FPU_SW_C2|FPU_SW_C3)
#define FPU_SW_CC (C0 | C1 | C2 | C3)
#define FPU_SW_Exceptions_Mask (0x027f) /* status word exceptions bit mask */
#define FPU_SW_Exceptions_Mask (0x027f) /* status word exceptions bit mask */
/* Exception flags: */
#define FPU_EX_Precision (0x0020) /* loss of precision */
#define FPU_EX_Underflow (0x0010) /* underflow */
#define FPU_EX_Overflow (0x0008) /* overflow */
#define FPU_EX_Zero_Div (0x0004) /* divide by zero */
#define FPU_EX_Denormal (0x0002) /* denormalized operand */
#define FPU_EX_Invalid (0x0001) /* invalid operation */
#define FPU_EX_Precision (0x0020) /* loss of precision */
#define FPU_EX_Underflow (0x0010) /* underflow */
#define FPU_EX_Overflow (0x0008) /* overflow */
#define FPU_EX_Zero_Div (0x0004) /* divide by zero */
#define FPU_EX_Denormal (0x0002) /* denormalized operand */
#define FPU_EX_Invalid (0x0001) /* invalid operation */
/* Special exceptions: */
#define FPU_EX_Stack_Overflow (0x0041 | C1) /* stack overflow */
#define FPU_EX_Stack_Underflow (0x0041) /* stack underflow */
#define FPU_EX_Stack_Overflow (0x0041|FPU_SW_C1) /* stack overflow */
#define FPU_EX_Stack_Underflow (0x0041) /* stack underflow */
/* precision control */
#define FPU_EX_Precision_Lost_Up (EX_Precision | C1)
#define FPU_EX_Precision_Lost_Dn (EX_Precision)
#define FPU_EX_Precision_Lost_Up (EX_Precision | SW_C1)
#define FPU_EX_Precision_Lost_Dn (EX_Precision)
#define setcc(cc) \
fpu_state.swd = (fpu_state.swd & ~(FPU_SW_CC)) | ((cc) &FPU_SW_CC)
#define setcc(cc) \
fpu_state.swd = (fpu_state.swd & ~(FPU_SW_CC)) | ((cc) & FPU_SW_CC)
#define clear_C1() \
{ \
fpu_state.swd &= ~C1; \
}
#define clear_C2() \
{ \
fpu_state.swd &= ~C2; \
}
#define clear_C1() { fpu_state.swd &= ~FPU_SW_C1; }
#define clear_C2() { fpu_state.swd &= ~FPU_SW_C2; }
/* ************ */
/* Control Word */
/* ************ */
#define FPU_CW_Inf (0x1000) /* infinity control, legacy */
#define FPU_CW_Reserved_Bits (0xe0c0) /* reserved bits */
#define FPU_CW_RC (0x0C00) /* rounding control */
#define FPU_CW_PC (0x0300) /* precision control */
#define FPU_CW_Inf (0x1000) /* infinity control, legacy */
#define FPU_RC_RND (0x0000) /* rounding control */
#define FPU_RC_DOWN (0x0400)
#define FPU_RC_UP (0x0800)
#define FPU_RC_CHOP (0x0C00)
#define FPU_CW_RC (0x0C00) /* rounding control */
#define FPU_CW_PC (0x0300) /* precision control */
#define FPU_CW_Precision (0x0020) /* loss of precision mask */
#define FPU_CW_Underflow (0x0010) /* underflow mask */
#define FPU_CW_Overflow (0x0008) /* overflow mask */
#define FPU_CW_Zero_Div (0x0004) /* divide by zero mask */
#define FPU_CW_Denormal (0x0002) /* denormalized operand mask */
#define FPU_CW_Invalid (0x0001) /* invalid operation mask */
#define FPU_RC_RND (0x0000) /* rounding control */
#define FPU_RC_DOWN (0x0400)
#define FPU_RC_UP (0x0800)
#define FPU_RC_CHOP (0x0C00)
#define FPU_CW_Exceptions_Mask (0x003f) /* all masks */
#define FPU_CW_Precision (0x0020) /* loss of precision mask */
#define FPU_CW_Underflow (0x0010) /* underflow mask */
#define FPU_CW_Overflow (0x0008) /* overflow mask */
#define FPU_CW_Zero_Div (0x0004) /* divide by zero mask */
#define FPU_CW_Denormal (0x0002) /* denormalized operand mask */
#define FPU_CW_Invalid (0x0001) /* invalid operation mask */
#define FPU_CW_Exceptions_Mask (0x003f) /* all masks */
/* Precision control bits affect only the following:
ADD, SUB(R), MUL, DIV(R), and SQRT */
#define FPU_PR_32_BITS (0x000)
#define FPU_PR_RESERVED_BITS (0x100)
#define FPU_PR_64_BITS (0x200)
#define FPU_PR_80_BITS (0x300)
#define FPU_PR_32_BITS (0x000)
#define FPU_PR_RESERVED_BITS (0x100)
#define FPU_PR_64_BITS (0x200)
#define FPU_PR_80_BITS (0x300)
#include "softfloat/softfloatx80.h"
#include "softfloat3e/softfloat.h"
static __inline int
is_IA_masked(void)
@@ -150,15 +141,15 @@ is_IA_masked(void)
return (fpu_state.cwd & FPU_CW_Invalid);
}
struct float_status_t i387cw_to_softfloat_status_word(uint16_t control_word);
struct softfloat_status_t i387cw_to_softfloat_status_word(uint16_t control_word);
uint16_t FPU_exception(uint32_t fetchdat, uint16_t exceptions, int store);
int FPU_status_word_flags_fpu_compare(int float_relation);
void FPU_write_eflags_fpu_compare(int float_relation);
void FPU_stack_overflow(uint32_t fetchdat);
void FPU_stack_underflow(uint32_t fetchdat, int stnr, int pop_stack);
int FPU_handle_NaN32(floatx80 a, float32 b, floatx80 *r, struct float_status_t *status);
int FPU_handle_NaN64(floatx80 a, float64 b, floatx80 *r, struct float_status_t *status);
int FPU_tagof(const floatx80 reg);
int FPU_handle_NaN32(extFloat80_t a, float32 b, extFloat80_t *r, struct softfloat_status_t *status);
int FPU_handle_NaN64(extFloat80_t a, float64 b, extFloat80_t *r, struct softfloat_status_t *status);
int FPU_tagof(const extFloat80_t reg);
uint8_t pack_FPU_TW(uint16_t twd);
uint16_t unpack_FPU_TW(uint16_t tag_byte);
@@ -207,11 +198,11 @@ FPU_push(void)
static __inline void
FPU_pop(void)
{
fpu_state.tag |= 3 << (fpu_state.tos * 2);
fpu_state.tag |= (3 << (fpu_state.tos * 2));
fpu_state.tos = (fpu_state.tos + 1) & 7;
}
static __inline floatx80
static __inline extFloat80_t
FPU_read_regi(int stnr)
{
return fpu_state.st_space[(stnr + fpu_state.tos) & 7];
@@ -221,14 +212,14 @@ FPU_read_regi(int stnr)
// instructions like FNSAVE, and they update tag word to its
// real value anyway
static __inline void
FPU_save_regi(floatx80 reg, int stnr)
FPU_save_regi(extFloat80_t reg, int stnr)
{
fpu_state.st_space[(stnr + fpu_state.tos) & 7] = reg;
FPU_settagi_valid(stnr);
}
static __inline void
FPU_save_regi_tag(floatx80 reg, int tag, int stnr)
FPU_save_regi_tag(extFloat80_t reg, int tag, int stnr)
{
fpu_state.st_space[(stnr + fpu_state.tos) & 7] = reg;
FPU_settagi(tag, stnr);
@@ -237,6 +228,7 @@ FPU_save_regi_tag(floatx80 reg, int tag, int stnr)
#define FPU_check_pending_exceptions() \
do { \
if (fpu_state.swd & FPU_SW_Summary) { \
pclog("SW Summary.\n"); \
if (cr0 & 0x20) { \
x86_int(16); \
return 1; \