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Another round of sonarlint work

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This commit is contained in:
Jasmine Iwanek
2023-06-28 13:46:28 -04:00
parent b750471e5c
commit 1116aadb6f
135 changed files with 2425 additions and 1355 deletions
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16
src/sio/sio_82091aa.c
View File

@@ -35,9 +35,10 @@
#include <86box/fdc.h>
#include <86box/sio.h>
typedef struct {
uint8_t cur_reg, has_ide,
regs[81];
typedef struct i82091aa_t {
uint8_t cur_reg;
uint8_t has_ide;
uint8_t regs[81];
uint16_t base_address;
fdc_t *fdc;
serial_t *uart[2];
@@ -71,6 +72,9 @@ lpt1_handler(i82091aa_t *dev)
case 3:
lpt_port = 0x000;
break;
default:
break;
}
if ((dev->regs[0x20] & 0x01) && lpt_port)
@@ -112,6 +116,9 @@ serial_handler(i82091aa_t *dev, int uart)
case 0x07:
uart_port = COM3_ADDR;
break;
default:
break;
}
if (dev->regs[reg] & 0x01)
@@ -193,6 +200,9 @@ i82091aa_write(uint16_t port, uint8_t val, void *priv)
if (dev->has_ide && (valxor & 0x03))
ide_handler(dev);
break;
default:
break;
}
}

14
src/sio/sio_acc3221.c
View File

@@ -31,6 +31,7 @@
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
#include <86box/plat_unused.h>
typedef struct acc3221_t {
int reg_idx;
@@ -344,9 +345,9 @@ acc3221_serial2_handler(acc3221_t *dev)
}
static void
acc3221_write(uint16_t addr, uint8_t val, void *p)
acc3221_write(uint16_t addr, uint8_t val, void *priv)
{
acc3221_t *dev = (acc3221_t *) p;
acc3221_t *dev = (acc3221_t *) priv;
uint8_t old;
if (!(addr & 1))
@@ -405,14 +406,17 @@ acc3221_write(uint16_t addr, uint8_t val, void *p)
ide_pri_enable();
}
break;
default:
break;
}
}
}
static uint8_t
acc3221_read(uint16_t addr, void *p)
acc3221_read(uint16_t addr, void *priv)
{
acc3221_t *dev = (acc3221_t *) p;
acc3221_t *dev = (acc3221_t *) priv;
if (!(addr & 1))
return dev->reg_idx;
@@ -448,7 +452,7 @@ acc3221_close(void *priv)
}
static void *
acc3221_init(const device_t *info)
acc3221_init(UNUSED(const device_t *info))
{
acc3221_t *dev = (acc3221_t *) malloc(sizeof(acc3221_t));
memset(dev, 0, sizeof(acc3221_t));

43
src/sio/sio_ali5123.c
View File

@@ -37,13 +37,14 @@
#define AB_RST 0x80
typedef struct {
uint8_t chip_id, is_apm,
tries,
regs[48],
ld_regs[13][256];
int locked,
cur_reg;
typedef struct ali5123_t {
uint8_t chip_id;
uint8_t is_apm;
uint8_t tries;
uint8_t regs[48];
uint8_t ld_regs[13][256];
int locked;
int cur_reg;
fdc_t *fdc;
serial_t *uart[3];
} ali5123_t;
@@ -125,6 +126,9 @@ ali5123_serial_handler(ali5123_t *dev, int uart)
case 0x05:
serial_set_clock_src(dev->uart[uart], 2000000.0);
break;
default:
break;
}
}
@@ -256,6 +260,10 @@ ali5123_write(uint16_t port, uint8_t val, void *priv)
case 0x07:
if (dev->cur_reg == 0xf0)
val &= 0xbf;
break;
default:
break;
}
dev->ld_regs[cur_ld][dev->cur_reg] = val;
}
@@ -288,6 +296,9 @@ ali5123_write(uint16_t port, uint8_t val, void *priv)
ali5123_serial_handler(dev, 2);
}
break;
default:
break;
}
return;
@@ -332,6 +343,9 @@ ali5123_write(uint16_t port, uint8_t val, void *priv)
if (valxor & 0x08)
fdc_update_drvrate(dev->fdc, 3, (val & 0x08) >> 3);
break;
default:
break;
}
break;
case 3:
@@ -346,6 +360,9 @@ ali5123_write(uint16_t port, uint8_t val, void *priv)
if (valxor)
ali5123_lpt_handler(dev);
break;
default:
break;
}
break;
case 4:
@@ -361,6 +378,9 @@ ali5123_write(uint16_t port, uint8_t val, void *priv)
if (valxor)
ali5123_serial_handler(dev, 0);
break;
default:
break;
}
break;
case 5:
@@ -376,6 +396,9 @@ ali5123_write(uint16_t port, uint8_t val, void *priv)
if (valxor)
ali5123_serial_handler(dev, (dev->regs[0x2d] & 0x20) ? 2 : 1);
break;
default:
break;
}
break;
case 0x0b:
@@ -391,8 +414,14 @@ ali5123_write(uint16_t port, uint8_t val, void *priv)
if (valxor)
ali5123_serial_handler(dev, (dev->regs[0x2d] & 0x20) ? 1 : 2);
break;
default:
break;
}
break;
default:
break;
}
}

5
src/sio/sio_detect.c
View File

@@ -26,8 +26,9 @@
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
#include <86box/plat_unused.h>
typedef struct {
typedef struct sio_detect_t {
uint8_t regs[2];
} sio_detect_t;
@@ -62,7 +63,7 @@ sio_detect_close(void *priv)
}
static void *
sio_detect_init(const device_t *info)
sio_detect_init(UNUSED(const device_t *info))
{
sio_detect_t *dev = (sio_detect_t *) malloc(sizeof(sio_detect_t));
memset(dev, 0, sizeof(sio_detect_t));

12
src/sio/sio_f82c710.c
View File

@@ -151,6 +151,9 @@ f82c606_update_ports(upc_t *dev, int set)
case 0xc0:
uart2_int = COM2_IRQ;
break;
default:
break;
}
switch (dev->regs[8] & 0x30) {
@@ -163,6 +166,9 @@ f82c606_update_ports(upc_t *dev, int set)
case 0x30:
uart2_int = COM1_IRQ;
break;
default:
break;
}
switch (dev->regs[8] & 0x0c) {
@@ -175,6 +181,9 @@ f82c606_update_ports(upc_t *dev, int set)
case 0x0c:
lpt1_int = LPT2_IRQ;
break;
default:
break;
}
switch (dev->regs[8] & 0x03) {
@@ -187,6 +196,9 @@ f82c606_update_ports(upc_t *dev, int set)
case 0x03:
lpt1_int = LPT1_IRQ;
break;
default:
break;
}
if (dev->regs[0] & 1) {

18
src/sio/sio_fdc37c669.c
View File

@@ -32,11 +32,13 @@
#include <86box/fdc.h>
#include <86box/sio.h>
typedef struct {
uint8_t id, tries,
regs[42];
int locked, rw_locked,
cur_reg;
typedef struct fdc37c669_t {
uint8_t id;
uint8_t tries;
uint8_t regs[42];
int locked;
int rw_locked;
int cur_reg;
fdc_t *fdc;
serial_t *uart[2];
} fdc37c669_t;
@@ -62,6 +64,9 @@ make_port(fdc37c669_t *dev, uint8_t reg)
case 0x25:
mask = 0xfe;
break;
default:
break;
}
p = ((uint16_t) (dev->regs[reg] & mask)) << 2;
@@ -217,6 +222,9 @@ fdc37c669_write(uint16_t port, uint8_t val, void *priv)
serial_setup(dev->uart[0], make_port(dev, 0x24), (dev->regs[0x28] & 0xf0) >> 4);
}
break;
default:
break;
}
}

61
src/sio/sio_fdc37c67x.c
View File

@@ -33,19 +33,23 @@
#include <86box/fdc.h>
#include "cpu.h"
#include <86box/sio.h>
#include <86box/plat_unused.h>
#define AB_RST 0x80
typedef struct {
uint8_t chip_id, is_apm,
tries,
gpio_regs[2], auxio_reg,
regs[48],
ld_regs[11][256];
uint16_t gpio_base, /* Set to EA */
auxio_base, sio_base;
int locked,
cur_reg;
typedef struct fdc37c67x_t {
uint8_t chip_id;
uint8_t is_apm;
uint8_t tries;
uint8_t gpio_regs[2];
uint8_t auxio_reg;
uint8_t regs[48];
uint8_t ld_regs[11][256];
uint16_t gpio_base; /* Set to EA */
uint16_t auxio_base;
uint16_t sio_base;
int locked;
int cur_reg;
fdc_t *fdc;
serial_t *uart[2];
} fdc37c67x_t;
@@ -65,7 +69,7 @@ make_port(fdc37c67x_t *dev, uint8_t ld)
}
static uint8_t
fdc37c67x_auxio_read(uint16_t port, void *priv)
fdc37c67x_auxio_read(UNUSED(uint16_t port), void *priv)
{
fdc37c67x_t *dev = (fdc37c67x_t *) priv;
@@ -73,7 +77,7 @@ fdc37c67x_auxio_read(uint16_t port, void *priv)
}
static void
fdc37c67x_auxio_write(uint16_t port, uint8_t val, void *priv)
fdc37c67x_auxio_write(UNUSED(uint16_t port), uint8_t val, void *priv)
{
fdc37c67x_t *dev = (fdc37c67x_t *) priv;
@@ -168,7 +172,7 @@ fdc37c67x_auxio_handler(fdc37c67x_t *dev)
}
static void
fdc37c67x_sio_handler(fdc37c67x_t *dev)
fdc37c67x_sio_handler(UNUSED(fdc37c67x_t *dev))
{
#if 0
if (dev->sio_base) {
@@ -207,6 +211,9 @@ fdc37c67x_gpio_handler(fdc37c67x_t *dev)
case 3:
ld_port = 0xea; /* Default */
break;
default:
break;
}
dev->gpio_base = ld_port;
if (ld_port > 0x0000)
@@ -279,6 +286,9 @@ fdc37c67x_write(uint16_t port, uint8_t val, void *priv)
case 0x02:
case 0x07:
return;
default:
break;
}
dev->ld_regs[dev->regs[7]][dev->cur_reg] = val | keep;
}
@@ -306,6 +316,9 @@ fdc37c67x_write(uint16_t port, uint8_t val, void *priv)
case 0x26:
case 0x27:
fdc37c67x_sio_handler(dev);
default:
break;
}
return;
@@ -359,6 +372,9 @@ fdc37c67x_write(uint16_t port, uint8_t val, void *priv)
if (valxor & 0x18)
fdc_update_drvrate(dev->fdc, 3, (val & 0x18) >> 3);
break;
default:
break;
}
break;
case 3:
@@ -375,6 +391,9 @@ fdc37c67x_write(uint16_t port, uint8_t val, void *priv)
if (dev->cur_reg == 0x70)
fdc37c67x_smi_handler(dev);
break;
default:
break;
}
break;
case 4:
@@ -391,6 +410,9 @@ fdc37c67x_write(uint16_t port, uint8_t val, void *priv)
if (dev->cur_reg == 0x70)
fdc37c67x_smi_handler(dev);
break;
default:
break;
}
break;
case 5:
@@ -407,6 +429,9 @@ fdc37c67x_write(uint16_t port, uint8_t val, void *priv)
if (dev->cur_reg == 0x70)
fdc37c67x_smi_handler(dev);
break;
default:
break;
}
break;
case 8:
@@ -423,8 +448,14 @@ fdc37c67x_write(uint16_t port, uint8_t val, void *priv)
case 0xb5:
fdc37c67x_smi_handler(dev);
break;
default:
break;
}
break;
default:
break;
}
}
@@ -570,7 +601,9 @@ fdc37c67x_init(const device_t *info)
dev->chip_id = info->local & 0xff;
dev->gpio_regs[0] = 0xff;
// dev->gpio_regs[1] = (info->local == 0x0030) ? 0xff : 0xfd;
#if 0
dev->gpio_regs[1] = (info->local == 0x0030) ? 0xff : 0xfd;
#endif
dev->gpio_regs[1] = (dev->chip_id == 0x30) ? 0xff : 0xfd;
fdc37c67x_reset(dev);

27
src/sio/sio_fdc37c6xx.c
View File

@@ -35,12 +35,15 @@
#include <86box/fdc.h>
#include <86box/sio.h>
typedef struct {
uint8_t max_reg, chip_id,
tries, has_ide,
regs[16];
int cur_reg,
com3_addr, com4_addr;
typedef struct fdc37c6xx_t {
uint8_t max_reg;
uint8_t chip_id;
uint8_t tries;
uint8_t has_ide;
uint8_t regs[16];
int cur_reg;
int com3_addr;
int com4_addr;
fdc_t *fdc;
serial_t *uart[2];
} fdc37c6xx_t;
@@ -65,6 +68,9 @@ set_com34_addr(fdc37c6xx_t *dev)
dev->com3_addr = 0x220;
dev->com4_addr = 0x228;
break;
default:
break;
}
}
@@ -92,6 +98,9 @@ set_serial_addr(fdc37c6xx_t *dev, int port)
case 3:
serial_setup(dev->uart[port], dev->com4_addr, COM4_IRQ);
break;
default:
break;
}
}
@@ -115,6 +124,9 @@ lpt1_handler(fdc37c6xx_t *dev)
lpt1_init(LPT2_ADDR);
lpt1_irq(7 /*5*/);
break;
default:
break;
}
}
@@ -206,6 +218,9 @@ fdc37c6xx_write(uint16_t port, uint8_t val, void *priv)
if (valxor & 0x20)
fdc_set_swap(dev->fdc, (dev->regs[5] & 0x20) >> 5);
break;
default:
break;
}
}
} else if ((port == FDC_PRIMARY_ADDR) && (val == 0x55))

80
src/sio/sio_fdc37c93x.c
View File

@@ -35,10 +35,11 @@
#include <86box/apm.h>
#include <86box/acpi.h>
#include <86box/sio.h>
#include <86box/plat_unused.h>
#define AB_RST 0x80
typedef struct {
typedef struct access_bus_t {
uint8_t control;
uint8_t status;
uint8_t own_addr;
@@ -47,16 +48,19 @@ typedef struct {
uint16_t base;
} access_bus_t;
typedef struct {
uint8_t chip_id, is_apm,
tries,
gpio_regs[2], auxio_reg,
regs[48],
ld_regs[11][256];
uint16_t gpio_base, /* Set to EA */
auxio_base, nvr_sec_base;
int locked,
cur_reg;
typedef struct fdc37c93x_t {
uint8_t chip_id;
uint8_t is_apm;
uint8_t tries;
uint8_t gpio_regs[2];
uint8_t auxio_reg;
uint8_t regs[48];
uint8_t ld_regs[11][256];
uint16_t gpio_base; /* Set to EA */
uint16_t auxio_base;
uint16_t nvr_sec_base;
int locked;
int cur_reg;
fdc_t *fdc;
serial_t *uart[2];
access_bus_t *access_bus;
@@ -87,7 +91,7 @@ make_port_sec(fdc37c93x_t *dev, uint8_t ld)
}
static uint8_t
fdc37c93x_auxio_read(uint16_t port, void *priv)
fdc37c93x_auxio_read(UNUSED(uint16_t port), void *priv)
{
fdc37c93x_t *dev = (fdc37c93x_t *) priv;
@@ -95,7 +99,7 @@ fdc37c93x_auxio_read(uint16_t port, void *priv)
}
static void
fdc37c93x_auxio_write(uint16_t port, uint8_t val, void *priv)
fdc37c93x_auxio_write(UNUSED(uint16_t port), uint8_t val, void *priv)
{
fdc37c93x_t *dev = (fdc37c93x_t *) priv;
@@ -239,6 +243,9 @@ fdc37c93x_gpio_handler(fdc37c93x_t *dev)
case 3:
ld_port = 0xea; /* Default */
break;
default:
break;
}
dev->gpio_base = ld_port;
if (ld_port > 0x0000)
@@ -266,6 +273,9 @@ fdc37c93x_access_bus_read(uint16_t port, void *priv)
case 3:
ret = (dev->clock & 0x87);
break;
default:
break;
}
return ret;
@@ -290,6 +300,9 @@ fdc37c93x_access_bus_write(uint16_t port, uint8_t val, void *priv)
dev->clock &= 0x80;
dev->clock |= (val & 0x07);
break;
default:
break;
}
}
@@ -410,6 +423,9 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
if (!dev->is_apm)
return;
break;
default:
break;
}
dev->ld_regs[dev->regs[7]][dev->cur_reg] = val | keep;
}
@@ -436,6 +452,9 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
if ((valxor & 0x40) && (dev->chip_id != 0x02))
fdc37c93x_access_bus_handler(dev);
break;
default:
break;
}
return;
@@ -489,6 +508,9 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
if (valxor & 0x18)
fdc_update_drvrate(dev->fdc, 3, (val & 0x18) >> 3);
break;
default:
break;
}
break;
case 3:
@@ -503,6 +525,9 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
if (valxor)
fdc37c93x_lpt_handler(dev);
break;
default:
break;
}
break;
case 4:
@@ -517,6 +542,9 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
if (valxor)
fdc37c93x_serial_handler(dev, 0);
break;
default:
break;
}
break;
case 5:
@@ -531,6 +559,9 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
if (valxor)
fdc37c93x_serial_handler(dev, 1);
break;
default:
break;
}
break;
case 6:
@@ -554,8 +585,8 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
nvr_lock_set(0xe0, 0x20, !!(dev->ld_regs[6][dev->cur_reg] & 0x08), dev->nvr);
if (dev->ld_regs[6][dev->cur_reg] & 0x80)
switch ((dev->ld_regs[6][dev->cur_reg] >> 4) & 0x07) {
case 0x00:
default:
case 0x00:
nvr_bank_set(0, 0xff, dev->nvr);
nvr_bank_set(1, 1, dev->nvr);
break;
@@ -588,6 +619,9 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
}
}
break;
default:
break;
}
break;
case 8:
@@ -600,6 +634,9 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
if (valxor)
fdc37c93x_auxio_handler(dev);
break;
default:
break;
}
break;
case 9:
@@ -614,6 +651,9 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
if (valxor)
fdc37c93x_access_bus_handler(dev);
break;
default:
break;
}
break;
case 10:
@@ -628,8 +668,14 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
if (valxor)
fdc37c93x_acpi_handler(dev);
break;
default:
break;
}
break;
default:
break;
}
}
@@ -783,7 +829,7 @@ access_bus_close(void *priv)
}
static void *
access_bus_init(const device_t *info)
access_bus_init(UNUSED(const device_t *info))
{
access_bus_t *dev = (access_bus_t *) malloc(sizeof(access_bus_t));
memset(dev, 0, sizeof(access_bus_t));
@@ -830,7 +876,9 @@ fdc37c93x_init(const device_t *info)
is_compaq = (info->local >> 8) & 0x02;
dev->gpio_regs[0] = 0xff;
// dev->gpio_regs[1] = (info->local == 0x0030) ? 0xff : 0xfd;
#if 0
dev->gpio_regs[1] = (info->local == 0x0030) ? 0xff : 0xfd;
#endif
dev->gpio_regs[1] = (dev->chip_id == 0x30) ? 0xff : 0xfd;
if (dev->chip_id == 0x30) {

15
src/sio/sio_fdc37m60x.c
View File

@@ -68,9 +68,12 @@ fdc37m60x_log(const char *fmt, ...)
# define fdc37m60x_log(fmt, ...)
#endif
typedef struct
{
uint8_t index, regs[256], device_regs[10][256], cfg_lock, ide_function;
typedef struct fdc37m60x_t {
uint8_t index;
uint8_t regs[256];
uint8_t device_regs[10][256];
uint8_t cfg_lock;
uint8_t ide_function;
uint16_t sio_index_port;
fdc_t *fdc;
@@ -141,6 +144,9 @@ fdc37m60x_write(uint16_t addr, uint8_t val, void *priv)
dev->device_regs[CURRENT_LOGICAL_DEVICE][INDEX] = (INDEX == 0x30) ? (val & 1) : val;
fdc37m60x_logical_device_handler(dev);
break;
default:
break;
}
}
} else {
@@ -242,6 +248,9 @@ fdc37m60x_logical_device_handler(fdc37m60x_t *dev)
case 0x05:
fdc37m60x_uart_handler(1, dev);
break;
default:
break;
}
}

28
src/sio/sio_it8661f.c
View File

@@ -32,16 +32,19 @@
#include <86box/fdc.h>
#include <86box/fdd_common.h>
#include <86box/sio.h>
#include <86box/plat_unused.h>
#define LDN dev->regs[7]
typedef struct
{
typedef struct it8661f_t {
fdc_t *fdc_controller;
serial_t *uart[2];
uint8_t index, regs[256], device_regs[6][256];
int unlocked, enumerator;
uint8_t index;
uint8_t regs[256];
uint8_t device_regs[6][256];
int unlocked;
int enumerator;
} it8661f_t;
static uint8_t mb_pnp_key[32] = { 0x6a, 0xb5, 0xda, 0xed, 0xf6, 0xfb, 0x7d, 0xbe, 0xdf, 0x6f, 0x37, 0x1b, 0x0d, 0x86, 0xc3, 0x61, 0xb0, 0x58, 0x2c, 0x16, 0x8b, 0x45, 0xa2, 0xd1, 0xe8, 0x74, 0x3a, 0x9d, 0xce, 0xe7, 0x73, 0x39 };
@@ -99,6 +102,9 @@ it8661_fdc(uint16_t addr, uint8_t val, it8661f_t *dev)
case 0xf0:
dev->device_regs[0][addr] = val & 0x0f;
break;
default:
break;
}
fdc_set_base(dev->fdc_controller, (dev->device_regs[0][0x60] << 8) | (dev->device_regs[0][0x61]));
@@ -140,6 +146,9 @@ it8661_serial(int uart, uint16_t addr, uint8_t val, it8661f_t *dev)
case 0xf0:
dev->device_regs[1 + uart][addr] = val & 3;
break;
default:
break;
}
serial_setup(dev->uart[uart], (dev->device_regs[1 + uart][0x60] << 8) | (dev->device_regs[1 + uart][0x61]), dev->device_regs[1 + uart][0x70] & 0x0f);
@@ -177,6 +186,9 @@ it8661_lpt(uint16_t addr, uint8_t val, it8661f_t *dev)
case 0xf0:
dev->device_regs[3][addr] = val & 3;
break;
default:
break;
}
lpt1_init((dev->device_regs[3][0x60] << 8) | (dev->device_regs[3][0x61]));
@@ -201,6 +213,9 @@ it8661_ldn(uint16_t addr, uint8_t val, it8661f_t *dev)
case 3:
it8661_lpt(addr, val, dev);
break;
default:
break;
}
}
@@ -246,6 +261,9 @@ it8661f_write(uint16_t addr, uint8_t val, void *priv)
}
}
break;
default:
break;
}
return;
@@ -300,7 +318,7 @@ it8661f_close(void *priv)
}
static void *
it8661f_init(const device_t *info)
it8661f_init(UNUSED(const device_t *info))
{
it8661f_t *dev = (it8661f_t *) malloc(sizeof(it8661f_t));
memset(dev, 0, sizeof(it8661f_t));

25
src/sio/sio_pc87306.c
View File

@@ -34,10 +34,12 @@
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
#include <86box/plat_unused.h>
typedef struct {
uint8_t tries,
regs[29], gpio[2];
typedef struct pc87306_t {
uint8_t tries;
uint8_t regs[29];
uint8_t gpio[2];
int cur_reg;
fdc_t *fdc;
serial_t *uart[2];
@@ -112,6 +114,9 @@ lpt1_handler(pc87306_t *dev)
lpt_port = 0x000;
lpt_irq = 0xff;
break;
default:
break;
}
if (dev->regs[0x1b] & 0x10)
@@ -165,6 +170,9 @@ serial_handler(pc87306_t *dev, int uart)
case 3:
serial_setup(dev->uart[uart], 0x220, irq);
break;
default:
break;
}
break;
case 3:
@@ -181,8 +189,14 @@ serial_handler(pc87306_t *dev, int uart)
case 3:
serial_setup(dev->uart[uart], 0x228, irq);
break;
default:
break;
}
break;
default:
break;
}
}
@@ -324,6 +338,9 @@ pc87306_write(uint16_t port, uint8_t val, void *priv)
serial_handler(dev, 1);
}
break;
default:
break;
}
}
@@ -392,7 +409,7 @@ pc87306_close(void *priv)
}
static void *
pc87306_init(const device_t *info)
pc87306_init(UNUSED(const device_t *info))
{
pc87306_t *dev = (pc87306_t *) malloc(sizeof(pc87306_t));
memset(dev, 0, sizeof(pc87306_t));

48
src/sio/sio_pc87307.c
View File

@@ -35,13 +35,17 @@
#include <86box/fdc.h>
#include <86box/sio.h>
typedef struct {
uint8_t id, pm_idx,
regs[48], ld_regs[256][208],
pcregs[16], gpio[2][4],
pm[8];
uint16_t gpio_base, gpio_base2,
pm_base;
typedef struct pc87307_t {
uint8_t id;
uint8_t pm_idx;
uint8_t regs[48];
uint8_t ld_regs[256][208];
uint8_t pcregs[16];
uint8_t gpio[2][4];
uint8_t pm[8];
uint16_t gpio_base;
uint16_t gpio_base2;
uint16_t pm_base;
int cur_reg;
fdc_t *fdc;
serial_t *uart[2];
@@ -74,6 +78,9 @@ pc87307_gpio_read(uint16_t port, void *priv)
mask = dev->gpio[bank][0x0001];
ret = (ret & mask) | (pins & ~mask);
break;
default:
break;
}
return ret;
@@ -122,6 +129,9 @@ pc87307_pm_write(uint16_t port, uint8_t val, void *priv)
serial_handler(dev, 1);
serial_handler(dev, 0);
break;
default:
break;
}
}
}
@@ -307,6 +317,9 @@ pc87307_write(uint16_t port, uint8_t val, void *priv)
case 0x08:
pm_handler(dev);
break;
default:
break;
}
break;
case 0x60:
@@ -333,6 +346,9 @@ pc87307_write(uint16_t port, uint8_t val, void *priv)
case 0x08:
pm_handler(dev);
break;
default:
break;
}
break;
case 0x61:
@@ -364,6 +380,9 @@ pc87307_write(uint16_t port, uint8_t val, void *priv)
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0xfe;
pm_handler(dev);
break;
default:
break;
}
break;
case 0x63:
@@ -396,6 +415,9 @@ pc87307_write(uint16_t port, uint8_t val, void *priv)
case 0x08:
pm_handler(dev);
break;
default:
break;
}
break;
case 0xf0:
@@ -416,12 +438,18 @@ pc87307_write(uint16_t port, uint8_t val, void *priv)
case 0x06:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0x87;
break;
default:
break;
}
break;
case 0xf1:
if (dev->regs[0x07] == 0x03)
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0x0f;
break;
default:
break;
}
}
@@ -519,8 +547,10 @@ pc87307_reset(pc87307_t *dev)
dev->ld_regs[0x08][0x44] = 0x04;
dev->ld_regs[0x08][0x45] = 0x04;
// dev->gpio[0] = 0xff;
// dev->gpio[1] = 0xfb;
#if 0
dev->gpio[0] = 0xff;
dev->gpio[1] = 0xfb;
#endif
dev->gpio[0][0] = 0xff;
dev->gpio[0][1] = 0x00;
dev->gpio[0][2] = 0x00;

31
src/sio/sio_pc87309.c
View File

@@ -35,10 +35,12 @@
#include <86box/fdc.h>
#include <86box/sio.h>
typedef struct {
uint8_t id, pm_idx,
regs[48], ld_regs[256][208],
pm[8];
typedef struct pc87309_t {
uint8_t id;
uint8_t pm_idx;
uint8_t regs[48];
uint8_t ld_regs[256][208];
uint8_t pm[8];
uint16_t pm_base;
int cur_reg;
fdc_t *fdc;
@@ -64,6 +66,9 @@ pc87309_pm_write(uint16_t port, uint8_t val, void *priv)
serial_handler(dev, 1);
serial_handler(dev, 0);
break;
default:
break;
}
} else
dev->pm_idx = val & 0x07;
@@ -221,6 +226,9 @@ pc87309_write(uint16_t port, uint8_t val, void *priv)
case 0x04:
pm_handler(dev);
break;
default:
break;
}
break;
case 0x60:
@@ -244,6 +252,9 @@ pc87309_write(uint16_t port, uint8_t val, void *priv)
case 0x04:
pm_handler(dev);
break;
default:
break;
}
break;
case 0x63:
@@ -275,6 +286,9 @@ pc87309_write(uint16_t port, uint8_t val, void *priv)
case 0x06:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0xf8;
break;
default:
break;
}
break;
case 0x70:
@@ -296,6 +310,9 @@ pc87309_write(uint16_t port, uint8_t val, void *priv)
case 0x04:
pm_handler(dev);
break;
default:
break;
}
break;
case 0xf0:
@@ -316,12 +333,18 @@ pc87309_write(uint16_t port, uint8_t val, void *priv)
case 0x06:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0xc1;
break;
default:
break;
}
break;
case 0xf1:
if (dev->regs[0x07] == 0x00)
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0x0f;
break;
default:
break;
}
}

19
src/sio/sio_pc87310.c
View File

@@ -40,6 +40,7 @@
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
#include <86box/plat_unused.h>
#define HAS_IDE_FUNCTIONALITY dev->ide_function
@@ -61,9 +62,10 @@ pc87310_log(const char *fmt, ...)
# define pc87310_log(fmt, ...)
#endif
typedef struct {
uint8_t tries, ide_function,
reg;
typedef struct pc87310_t {
uint8_t tries;
uint8_t ide_function;
uint8_t reg;
fdc_t *fdc;
serial_t *uart[2];
} pc87310_t;
@@ -97,6 +99,9 @@ lpt1_handler(pc87310_t *dev)
lpt_port = 0x000;
lpt_irq = 0xff;
break;
default:
break;
}
if (lpt_port)
@@ -127,7 +132,7 @@ serial_handler(pc87310_t *dev, int uart)
}
static void
pc87310_write(uint16_t port, uint8_t val, void *priv)
pc87310_write(UNUSED(uint16_t port), uint8_t val, void *priv)
{
pc87310_t *dev = (pc87310_t *) priv;
uint8_t valxor;
@@ -189,7 +194,7 @@ pc87310_write(uint16_t port, uint8_t val, void *priv)
}
uint8_t
pc87310_read(uint16_t port, void *priv)
pc87310_read(UNUSED(uint16_t port), void *priv)
{
pc87310_t *dev = (pc87310_t *) priv;
uint8_t ret = 0xff;
@@ -219,7 +224,9 @@ pc87310_reset(pc87310_t *dev)
serial_handler(dev, 0);
serial_handler(dev, 1);
fdc_reset(dev->fdc);
// ide_pri_enable();
#if 0
ide_pri_enable();
#endif
}
static void

26
src/sio/sio_pc87311.c
View File

@@ -32,6 +32,7 @@
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
#include <86box/plat_unused.h>
#define HAS_IDE_FUNCTIONALITY dev->ide_function
@@ -64,10 +65,13 @@ pc87311_log(const char *fmt, ...)
# define pc87311_log(fmt, ...)
#endif
typedef struct
{
uint8_t index, regs[256], cfg_lock, ide_function;
uint16_t base, irq;
typedef struct pc87311_t {
uint8_t index;
uint8_t regs[256];
uint8_t cfg_lock;
uint8_t ide_function;
uint16_t base;
uint16_t irq;
fdc_t *fdc_controller;
serial_t *uart[2];
@@ -102,15 +106,21 @@ pc87311_write(uint16_t addr, uint8_t val, void *priv)
case 0x02:
POWER_TEST = val;
break;
default:
break;
}
break;
default:
break;
}
pc87311_enable(dev);
}
static uint8_t
pc87311_read(uint16_t addr, void *priv)
pc87311_read(UNUSED(uint16_t addr), void *priv)
{
pc87311_t *dev = (pc87311_t *) priv;
@@ -181,6 +191,9 @@ pc87311_uart_handler(uint8_t num, pc87311_t *dev)
dev->base = com4(dev);
dev->irq = COM4_IRQ;
break;
default:
break;
}
serial_setup(dev->uart[num & 1], dev->base, dev->irq);
pc87311_log("PC87311-UART%01x: BASE %04x IRQ %01x\n", num & 1, dev->base, dev->irq);
@@ -203,6 +216,9 @@ pc87311_lpt_handler(pc87311_t *dev)
dev->base = LPT2_ADDR;
dev->irq = LPT2_IRQ;
break;
default:
break;
}
lpt1_init(dev->base);
lpt1_irq(dev->irq);

23
src/sio/sio_pc87332.c
View File

@@ -35,9 +35,11 @@
#include <86box/fdc.h>
#include <86box/sio.h>
typedef struct {
uint8_t tries, has_ide,
fdc_on, regs[15];
typedef struct pc87332_t {
uint8_t tries;
uint8_t has_ide;
uint8_t fdc_on;
uint8_t regs[15];
int cur_reg;
fdc_t *fdc;
serial_t *uart[2];
@@ -69,6 +71,9 @@ lpt1_handler(pc87332_t *dev)
lpt_port = 0x000;
lpt_irq = 0xff;
break;
default:
break;
}
if (lpt_port)
@@ -105,6 +110,9 @@ serial_handler(pc87332_t *dev, int uart)
case 3:
serial_setup(dev->uart[uart], 0x220, COM3_IRQ);
break;
default:
break;
}
break;
case 3:
@@ -121,8 +129,14 @@ serial_handler(pc87332_t *dev, int uart)
case 3:
serial_setup(dev->uart[uart], 0x228, COM4_IRQ);
break;
default:
break;
}
break;
default:
break;
}
}
@@ -238,6 +252,9 @@ pc87332_write(uint16_t port, uint8_t val, void *priv)
lpt1_handler(dev);
}
break;
default:
break;
}
}

20
src/sio/sio_prime3b.c
View File

@@ -32,6 +32,7 @@
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
#include <86box/plat_unused.h>
#define FSR dev->regs[0xa0]
#define ASR dev->regs[0xa1]
@@ -56,10 +57,13 @@ prime3b_log(const char *fmt, ...)
# define prime3b_log(fmt, ...)
#endif
typedef struct
{
uint8_t index, regs[256], cfg_lock, ide_function;
uint16_t com3_addr, com4_addr;
typedef struct prime3b_t {
uint8_t index;
uint8_t regs[256];
uint8_t cfg_lock;
uint8_t ide_function;
uint16_t com3_addr;
uint16_t com4_addr;
fdc_t *fdc_controller;
serial_t *uart[2];
@@ -121,17 +125,23 @@ prime3b_write(uint16_t addr, uint8_t val, void *priv)
dev->com3_addr = 0x220;
dev->com4_addr = 0x228;
break;
default:
break;
}
break;
case 0xa5: /* ECP Register */
dev->regs[0xa5] = val;
break;
default:
break;
}
}
}
static uint8_t
prime3b_read(uint16_t addr, void *priv)
prime3b_read(UNUSED(uint16_t addr), void *priv)
{
prime3b_t *dev = (prime3b_t *) priv;

17
src/sio/sio_prime3c.c
View File

@@ -32,6 +32,7 @@
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
#include <86box/plat_unused.h>
#ifdef ENABLE_PRIME3C_LOG
int prime3c_do_log = ENABLE_PRIME3C_LOG;
@@ -75,9 +76,11 @@ prime3c_log(const char *fmt, ...)
/* IDE functionality(Note on Init) */
#define HAS_IDE_FUNCTIONALITY dev->ide_function
typedef struct
{
uint8_t index, regs[256], cfg_lock, ide_function;
typedef struct prime3c_t {
uint8_t index;
uint8_t regs[256];
uint8_t cfg_lock;
uint8_t ide_function;
fdc_t *fdc_controller;
serial_t *uart[2];
@@ -189,14 +192,20 @@ prime3c_write(uint16_t addr, uint8_t val, void *priv)
case 0xd8:
dev->regs[dev->index] = val;
break;
default:
break;
}
}
break;
default:
break;
}
}
static uint8_t
prime3c_read(uint16_t addr, void *priv)
prime3c_read(UNUSED(uint16_t addr), void *priv)
{
prime3c_t *dev = (prime3c_t *) priv;

9
src/sio/sio_um8669f.c
View File

@@ -37,6 +37,7 @@
#include <86box/gameport.h>
#include <86box/sio.h>
#include <86box/isapnp.h>
#include <86box/plat_unused.h>
/* This ROM was reconstructed out of many assumptions, some of which based on the IT8671F. */
static uint8_t um8669f_pnp_rom[] = {
@@ -112,7 +113,8 @@ um8669f_log(const char *fmt, ...)
#endif
typedef struct um8669f_t {
int locked, cur_reg_108;
int locked;
int cur_reg_108;
void *pnp_card;
isapnp_device_config_t *pnp_config[5];
@@ -184,6 +186,9 @@ um8669f_pnp_config_changed(uint8_t ld, isapnp_device_config_t *config, void *pri
um8669f_log("UM8669F: Game port disabled\n");
gameport_remap(dev->gameport, 0);
}
default:
break;
}
}
@@ -263,7 +268,7 @@ um8669f_close(void *priv)
}
static void *
um8669f_init(const device_t *info)
um8669f_init(UNUSED(const device_t *info))
{
um8669f_log("UM8669F: init()\n");

21
src/sio/sio_vt82c686.c
View File

@@ -31,10 +31,17 @@
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
#include <86box/plat_unused.h>
typedef struct {
uint8_t cur_reg, last_val, regs[25],
fdc_dma, fdc_irq, uart_irq[2], lpt_dma, lpt_irq;
typedef struct vt82c686_t {
uint8_t cur_reg;
uint8_t last_val;
uint8_t regs[25];
uint8_t fdc_dma;
uint8_t fdc_irq;
uint8_t uart_irq[2];
uint8_t lpt_dma;
uint8_t lpt_irq;
fdc_t *fdc;
serial_t *uart[2];
} vt82c686_t;
@@ -189,6 +196,9 @@ vt82c686_write(uint16_t port, uint8_t val, void *priv)
dev->regs[reg] &= 0xf7;
vt82c686_fdc_handler(dev);
break;
default:
break;
}
}
@@ -242,6 +252,9 @@ vt82c686_sio_write(uint8_t addr, uint8_t val, void *priv)
if (val & 0x02)
io_sethandler(FDC_PRIMARY_ADDR, 2, vt82c686_read, NULL, NULL, vt82c686_write, NULL, NULL, dev);
break;
default:
break;
}
}
@@ -272,7 +285,7 @@ vt82c686_close(void *priv)
}
static void *
vt82c686_init(const device_t *info)
vt82c686_init(UNUSED(const device_t *info))
{
vt82c686_t *dev = (vt82c686_t *) malloc(sizeof(vt82c686_t));
memset(dev, 0, sizeof(vt82c686_t));

18
src/sio/sio_w83787f.c
View File

@@ -74,13 +74,16 @@ w83787_log(const char *fmt, ...)
#define HAS_IDE_FUNCTIONALITY dev->ide_function
typedef struct {
uint8_t tries, regs[42];
typedef struct w83787f_t {
uint8_t tries;
uint8_t regs[42];
uint16_t reg_init;
int locked, rw_locked,
cur_reg,
key, ide_function,
ide_start;
int locked;
int rw_locked;
int cur_reg;
int key;
int ide_function;
int ide_start;
fdc_t *fdc;
serial_t *uart[2];
void *gameport;
@@ -342,6 +345,9 @@ w83787f_write(uint16_t port, uint8_t val, void *priv)
if (valxor & 0x20)
w83787f_remap(dev);
break;
default:
break;
}
}

23
src/sio/sio_w83877f.c
View File

@@ -56,13 +56,16 @@
#define PRTIQS (dev->regs[0x27] & 0x0f)
#define ECPIRQ ((dev->regs[0x27] >> 5) & 0x07)
typedef struct {
uint8_t tries, regs[42];
uint16_t reg_init;
int locked, rw_locked,
cur_reg,
base_address, key,
key_times;
typedef struct w83877f_t {
uint8_t tries;
uint8_t regs[42];
uint16_t reg_init;
int locked;
int rw_locked;
int cur_reg;
int base_address;
int key;
int key_times;
fdc_t *fdc;
serial_t *uart[2];
} w83877f_t;
@@ -140,6 +143,9 @@ make_port(w83877f_t *dev, uint8_t reg)
if ((p < 0x100) || (p > 0x3F8))
p = COM2_ADDR;
break;
default:
break;
}
return p;
@@ -358,6 +364,9 @@ w83877f_write(uint16_t port, uint8_t val, void *priv)
w83877f_serial_handler(dev, 0);
}
break;
default:
break;
}
}

51
src/sio/sio_w83977f.c
View File

@@ -36,13 +36,17 @@
#define HEFRAS (dev->regs[0x26] & 0x40)
typedef struct {
uint8_t id, tries,
regs[48],
dev_regs[256][208];
int locked, rw_locked,
cur_reg, base_address,
type, hefras;
typedef struct w83977f_t {
uint8_t id;
uint8_t tries;
uint8_t regs[48];
uint8_t dev_regs[256][208];
int locked;
int rw_locked;
int cur_reg;
int base_address;
int type;
int hefras;
fdc_t *fdc;
serial_t *uart[2];
} w83977f_t;
@@ -145,6 +149,9 @@ w83977f_serial_handler(w83977f_t *dev, int uart)
case 0x03:
clock_src = 24000000.0 / 1.625;
break;
default:
break;
}
serial_set_clock_src(dev->uart[uart], clock_src);
@@ -194,8 +201,10 @@ w83977f_write(uint16_t port, uint8_t val, void *priv)
switch (dev->cur_reg) {
case 0x02:
/* if (valxor & 0x02)
softresetx86(); */
#if 0
if (valxor & 0x02)
softresetx86();
#endif
break;
case 0x22:
if (valxor & 0x20)
@@ -226,6 +235,9 @@ w83977f_write(uint16_t port, uint8_t val, void *priv)
case 0x03:
w83977f_serial_handler(dev, ld - 2);
break;
default:
break;
}
break;
case 0x60:
@@ -242,6 +254,9 @@ w83977f_write(uint16_t port, uint8_t val, void *priv)
case 0x03:
w83977f_serial_handler(dev, ld - 2);
break;
default:
break;
}
break;
case 0x70:
@@ -257,6 +272,9 @@ w83977f_write(uint16_t port, uint8_t val, void *priv)
case 0x03:
w83977f_serial_handler(dev, ld - 2);
break;
default:
break;
}
break;
case 0xf0:
@@ -281,6 +299,9 @@ w83977f_write(uint16_t port, uint8_t val, void *priv)
if (valxor & 0x03)
w83977f_serial_handler(dev, ld - 2);
break;
default:
break;
}
break;
case 0xf1:
@@ -298,6 +319,9 @@ w83977f_write(uint16_t port, uint8_t val, void *priv)
if (!dev->id && (valxor & 0x01))
fdc_set_swwp(dev->fdc, (val & 0x01) ? 1 : 0);
break;
default:
break;
}
break;
case 0xf2:
@@ -315,6 +339,9 @@ w83977f_write(uint16_t port, uint8_t val, void *priv)
if (!dev->id && (valxor & 0x03))
fdc_update_rwc(dev->fdc, 0, val & 0x03);
break;
default:
break;
}
break;
case 0xf4:
@@ -329,8 +356,14 @@ w83977f_write(uint16_t port, uint8_t val, void *priv)
if (!dev->id && (valxor & 0x18))
fdc_update_drvrate(dev->fdc, dev->cur_reg & 0x03, (val & 0x18) >> 3);
break;
default:
break;
}
break;
default:
break;
}
}