Preliminary VIA Cyrix III emulation
This adds preliminary emulation of the first-gen Samuel core, used in the VIA Cyrix III CPU, at clock speeds from 66 to 700 MHz. This also moves the 440BX emulation out of the dev-branch. Things working: - CPUID - Windows 98SE - Timings seem identical between WinChip/W2's integer section and this Things left to do: - 3DNow on old dynarec - Half-speed FPU (currently simulated with WinChip 1 timings instead of WinChip 2)
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nerd73
@@ -1601,6 +1601,61 @@ cpu_set(void)
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#endif
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break;
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#endif
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case CPU_CYRIX3S:
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#ifdef USE_DYNAREC
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#ifdef USE_NEW_DYNAREC
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x86_setopcodes(ops_386, ops_winchip2_0f, dynarec_ops_386, dynarec_ops_winchip2_0f);
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#else
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x86_setopcodes(ops_386, ops_winchip_0f, dynarec_ops_386, dynarec_ops_winchip_0f);
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#endif
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#else
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#ifdef USE_NEW_DYNAREC
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x86_setopcodes(ops_386, ops_winchip2_0f);
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#else
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x86_setopcodes(ops_386, ops_winchip_0f);
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#endif
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#endif
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timing_rr = 1; /*register dest - register src*/
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timing_rm = 2; /*register dest - memory src*/
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timing_mr = 2; /*memory dest - register src*/
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timing_mm = 3;
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timing_rml = 2; /*register dest - memory src long*/
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timing_mrl = 2; /*memory dest - register src long*/
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timing_mml = 3;
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timing_bt = 3-1; /*branch taken*/
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timing_bnt = 1; /*branch not taken*/
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#ifdef USE_NEW_DYNAREC
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cpu_features = CPU_FEATURE_RDTSC | CPU_FEATURE_MMX | CPU_FEATURE_MSR | CPU_FEATURE_CR4 | CPU_FEATURE_3DNOW;
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#else
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cpu_features = CPU_FEATURE_RDTSC | CPU_FEATURE_MMX | CPU_FEATURE_MSR | CPU_FEATURE_CR4;
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#endif
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msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) | (1 << 16) | (1 << 18) | (1 << 19) | (1 << 20) | (1 << 21);
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cpu_CR4_mask = CR4_TSD | CR4_DE | CR4_MCE | CR4_PCE;
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/*unknown*/
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timing_int_rm = 26;
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timing_int_v86 = 82;
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timing_int_pm = 44;
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timing_int_pm_outer = 71;
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timing_iret_rm = 7;
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timing_iret_v86 = 26;
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timing_iret_pm = 10;
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timing_iret_pm_outer = 26;
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timing_call_rm = 4;
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timing_call_pm = 15;
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timing_call_pm_gate = 26;
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timing_call_pm_gate_inner = 35;
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timing_retf_rm = 4;
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timing_retf_pm = 7;
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timing_retf_pm_outer = 23;
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timing_jmp_rm = 5;
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timing_jmp_pm = 7;
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timing_jmp_pm_gate = 17;
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timing_misaligned = 2;
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cpu_cyrix_alignment = 1;
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#ifdef USE_DYNAREC
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codegen_timing_set(&codegen_timing_winchip);
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#endif
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break;
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default:
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fatal("cpu_set : unknown CPU type %i\n", cpu_s->cpu_type);
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@@ -1755,7 +1810,7 @@ cpu_CPUID(void)
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}
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break;
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case 1:
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EAX = 0x580;
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EAX = CPUID;
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EBX = ECX = 0;
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EDX = CPUID_FPU | CPUID_TSC | CPUID_MSR;
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if (cpu_has_feature(CPU_FEATURE_CX8))
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@@ -1767,7 +1822,7 @@ cpu_CPUID(void)
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EAX = 0x80000005;
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break;
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case 0x80000001:
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EAX = 0x580;
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EAX = CPUID;
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EDX = CPUID_FPU | CPUID_TSC | CPUID_MSR;
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if (cpu_has_feature(CPU_FEATURE_CX8))
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EDX |= CPUID_CMPXCHG8B;
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@@ -2281,7 +2336,67 @@ cpu_CPUID(void)
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break;
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#endif
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#endif
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case CPU_CYRIX3S:
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switch (EAX)
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{
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case 0:
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EAX = 1;
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if (msr.fcr2 & (1 << 14))
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{
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EBX = msr.fcr3 >> 32;
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ECX = msr.fcr3 & 0xffffffff;
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EDX = msr.fcr2 >> 32;
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}
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else
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{
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EBX = 0x746e6543; /*CentaurHauls*/
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ECX = 0x736c7561;
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EDX = 0x48727561;
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}
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break;
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case 1:
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EAX = CPUID;
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EBX = ECX = 0;
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EDX = CPUID_FPU | CPUID_TSC | CPUID_MSR;
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if (cpu_has_feature(CPU_FEATURE_CX8))
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EDX |= CPUID_CMPXCHG8B;
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if (msr.fcr & (1 << 9))
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EDX |= CPUID_MMX;
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break;
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case 0x80000000:
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EAX = 0x80000005;
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break;
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case 0x80000001:
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EAX = CPUID;
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EDX = CPUID_FPU | CPUID_TSC | CPUID_MSR;
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if (cpu_has_feature(CPU_FEATURE_CX8))
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EDX |= CPUID_CMPXCHG8B;
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if (msr.fcr & (1 << 9))
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EDX |= CPUID_MMX;
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#ifdef USE_NEW_DYNAREC
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if (cpu_has_feature(CPU_FEATURE_3DNOW))
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EDX |= CPUID_3DNOW;
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#endif
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break;
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case 0x80000002: /*Processor name string*/
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EAX = 0x20414956; /*VIA Samuel*/
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EBX = 0x756d6153;
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ECX = 0x00006c65;
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EDX = 0x00000000;
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break;
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case 0x80000005: /*Cache information*/
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EBX = 0x08800880; /*TLBs*/
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ECX = 0x40040120; /*L1 data cache*/
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EDX = 0x40020120; /*L1 instruction cache*/
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break;
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default:
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EAX = EBX = ECX = EDX = 0;
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break;
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}
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break;
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}
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}
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@@ -2295,11 +2410,11 @@ void cpu_ven_reset(void)
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case CPU_K6:
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amd_efer = amd_whcr = 0ULL;
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break;
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#ifdef USE_NEW_DYNAREC
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case CPU_K6_2:
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amd_efer = amd_whcr = 0ULL;
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star = 0ULL;
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break;
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#ifdef USE_NEW_DYNAREC
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case CPU_K6_2C:
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amd_efer = 2ULL;
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amd_whcr = star = 0ULL;
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@@ -2363,7 +2478,37 @@ void cpu_RDMSR()
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break;
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}
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break;
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case CPU_CYRIX3S:
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EAX = EDX = 0;
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switch (ECX)
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{
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case 0x02:
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EAX = msr.tr1;
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break;
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case 0x0e:
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EAX = msr.tr12;
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break;
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case 0x10:
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EAX = tsc & 0xffffffff;
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EDX = tsc >> 32;
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break;
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case 0x11:
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EAX = msr.cesr;
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break;
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case 0x1107:
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EAX = msr.fcr;
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break;
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case 0x108:
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EAX = msr.fcr2 & 0xffffffff;
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EDX = msr.fcr2 >> 32;
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break;
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case 0x10a:
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EAX = cpu_multi & 3;
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break;
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}
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break;
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#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K))
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case CPU_K5:
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case CPU_5K86:
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@@ -2778,6 +2923,50 @@ void cpu_WRMSR()
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cpu_features |= CPU_FEATURE_3DNOW;
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else
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cpu_features &= ~CPU_FEATURE_3DNOW;
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#endif
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if (EAX & (1 << 29))
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CPUID = 0;
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else
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CPUID = machines[machine].cpu[cpu_manufacturer].cpus[cpu].cpuid_model;
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break;
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case 0x108:
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msr.fcr2 = EAX | ((uint64_t)EDX << 32);
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break;
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case 0x109:
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msr.fcr3 = EAX | ((uint64_t)EDX << 32);
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break;
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}
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break;
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case CPU_CYRIX3S:
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switch (ECX)
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{
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case 0x02:
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msr.tr1 = EAX & 2;
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break;
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case 0x0e:
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msr.tr12 = EAX & 0x228;
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break;
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case 0x10:
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tsc = EAX | ((uint64_t)EDX << 32);
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break;
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case 0x11:
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msr.cesr = EAX & 0xff00ff;
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break;
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case 0x1107:
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msr.fcr = EAX;
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if (EAX & (1 << 9))
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cpu_features |= CPU_FEATURE_MMX;
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else
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cpu_features &= ~CPU_FEATURE_MMX;
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if (EAX & (1 << 1))
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cpu_features |= CPU_FEATURE_CX8;
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else
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cpu_features &= ~CPU_FEATURE_CX8;
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#ifdef USE_NEW_DYNAREC
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if (EAX & (1 << 20))
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cpu_features |= CPU_FEATURE_3DNOW;
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else
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cpu_features &= ~CPU_FEATURE_3DNOW;
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#endif
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if (EAX & (1 << 29))
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CPUID = 0;
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@@ -2792,7 +2981,7 @@ void cpu_WRMSR()
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break;
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}
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break;
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#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K))
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case CPU_K5:
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case CPU_5K86:
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