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Preliminary VIA Cyrix III emulation

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This adds preliminary emulation of the first-gen Samuel core, used in the VIA Cyrix III CPU, at clock speeds from 66 to 700 MHz. This also moves the 440BX emulation out of the dev-branch.

Things working:
- CPUID
- Windows 98SE
- Timings seem identical between WinChip/W2's integer section and this

Things left to do:
- 3DNow on old dynarec
- Half-speed FPU (currently simulated with WinChip 1 timings instead of WinChip 2)
This commit is contained in:
nerd73
2020-03-01 15:06:35 -07:00
parent 5c4542283d
commit 111d82fa0c
10 changed files with 267 additions and 113 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/chipset/chipset.h
View File

@@ -43,8 +43,8 @@ extern const device_t i430vx_device;
extern const device_t i430tx_device;
#if defined(DEV_BRANCH) && defined(USE_I686)
extern const device_t i440fx_device;
extern const device_t i440bx_device;
#endif
extern const device_t i440bx_device;
/* NEAT */
extern const device_t neat_device;

132
src/chipset/intel_4x0.c
View File

@@ -41,11 +41,12 @@ enum
INTEL_430FX_PB640,
INTEL_430HX,
INTEL_430VX,
INTEL_430TX
INTEL_430TX,
#if defined(DEV_BRANCH) && defined(USE_I686)
,INTEL_440FX,
INTEL_440BX
INTEL_440FX,
#endif
INTEL_440BX
};
typedef struct
@@ -84,7 +85,6 @@ i4x0_map(uint32_t addr, uint32_t size, int state)
}
#if defined(DEV_BRANCH) && defined(USE_I686)
static void
i4x0_mask_bar(uint8_t *regs)
{
@@ -95,7 +95,6 @@ i4x0_mask_bar(uint8_t *regs)
regs[0x12] = (bar >> 16) & 0xff;
regs[0x13] = (bar >> 24) & 0xff;
}
#endif
static uint8_t
@@ -122,19 +121,12 @@ static void
i4x0_write(int func, int addr, uint8_t val, void *priv)
{
i4x0_t *dev = (i4x0_t *) priv;
#if defined(DEV_BRANCH) && defined(USE_I686)
uint8_t *regs = (uint8_t *) dev->regs[func];
uint8_t *regs_l = (uint8_t *) dev->regs_locked[func];
int i;
#else
uint8_t *regs = (uint8_t *) dev->regs;
#endif
#if defined(DEV_BRANCH) && defined(USE_I686)
if (func > dev->max_func) {
#else
if (func > 0) {
#endif
// pclog("invalid write %02X to %02X:%02X\n", val, func, addr);
return;
}
@@ -148,9 +140,6 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case 0x04: /*Command register*/
switch (dev->type) {
case INTEL_420TX: case INTEL_420ZX: case INTEL_430LX: case INTEL_430NX:
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440BX:
#endif
default:
regs[0x04] = (regs[0x04] & ~0x42) | (val & 0x42);
break;
@@ -164,9 +153,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x05:
switch (dev->type) {
case INTEL_420TX: case INTEL_420ZX: case INTEL_430LX: case INTEL_430NX: case INTEL_430HX:
case INTEL_420TX: case INTEL_420ZX: case INTEL_430LX: case INTEL_430NX: case INTEL_430HX: case INTEL_440BX:
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX: case INTEL_440BX:
case INTEL_440FX:
#endif
regs[0x05] = (regs[0x05] & ~0x01) | (val & 0x01);
break;
@@ -185,10 +174,10 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440FX:
regs[0x07] &= ~(val & 0xf9);
break;
case INTEL_440BX:
regs[0x07] &= ~(val & 0xf0);
break;
#endif
case INTEL_440BX:
regs[0x07] &= ~(val & 0xf0);
break;
}
break;
case 0x0d:
@@ -208,7 +197,6 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
}
break;
#if defined(DEV_BRANCH) && defined(USE_I686)
case 0x12:
switch (dev->type) {
case INTEL_440BX:
@@ -235,7 +223,6 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
}
break;
#endif
case 0x4f:
switch (dev->type) {
case INTEL_430HX:
@@ -271,10 +258,10 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440FX:
regs[0x50] = (val & 0xf4);
break;
case INTEL_440BX:
regs[0x50] = (regs[0x50] & 0x14) | (val & 0xeb);
break;
#endif
case INTEL_440BX:
regs[0x50] = (regs[0x50] & 0x14) | (val & 0xeb);
break;
}
break;
case 0x51:
@@ -286,10 +273,10 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440FX:
regs[0x51] = (val & 0xc3);
break;
case INTEL_440BX:
regs[0x51] = (regs[0x50] & 0x70) | (val & 0x8f);
break;
#endif
case INTEL_440BX:
regs[0x51] = (regs[0x50] & 0x70) | (val & 0x8f);
break;
}
break;
case 0x52: /* Cache Control Register */
@@ -307,11 +294,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
#endif
regs[0x52] = val;
break;
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440BX:
regs[0x52] = val & 0x07;
break;
#endif
}
break;
case 0x53:
@@ -397,10 +382,10 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440FX:
regs[0x57] = val & 0x77;
break;
case INTEL_440BX:
regs[0x57] = val & 0x3f;
break;
#endif
case INTEL_440BX:
regs[0x57] = val & 0x3f;
break;
}
break;
case 0x58:
@@ -410,9 +395,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
regs[0x58] = val & 0x01;
break;
case INTEL_430NX:
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440BX:
#endif
regs[0x58] = val & 0x03;
break;
case INTEL_430FX: case INTEL_430FX_PB640:
@@ -489,9 +472,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
switch (dev->type) {
case INTEL_420TX: case INTEL_420ZX:
case INTEL_430LX: case INTEL_430NX:
case INTEL_430HX:
case INTEL_430HX: case INTEL_440BX:
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX: case INTEL_440BX:
case INTEL_440FX:
#endif
default:
regs[addr] = val;
@@ -509,9 +492,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
switch (dev->type) {
case INTEL_420TX: case INTEL_420ZX:
case INTEL_430LX: case INTEL_430NX:
case INTEL_430HX:
case INTEL_430HX: case INTEL_440BX:
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX: case INTEL_440BX:
case INTEL_440FX:
#endif
regs[addr] = val;
break;
@@ -526,8 +509,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case 0x66:
switch (dev->type) {
case INTEL_430NX: case INTEL_430HX:
case INTEL_440BX:
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX: case INTEL_440BX:
case INTEL_440FX:
#endif
regs[addr] = val;
break;
@@ -536,8 +520,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case 0x67:
switch (dev->type) {
case INTEL_430NX: case INTEL_430HX:
case INTEL_440BX:
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX: case INTEL_440BX:
case INTEL_440FX:
#endif
regs[addr] = val;
break;
@@ -562,18 +547,16 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440FX:
regs[0x68] = val & 0xc0;
break;
case INTEL_440BX:
regs[0x68] = (regs[0x68] & 0x38) | (val & 0xc7);
break;
#endif
case INTEL_440BX:
regs[0x68] = (regs[0x68] & 0x38) | (val & 0xc7);
break;
}
break;
case 0x69:
switch (dev->type) {
case INTEL_430NX:
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440BX:
#endif
regs[0x69] = val;
break;
case INTEL_430VX:
@@ -584,14 +567,11 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case 0x6a: case 0x6b:
switch (dev->type) {
case INTEL_430NX:
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440BX:
#endif
regs[addr] = val;
break;
}
break;
#if defined(DEV_BRANCH) && defined(USE_I686)
case 0x6c: case 0x6d: case 0x6e:
switch (dev->type) {
case INTEL_440BX:
@@ -599,7 +579,6 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
}
break;
#endif
case 0x70:
switch (dev->type) {
case INTEL_420TX: case INTEL_420ZX:
@@ -651,24 +630,19 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430VX:
regs[0x73] = val & 0x03;
break;
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440BX:
regs[0x73] = val;
break;
#endif
}
break;
case 0x74:
switch (dev->type) {
case INTEL_430VX:
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440BX:
#endif
regs[0x74] = val;
break;
}
break;
#if defined(DEV_BRANCH) && defined(USE_I686)
case 0x75: case 0x76:
case 0x7b:
switch (dev->type) {
@@ -682,17 +656,14 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
regs[0x77] = val & 0x03;
}
break;
#endif
case 0x78:
switch (dev->type) {
case INTEL_430VX:
regs[0x78] = val & 0xcf;
break;
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440BX:
regs[0x78] = val & 0x0f;
break;
#endif
}
break;
case 0x79:
@@ -704,14 +675,11 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev);
// pclog("430TX: PM2_CTL now %sabled\n", (val & 0x40) ? "en" : "dis");
break;
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440BX:
regs[0x79] = val;
break;
#endif
}
break;
#if defined(DEV_BRANCH) && defined(USE_I686)
case 0x7a:
switch (dev->type) {
case INTEL_440BX:
@@ -723,18 +691,15 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
}
break;
#endif
case 0x7c:
switch (dev->type) {
case INTEL_420TX: case INTEL_420ZX:
case INTEL_430LX: case INTEL_430NX:
regs[0x7c] = val & 0x8f;
break;
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440BX:
regs[0x7c] = val & 0x1f;
break;
#endif
}
case 0x7d:
switch (dev->type) {
@@ -750,7 +715,6 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
regs[addr] = val;
break;
}
#if defined(DEV_BRANCH) && defined(USE_I686)
case 0x80:
switch (dev->type) {
case INTEL_440BX:
@@ -758,7 +722,6 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
}
break;
#endif
case 0x90:
switch (dev->type) {
case INTEL_430HX:
@@ -768,23 +731,22 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440FX:
regs[0x80] = val & 0x1b;
break;
case INTEL_440BX:
regs[0x7c] = val;
break;
#endif
case INTEL_440BX:
regs[0x7c] = val;
break;
}
break;
case 0x91:
switch (dev->type) {
case INTEL_430HX:
case INTEL_430HX: case INTEL_440BX:
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX: case INTEL_440BX:
case INTEL_440FX:
#endif
regs[0x91] &= ~(val & 0x11);
break;
}
break;
#if defined(DEV_BRANCH) && defined(USE_I686)
case 0x92:
switch (dev->type) {
case INTEL_440BX:
@@ -792,6 +754,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
}
break;
#if defined(DEV_BRANCH) && defined(USE_I686)
case 0x93:
switch (dev->type) {
case INTEL_440FX:
@@ -800,6 +763,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
}
break;
#endif
case 0xa8: case 0xa9:
switch (dev->type) {
case INTEL_440BX:
@@ -948,7 +912,6 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
}
break;
#endif
}
}
@@ -958,17 +921,9 @@ i4x0_read(int func, int addr, void *priv)
{
i4x0_t *dev = (i4x0_t *) priv;
uint8_t ret = 0xff;
#if defined(DEV_BRANCH) && defined(USE_I686)
uint8_t *regs = (uint8_t *) dev->regs[func];
#else
uint8_t *regs = (uint8_t *) dev->regs;
#endif
#if defined(DEV_BRANCH) && defined(USE_I686)
if (func > dev->max_func) {
#else
if (func > 0) {
#endif
ret = 0xff;
// pclog("invalid read %02X from %02X:%02X\n", ret, func, addr);
} else {
@@ -1005,12 +960,10 @@ i4x0_reset(void *priv)
else
i4x0_write(0, 0x72, 0x00, priv);
#if defined(DEV_BRANCH) && defined(USE_I686)
if (dev->type == INTEL_440BX) {
for (i = 0; i <= dev->max_func; i++)
memset(dev->regs_locked[i], 0x00, 256 * sizeof(uint8_t));
}
#endif
smbase = 0xa0000;
}
@@ -1035,11 +988,7 @@ static void
dev->type = info->local & 0xff;
#if defined(DEV_BRANCH) && defined(USE_I686)
regs = (uint8_t *) dev->regs[0];
#else
regs = (uint8_t *) dev->regs;
#endif
// This is off by default and has to be moved to the appropriate register handling.
// io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev);
@@ -1185,6 +1134,7 @@ static void
regs[0x71] = 0x10;
regs[0x72] = 0x02;
break;
#endif
case INTEL_440BX:
regs[0x7a] = (info->local >> 8) & 0xff;
dev->max_func = (regs[0x7a] & 0x02) ? 0 : 1;
@@ -1210,7 +1160,6 @@ static void
regs[0xa5] = 0x02;
regs[0xa7] = 0x1f;
break;
#endif
}
regs[0x04] = 0x06; regs[0x07] = 0x02;
@@ -1233,7 +1182,6 @@ static void
smbase = 0xa0000;
#if defined(DEV_BRANCH) && defined(USE_I686)
if ((dev->type == INTEL_440BX) && (dev->max_func == 1)) {
regs = (uint8_t *) dev->regs[1];
@@ -1249,7 +1197,6 @@ static void
regs[0x24] = 0xf0; regs[0x25] = 0xff;
regs[0x3e] = 0x80;
}
#endif
pci_add_card(PCI_ADD_NORTHBRIDGE, i4x0_read, i4x0_write, dev);
@@ -1407,7 +1354,7 @@ const device_t i440fx_device =
NULL
};
#endif
const device_t i440bx_device =
{
"Intel 82443BX",
@@ -1421,4 +1368,3 @@ const device_t i440bx_device =
NULL,
NULL
};
#endif

195
src/cpu_common/cpu.c
View File

@@ -1601,6 +1601,61 @@ cpu_set(void)
#endif
break;
#endif
case CPU_CYRIX3S:
#ifdef USE_DYNAREC
#ifdef USE_NEW_DYNAREC
x86_setopcodes(ops_386, ops_winchip2_0f, dynarec_ops_386, dynarec_ops_winchip2_0f);
#else
x86_setopcodes(ops_386, ops_winchip_0f, dynarec_ops_386, dynarec_ops_winchip_0f);
#endif
#else
#ifdef USE_NEW_DYNAREC
x86_setopcodes(ops_386, ops_winchip2_0f);
#else
x86_setopcodes(ops_386, ops_winchip_0f);
#endif
#endif
timing_rr = 1; /*register dest - register src*/
timing_rm = 2; /*register dest - memory src*/
timing_mr = 2; /*memory dest - register src*/
timing_mm = 3;
timing_rml = 2; /*register dest - memory src long*/
timing_mrl = 2; /*memory dest - register src long*/
timing_mml = 3;
timing_bt = 3-1; /*branch taken*/
timing_bnt = 1; /*branch not taken*/
#ifdef USE_NEW_DYNAREC
cpu_features = CPU_FEATURE_RDTSC | CPU_FEATURE_MMX | CPU_FEATURE_MSR | CPU_FEATURE_CR4 | CPU_FEATURE_3DNOW;
#else
cpu_features = CPU_FEATURE_RDTSC | CPU_FEATURE_MMX | CPU_FEATURE_MSR | CPU_FEATURE_CR4;
#endif
msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) | (1 << 16) | (1 << 18) | (1 << 19) | (1 << 20) | (1 << 21);
cpu_CR4_mask = CR4_TSD | CR4_DE | CR4_MCE | CR4_PCE;
/*unknown*/
timing_int_rm = 26;
timing_int_v86 = 82;
timing_int_pm = 44;
timing_int_pm_outer = 71;
timing_iret_rm = 7;
timing_iret_v86 = 26;
timing_iret_pm = 10;
timing_iret_pm_outer = 26;
timing_call_rm = 4;
timing_call_pm = 15;
timing_call_pm_gate = 26;
timing_call_pm_gate_inner = 35;
timing_retf_rm = 4;
timing_retf_pm = 7;
timing_retf_pm_outer = 23;
timing_jmp_rm = 5;
timing_jmp_pm = 7;
timing_jmp_pm_gate = 17;
timing_misaligned = 2;
cpu_cyrix_alignment = 1;
#ifdef USE_DYNAREC
codegen_timing_set(&codegen_timing_winchip);
#endif
break;
default:
fatal("cpu_set : unknown CPU type %i\n", cpu_s->cpu_type);
@@ -1755,7 +1810,7 @@ cpu_CPUID(void)
}
break;
case 1:
EAX = 0x580;
EAX = CPUID;
EBX = ECX = 0;
EDX = CPUID_FPU | CPUID_TSC | CPUID_MSR;
if (cpu_has_feature(CPU_FEATURE_CX8))
@@ -1767,7 +1822,7 @@ cpu_CPUID(void)
EAX = 0x80000005;
break;
case 0x80000001:
EAX = 0x580;
EAX = CPUID;
EDX = CPUID_FPU | CPUID_TSC | CPUID_MSR;
if (cpu_has_feature(CPU_FEATURE_CX8))
EDX |= CPUID_CMPXCHG8B;
@@ -2281,7 +2336,67 @@ cpu_CPUID(void)
break;
#endif
#endif
case CPU_CYRIX3S:
switch (EAX)
{
case 0:
EAX = 1;
if (msr.fcr2 & (1 << 14))
{
EBX = msr.fcr3 >> 32;
ECX = msr.fcr3 & 0xffffffff;
EDX = msr.fcr2 >> 32;
}
else
{
EBX = 0x746e6543; /*CentaurHauls*/
ECX = 0x736c7561;
EDX = 0x48727561;
}
break;
case 1:
EAX = CPUID;
EBX = ECX = 0;
EDX = CPUID_FPU | CPUID_TSC | CPUID_MSR;
if (cpu_has_feature(CPU_FEATURE_CX8))
EDX |= CPUID_CMPXCHG8B;
if (msr.fcr & (1 << 9))
EDX |= CPUID_MMX;
break;
case 0x80000000:
EAX = 0x80000005;
break;
case 0x80000001:
EAX = CPUID;
EDX = CPUID_FPU | CPUID_TSC | CPUID_MSR;
if (cpu_has_feature(CPU_FEATURE_CX8))
EDX |= CPUID_CMPXCHG8B;
if (msr.fcr & (1 << 9))
EDX |= CPUID_MMX;
#ifdef USE_NEW_DYNAREC
if (cpu_has_feature(CPU_FEATURE_3DNOW))
EDX |= CPUID_3DNOW;
#endif
break;
case 0x80000002: /*Processor name string*/
EAX = 0x20414956; /*VIA Samuel*/
EBX = 0x756d6153;
ECX = 0x00006c65;
EDX = 0x00000000;
break;
case 0x80000005: /*Cache information*/
EBX = 0x08800880; /*TLBs*/
ECX = 0x40040120; /*L1 data cache*/
EDX = 0x40020120; /*L1 instruction cache*/
break;
default:
EAX = EBX = ECX = EDX = 0;
break;
}
break;
}
}
@@ -2295,11 +2410,11 @@ void cpu_ven_reset(void)
case CPU_K6:
amd_efer = amd_whcr = 0ULL;
break;
#ifdef USE_NEW_DYNAREC
case CPU_K6_2:
amd_efer = amd_whcr = 0ULL;
star = 0ULL;
break;
#ifdef USE_NEW_DYNAREC
case CPU_K6_2C:
amd_efer = 2ULL;
amd_whcr = star = 0ULL;
@@ -2364,6 +2479,36 @@ void cpu_RDMSR()
}
break;
case CPU_CYRIX3S:
EAX = EDX = 0;
switch (ECX)
{
case 0x02:
EAX = msr.tr1;
break;
case 0x0e:
EAX = msr.tr12;
break;
case 0x10:
EAX = tsc & 0xffffffff;
EDX = tsc >> 32;
break;
case 0x11:
EAX = msr.cesr;
break;
case 0x1107:
EAX = msr.fcr;
break;
case 0x108:
EAX = msr.fcr2 & 0xffffffff;
EDX = msr.fcr2 >> 32;
break;
case 0x10a:
EAX = cpu_multi & 3;
break;
}
break;
#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K))
case CPU_K5:
case CPU_5K86:
@@ -2778,6 +2923,50 @@ void cpu_WRMSR()
cpu_features |= CPU_FEATURE_3DNOW;
else
cpu_features &= ~CPU_FEATURE_3DNOW;
#endif
if (EAX & (1 << 29))
CPUID = 0;
else
CPUID = machines[machine].cpu[cpu_manufacturer].cpus[cpu].cpuid_model;
break;
case 0x108:
msr.fcr2 = EAX | ((uint64_t)EDX << 32);
break;
case 0x109:
msr.fcr3 = EAX | ((uint64_t)EDX << 32);
break;
}
break;
case CPU_CYRIX3S:
switch (ECX)
{
case 0x02:
msr.tr1 = EAX & 2;
break;
case 0x0e:
msr.tr12 = EAX & 0x228;
break;
case 0x10:
tsc = EAX | ((uint64_t)EDX << 32);
break;
case 0x11:
msr.cesr = EAX & 0xff00ff;
break;
case 0x1107:
msr.fcr = EAX;
if (EAX & (1 << 9))
cpu_features |= CPU_FEATURE_MMX;
else
cpu_features &= ~CPU_FEATURE_MMX;
if (EAX & (1 << 1))
cpu_features |= CPU_FEATURE_CX8;
else
cpu_features &= ~CPU_FEATURE_CX8;
#ifdef USE_NEW_DYNAREC
if (EAX & (1 << 20))
cpu_features |= CPU_FEATURE_3DNOW;
else
cpu_features &= ~CPU_FEATURE_3DNOW;
#endif
if (EAX & (1 << 29))
CPUID = 0;

2
src/cpu_common/cpu.h
View File

@@ -76,6 +76,7 @@ enum {
CPU_K6_2P,
CPU_K6_3P,
#endif
CPU_CYRIX3S,
#if defined(DEV_BRANCH) && defined(USE_I686)
CPU_PENTIUMPRO, /* 686 class CPUs */
CPU_PENTIUM2,
@@ -152,6 +153,7 @@ extern CPU cpus_6x86[];
#ifdef USE_NEW_DYNAREC
extern CPU cpus_6x86SS7[];
#endif
extern CPU cpus_Cyrix3[];
#if defined(DEV_BRANCH) && defined(USE_I686)
extern CPU cpus_PentiumPro[];
extern CPU cpus_PentiumII[];

18
src/cpu_common/cpu_table.c
View File

@@ -714,6 +714,24 @@ CPU cpus_PentiumII[] = {
{"Pentium II Deschutes 400", CPU_PENTIUM2D, 400000000, 4, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36,36,12,12, 48},
{"Pentium II Deschutes 450", CPU_PENTIUM2D, 450000000, 9/2, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41,41,14,14, 54},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
#endif
#endif
CPU cpus_Cyrix3[] = {
/*VIA Cyrix III (Samuel)*/
{"Cyrix III 66", CPU_CYRIX3S, 66666666, 1, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 8}, /*66 MHz version*/
{"Cyrix III 233", CPU_CYRIX3S, 233333333, 7/2, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 9, 9, 28},
{"Cyrix III 266", CPU_CYRIX3S, 266666666, 4, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 32},
{"Cyrix III 300", CPU_CYRIX3S, 300000000, 9/2, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 27, 27, 13, 13, 36},
{"Cyrix III 333", CPU_CYRIX3S, 333333333, 5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 30, 30, 15, 15, 40},
{"Cyrix III 350", CPU_CYRIX3S, 350000000, 7/2, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 32, 32, 11, 11, 42},
{"Cyrix III 400", CPU_CYRIX3S, 400000000, 4, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 36, 36, 12, 12, 48},
{"Cyrix III 450", CPU_CYRIX3S, 450000000, 9/2, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 41, 41, 14, 14, 54}, /*^ is lower P2 speeds to allow emulation below 466 mhz*/
{"Cyrix III 500", CPU_CYRIX3S, 500000000, 5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 45, 45, 15, 15, 60},
{"Cyrix III 550", CPU_CYRIX3S, 550000000, 11/2, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 50, 50, 17, 17, 66},
{"Cyrix III 600", CPU_CYRIX3S, 600000000, 6, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 54, 54, 18, 18, 72},
{"Cyrix III 650", CPU_CYRIX3S, 650000000, 13/2, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 58, 58, 20, 20, 78},
{"Cyrix III 700", CPU_CYRIX3S, 700000000, 7, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 62, 62, 21, 21, 84},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};

7
src/machine/m_at_socket8.c
View File

@@ -102,7 +102,7 @@ machine_at_s1668_init(const machine_t *model)
return ret;
}
#endif
int
machine_at_6abx3_init(const machine_t *model)
{
@@ -131,10 +131,7 @@ machine_at_6abx3_init(const machine_t *model)
// device_add(&w83977tf_device);
// device_add(&intel_flash_bxt_device);
// device_add(&sst_flash_29ee020_device);
device_add(&sst_flash_39sf020_device);
device_add(&intel_flash_bxt_device);
return ret;
}
#endif

3
src/machine/machine.h
View File

@@ -304,9 +304,10 @@ extern const device_t *at_pb640_get_device(void);
#if defined(DEV_BRANCH) && defined(USE_I686)
extern int machine_at_i440fx_init(const machine_t *);
extern int machine_at_s1668_init(const machine_t *);
#endif
extern int machine_at_6abx3_init(const machine_t *);
#endif
/* m_at_t3100e.c */
extern int machine_at_t3100e_init(const machine_t *);

5
src/machine/machine_table.c
View File

@@ -61,7 +61,6 @@
#define MACHINE_CPUS_PENTIUM_SS7 MACHINE_CPUS_PENTIUM_S7
#endif
const machine_t machines[] = {
{ "[8088] AMI XT clone", "amixt", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA, 64, 640, 64, 0, machine_xt_amixt_init, NULL },
{ "[8088] Compaq Portable", "portable", {{"Intel", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VIDEO, 128, 640, 128, 0, machine_xt_compaq_init, NULL },
@@ -237,7 +236,9 @@ const machine_t machines[] = {
{ "[Socket 8 FX] Tyan Titan-Pro AT", "440fx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 127, machine_at_i440fx_init, NULL },
{ "[Socket 8 FX] Tyan Titan-Pro ATX", "tpatx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 127, machine_at_s1668_init, NULL },
{ "[Slot 1 BX] Lucky Star 6ABX3", "6abx3", {{"Intel", cpus_PentiumII}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_6abx3_init, NULL },
{ "[Slot 1 BX] Lucky Star 6ABX3", "6abx3", {{"Intel", cpus_PentiumII}, {"VIA", cpus_Cyrix3},{"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_6abx3_init, NULL },
#else
{ "[Slot 1 BX] Lucky Star 6ABX3", "6abx3", {{"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_6abx3_init, NULL },
#endif
{ NULL, NULL, {{"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}}, 0, 0, 0, 0, 0, NULL, NULL }
};

4
src/win/Makefile.mingw
View File

@@ -478,7 +478,6 @@ endif
ifeq ($(I686), y)
OPTS += -DUSE_I686
DEVBROBJ += m_at_socket8.o
endif
ifeq ($(LASERXT), y)
@@ -595,7 +594,8 @@ MCHOBJ := machine.o machine_table.o \
m_ps2_isa.o m_ps2_mca.o \
m_at_compaq.o \
m_at_286_386sx.o m_at_386dx_486.o \
m_at_socket4_5.o m_at_socket7_s7.o
m_at_socket4_5.o m_at_socket7_s7.o \
m_at_socket8.o
DEVOBJ := bugger.o ibm_5161.o isamem.o isartc.o lpt.o $(SERIAL) \
sio_acc3221.o \

4
src/win/Makefile_ndr.mingw
View File

@@ -484,7 +484,6 @@ endif
ifeq ($(I686), y)
OPTS += -DUSE_I686
DEVBROBJ += m_at_socket8.o
endif
ifeq ($(LASERXT), y)
@@ -600,7 +599,8 @@ MCHOBJ := machine.o machine_table.o \
m_ps2_isa.o m_ps2_mca.o \
m_at_compaq.o \
m_at_286_386sx.o m_at_386dx_486.o \
m_at_socket4_5.o m_at_socket7_s7.o
m_at_socket4_5.o m_at_socket7_s7.o \
m_at_socket8.o
DEVOBJ := bugger.o ibm_5161.o isamem.o isartc.o lpt.o $(SERIAL) \
sio_acc3221.o \