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ATAPI CD-ROM no longer lowers IRQ at the wrong time, fixes booting of some CD's;

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Fixed DMA emulation, fixes Olivetti M24;
(S)VGA emulation for PS/1 and PS/2 machines now uses the old, less accurate sense switches, fixes display error on POST;
Bit 2 of the AT keyboard input port is now always held active, fixes PS/2 mouse on PS/1 and PS/2 machines;
Fixed mouse type selection on non-AT boards;
Fixed RAM type selection;
The entire palette is now overwritten when a monochrome monitor type is selected, fixes graphics mode on Hercules;
Applied updated SCAT emulation patch from PCem forum;
Nvidia Riva and S3 Virge IRQ is now configurable;
Properly applied the mainline PCem commit that fixed the Bahamas64 on the Intel AMI BIOS boards;
Commented out the Diamond Stealth 64 and the Miro Crystal S3 Vision 964 due to their non-working state;
Changed version to 1.06.
This commit is contained in:
OBattler
2017-03-01 23:23:52 +01:00
parent 99de4f11b6
commit 13683628a5
18 changed files with 498 additions and 125 deletions
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67
src/dma.c
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@@ -70,7 +70,8 @@ uint8_t dma_read(uint16_t addr, void *priv)
return temp;
case 0xd: /*Temporary register*/
return dmaregs[addr & 0xd];
// return dmaregs[addr & 0xd];
return 0;
case 0xf: /*Mask register*/
return dma16.m;
@@ -89,16 +90,20 @@ void dma_write(uint16_t addr, uint8_t val, void *priv)
{
case 0: case 2: case 4: case 6: /*Address registers*/
dma.wp ^= 1;
if (dma.wp) dma.ab[(addr >> 1) & 3] = (dma.ab[(addr >> 1) & 3] & 0xff00) | val;
else dma.ab[(addr >> 1) & 3] = (dma.ab[(addr >> 1) & 3] & 0x00ff) | (val << 8);
// if (dma.wp) dma.ab[(addr >> 1) & 3] = (dma.ab[(addr >> 1) & 3] & 0xff00) | val;
// else dma.ab[(addr >> 1) & 3] = (dma.ab[(addr >> 1) & 3] & 0x00ff) | (val << 8);
if (dma.wp) dma.ab[(addr >> 1) & 3] = val;
else dma.ab[(addr >> 1) & 3] |= (((uint16_t) val) << 8);
dma.ac[(addr >> 1) & 3] = dma.ab[(addr >> 1) & 3] & 0xffff;
dmaon[(addr >> 1) & 3] = 1;
return;
case 1: case 3: case 5: case 7: /*Count registers*/
dma.wp ^= 1;
if (dma.wp) dma.cb[(addr >> 1) & 3] = (dma.cb[(addr >> 1) & 3] & 0xff00) | val;
else dma.cb[(addr >> 1) & 3] = (dma.cb[(addr >> 1) & 3] & 0x00ff) | (val << 8);
// if (dma.wp) dma.cb[(addr >> 1) & 3] = (dma.cb[(addr >> 1) & 3] & 0xff00) | val;
// else dma.cb[(addr >> 1) & 3] = (dma.cb[(addr >> 1) & 3] & 0x00ff) | (val << 8);
if (dma.wp) dma.cb[(addr >> 1) & 3] = val;
else dma.cb[(addr >> 1) & 3] |= (((uint16_t) val) << 8);
dma.cc[(addr >> 1) & 3] = dma.cb[(addr >> 1) & 3] & 0xffff;
// pclog("DMA count for channel %i now: %02X\n", (addr >> 1) & 3, dma.cc[(addr >> 1) & 3]);
dmaon[(addr >> 1) & 3] = 1;
@@ -111,15 +116,11 @@ void dma_write(uint16_t addr, uint8_t val, void *priv)
case 9: /*Request register*/
if (val & 4)
{
dma.request |= (1 << (channel + 4));
if (dma.command & 1)
{
dma.request |= (1 << channel);
}
dma.stat |= (1 << (channel + 4));
}
else
{
dma.request &= ~(1 << (channel + 4));
dma.stat &= ~(1 << (channel + 4));
}
return;
@@ -138,9 +139,10 @@ void dma_write(uint16_t addr, uint8_t val, void *priv)
return;
case 0xd: /*Master clear*/
dma.wp = 0;
dma.stat = 0;
dma.m = 0xf;
dma.command = 0;
dma.stat = 0;
dma.wp = 0;
return;
case 0xe: /*Mask reset*/
@@ -178,7 +180,8 @@ uint8_t dma16_read(uint16_t addr, void *priv)
return temp;
case 0xd: /*Temporary register*/
return dma16regs[addr & 0xd];
// return dma16regs[addr & 0xd];
return 0;
case 0xf: /*Mask register*/
return dma16.m;
@@ -198,16 +201,20 @@ void dma16_write(uint16_t addr, uint8_t val, void *priv)
{
case 0: case 2: case 4: case 6: /*Address registers*/
dma16.wp ^= 1;
if (dma16.wp) dma16.ab[(addr >> 1) & 3] = (dma16.ab[(addr >> 1) & 3] & 0xff00) | val;
else dma16.ab[(addr >> 1) & 3] = (dma16.ab[(addr >> 1) & 3] & 0x00ff) | (val << 8);
// if (dma16.wp) dma16.ab[(addr >> 1) & 3] = (dma16.ab[(addr >> 1) & 3] & 0xff00) | val;
// else dma16.ab[(addr >> 1) & 3] = (dma16.ab[(addr >> 1) & 3] & 0x00ff) | (val << 8);
if (dma16.wp) dma16.ab[(addr >> 1) & 3] = val;
else dma16.ab[(addr >> 1) & 3] |= (((uint16_t) val) << 8);
dma16.ac[(addr >> 1) & 3] = dma16.ab[(addr >> 1) & 3] & 0xffff;
dma16on[(addr >> 1) & 3] = 1;
return;
case 1: case 3: case 5: case 7: /*Count registers*/
dma16.wp ^= 1;
if (dma16.wp) dma16.cb[(addr >> 1) & 3] = (dma16.cb[(addr >> 1) & 3] & 0xff00) | val;
else dma16.cb[(addr >> 1) & 3] = (dma16.cb[(addr >> 1) & 3] & 0x00ff) | (val << 8);
// if (dma16.wp) dma16.cb[(addr >> 1) & 3] = (dma16.cb[(addr >> 1) & 3] & 0xff00) | val;
// else dma16.cb[(addr >> 1) & 3] = (dma16.cb[(addr >> 1) & 3] & 0x00ff) | (val << 8);
if (dma16.wp) dma16.cb[(addr >> 1) & 3] = val;
else dma16.cb[(addr >> 1) & 3] |= (((uint16_t) val) << 8);
dma16.cc[(addr >> 1) & 3] = dma16.cb[(addr >> 1) & 3] & 0xffff;
dma16on[(addr >> 1) & 3] = 1;
return;
@@ -219,15 +226,11 @@ void dma16_write(uint16_t addr, uint8_t val, void *priv)
case 9: /*Request register*/
if (val & 4)
{
dma16.request |= (1 << (channel + 4));
if (dma16.command & 1)
{
dma16.request |= (1 << channel);
}
dma16.stat |= (1 << (channel + 4));
}
else
{
dma16.request &= ~(1 << (channel + 4));
dma16.stat &= ~(1 << (channel + 4));
}
return;
@@ -246,9 +249,10 @@ void dma16_write(uint16_t addr, uint8_t val, void *priv)
return;
case 0xd: /*Master clear*/
dma16.wp = 0;
dma16.stat = 0;
dma16.m = 0xf;
dma16.command = 0;
dma16.stat = 0;
dma16.wp = 0;
return;
case 0xe: /*Mask reset*/
@@ -278,10 +282,7 @@ void dma_page_write(uint16_t addr, uint8_t val, void *priv)
dma.page[1] = (AT) ? val : val & 0xf;
break;
case 0x7:
if (is386)
{
dma.page[0] = (AT) ? val : val & 0xf;
}
dma.page[0] = (AT) ? val : val & 0xf;
break;
case 0x9:
dma16.page[2] = val;
@@ -292,6 +293,12 @@ void dma_page_write(uint16_t addr, uint8_t val, void *priv)
case 0xb:
dma16.page[1] = val;
break;
case 0xf:
dma16.page[0] = val;
break;
default:
pclog("DMA write to extra page register: %02X\n", addr & 0xf);
break;
}
}