claunia/86Box
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

ATAPI CD-ROM no longer lowers IRQ at the wrong time, fixes booting of some CD's;

Browse Source 
Fixed DMA emulation, fixes Olivetti M24;
(S)VGA emulation for PS/1 and PS/2 machines now uses the old, less accurate sense switches, fixes display error on POST;
Bit 2 of the AT keyboard input port is now always held active, fixes PS/2 mouse on PS/1 and PS/2 machines;
Fixed mouse type selection on non-AT boards;
Fixed RAM type selection;
The entire palette is now overwritten when a monochrome monitor type is selected, fixes graphics mode on Hercules;
Applied updated SCAT emulation patch from PCem forum;
Nvidia Riva and S3 Virge IRQ is now configurable;
Properly applied the mainline PCem commit that fixed the Bahamas64 on the Intel AMI BIOS boards;
Commented out the Diamond Stealth 64 and the Miro Crystal S3 Vision 964 due to their non-working state;
Changed version to 1.06.
This commit is contained in:
OBattler
2017-03-01 23:23:52 +01:00
parent 99de4f11b6
commit 13683628a5
18 changed files with 498 additions and 125 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/86box.h
View File

@@ -1,4 +1,4 @@
/* Copyright holders: Tenshi
see COPYING for more details
*/
#define emulator_version "1.10"
#define emulator_version "1.06"

10
src/cdrom.c
View File

@@ -2745,14 +2745,6 @@ int cdrom_block_check(uint8_t id)
int alloc_length = 0;
int ret = 0;
if (!cdrom_drives[id].bus_type)
{
cdrom_log("CD-ROM %i: Lowering IDE IRQ\n", id);
ide_irq_lower(&(ide_drives[cdrom_drives[id].ide_channel]));
}
cdrom[id].status = BUSY_STAT;
/* If this is a media access command, and we hit the end of the block but not the entire length,
read the next block. */
if (cdrom_is_media_access(id))
@@ -2808,7 +2800,6 @@ void cdrom_callback(uint8_t id) /* Callback for non-Read CD commands */
int ret = 0;
int old_pos = 0;
#if 0
if (!cdrom_drives[id].bus_type)
{
cdrom_log("CD-ROM %i: Lowering IDE IRQ\n", id);
@@ -2816,7 +2807,6 @@ void cdrom_callback(uint8_t id) /* Callback for non-Read CD commands */
}
cdrom[id].status = BUSY_STAT;
#endif
if (cdrom[id].total_read >= cdrom[id].packet_len)
{

65
src/dma.c
View File

@@ -70,7 +70,8 @@ uint8_t dma_read(uint16_t addr, void *priv)
return temp;
case 0xd: /*Temporary register*/
return dmaregs[addr & 0xd];
// return dmaregs[addr & 0xd];
return 0;
case 0xf: /*Mask register*/
return dma16.m;
@@ -89,16 +90,20 @@ void dma_write(uint16_t addr, uint8_t val, void *priv)
{
case 0: case 2: case 4: case 6: /*Address registers*/
dma.wp ^= 1;
if (dma.wp) dma.ab[(addr >> 1) & 3] = (dma.ab[(addr >> 1) & 3] & 0xff00) | val;
else dma.ab[(addr >> 1) & 3] = (dma.ab[(addr >> 1) & 3] & 0x00ff) | (val << 8);
// if (dma.wp) dma.ab[(addr >> 1) & 3] = (dma.ab[(addr >> 1) & 3] & 0xff00) | val;
// else dma.ab[(addr >> 1) & 3] = (dma.ab[(addr >> 1) & 3] & 0x00ff) | (val << 8);
if (dma.wp) dma.ab[(addr >> 1) & 3] = val;
else dma.ab[(addr >> 1) & 3] |= (((uint16_t) val) << 8);
dma.ac[(addr >> 1) & 3] = dma.ab[(addr >> 1) & 3] & 0xffff;
dmaon[(addr >> 1) & 3] = 1;
return;
case 1: case 3: case 5: case 7: /*Count registers*/
dma.wp ^= 1;
if (dma.wp) dma.cb[(addr >> 1) & 3] = (dma.cb[(addr >> 1) & 3] & 0xff00) | val;
else dma.cb[(addr >> 1) & 3] = (dma.cb[(addr >> 1) & 3] & 0x00ff) | (val << 8);
// if (dma.wp) dma.cb[(addr >> 1) & 3] = (dma.cb[(addr >> 1) & 3] & 0xff00) | val;
// else dma.cb[(addr >> 1) & 3] = (dma.cb[(addr >> 1) & 3] & 0x00ff) | (val << 8);
if (dma.wp) dma.cb[(addr >> 1) & 3] = val;
else dma.cb[(addr >> 1) & 3] |= (((uint16_t) val) << 8);
dma.cc[(addr >> 1) & 3] = dma.cb[(addr >> 1) & 3] & 0xffff;
// pclog("DMA count for channel %i now: %02X\n", (addr >> 1) & 3, dma.cc[(addr >> 1) & 3]);
dmaon[(addr >> 1) & 3] = 1;
@@ -111,15 +116,11 @@ void dma_write(uint16_t addr, uint8_t val, void *priv)
case 9: /*Request register*/
if (val & 4)
{
dma.request |= (1 << (channel + 4));
if (dma.command & 1)
{
dma.request |= (1 << channel);
}
dma.stat |= (1 << (channel + 4));
}
else
{
dma.request &= ~(1 << (channel + 4));
dma.stat &= ~(1 << (channel + 4));
}
return;
@@ -138,9 +139,10 @@ void dma_write(uint16_t addr, uint8_t val, void *priv)
return;
case 0xd: /*Master clear*/
dma.wp = 0;
dma.stat = 0;
dma.m = 0xf;
dma.command = 0;
dma.stat = 0;
dma.wp = 0;
return;
case 0xe: /*Mask reset*/
@@ -178,7 +180,8 @@ uint8_t dma16_read(uint16_t addr, void *priv)
return temp;
case 0xd: /*Temporary register*/
return dma16regs[addr & 0xd];
// return dma16regs[addr & 0xd];
return 0;
case 0xf: /*Mask register*/
return dma16.m;
@@ -198,16 +201,20 @@ void dma16_write(uint16_t addr, uint8_t val, void *priv)
{
case 0: case 2: case 4: case 6: /*Address registers*/
dma16.wp ^= 1;
if (dma16.wp) dma16.ab[(addr >> 1) & 3] = (dma16.ab[(addr >> 1) & 3] & 0xff00) | val;
else dma16.ab[(addr >> 1) & 3] = (dma16.ab[(addr >> 1) & 3] & 0x00ff) | (val << 8);
// if (dma16.wp) dma16.ab[(addr >> 1) & 3] = (dma16.ab[(addr >> 1) & 3] & 0xff00) | val;
// else dma16.ab[(addr >> 1) & 3] = (dma16.ab[(addr >> 1) & 3] & 0x00ff) | (val << 8);
if (dma16.wp) dma16.ab[(addr >> 1) & 3] = val;
else dma16.ab[(addr >> 1) & 3] |= (((uint16_t) val) << 8);
dma16.ac[(addr >> 1) & 3] = dma16.ab[(addr >> 1) & 3] & 0xffff;
dma16on[(addr >> 1) & 3] = 1;
return;
case 1: case 3: case 5: case 7: /*Count registers*/
dma16.wp ^= 1;
if (dma16.wp) dma16.cb[(addr >> 1) & 3] = (dma16.cb[(addr >> 1) & 3] & 0xff00) | val;
else dma16.cb[(addr >> 1) & 3] = (dma16.cb[(addr >> 1) & 3] & 0x00ff) | (val << 8);
// if (dma16.wp) dma16.cb[(addr >> 1) & 3] = (dma16.cb[(addr >> 1) & 3] & 0xff00) | val;
// else dma16.cb[(addr >> 1) & 3] = (dma16.cb[(addr >> 1) & 3] & 0x00ff) | (val << 8);
if (dma16.wp) dma16.cb[(addr >> 1) & 3] = val;
else dma16.cb[(addr >> 1) & 3] |= (((uint16_t) val) << 8);
dma16.cc[(addr >> 1) & 3] = dma16.cb[(addr >> 1) & 3] & 0xffff;
dma16on[(addr >> 1) & 3] = 1;
return;
@@ -219,15 +226,11 @@ void dma16_write(uint16_t addr, uint8_t val, void *priv)
case 9: /*Request register*/
if (val & 4)
{
dma16.request |= (1 << (channel + 4));
if (dma16.command & 1)
{
dma16.request |= (1 << channel);
}
dma16.stat |= (1 << (channel + 4));
}
else
{
dma16.request &= ~(1 << (channel + 4));
dma16.stat &= ~(1 << (channel + 4));
}
return;
@@ -246,9 +249,10 @@ void dma16_write(uint16_t addr, uint8_t val, void *priv)
return;
case 0xd: /*Master clear*/
dma16.wp = 0;
dma16.stat = 0;
dma16.m = 0xf;
dma16.command = 0;
dma16.stat = 0;
dma16.wp = 0;
return;
case 0xe: /*Mask reset*/
@@ -278,10 +282,7 @@ void dma_page_write(uint16_t addr, uint8_t val, void *priv)
dma.page[1] = (AT) ? val : val & 0xf;
break;
case 0x7:
if (is386)
{
dma.page[0] = (AT) ? val : val & 0xf;
}
break;
case 0x9:
dma16.page[2] = val;
@@ -292,6 +293,12 @@ void dma_page_write(uint16_t addr, uint8_t val, void *priv)
case 0xb:
dma16.page[1] = val;
break;
case 0xf:
dma16.page[0] = val;
break;
default:
pclog("DMA write to extra page register: %02X\n", addr & 0xf);
break;
}
}

9
src/keyboard_at.c
View File

@@ -642,9 +642,7 @@ bad_command:
break;
case 0xc0: /*Read input port*/
keyboard_at_adddata((keyboard_at.input_port & 0xf0) | 0x80);
// keyboard_at_adddata(keyboard_at.input_port | 4);
// keyboard_at.input_port = ((keyboard_at.input_port + 1) & 3) | (keyboard_at.input_port & 0xfc);
keyboard_at_adddata((keyboard_at.input_port & 0xfc) | 0x84);
break;
case 0xc1: /*Copy bits 0 to 3 of input port to status bits 4 to 7*/
@@ -726,13 +724,16 @@ uint8_t keyboard_at_read(uint16_t port, void *priv)
case 0x60:
temp = keyboard_at.out;
keyboard_at.status &= ~(STAT_OFULL/* | STAT_MFULL*/);
picintc(keyboard_at.last_irq);
if (PCI)
{
/* The PIIX/PIIX3 datasheet mandates that both of these interrupts are cleared on any read of port 0x60. */
picintc(1 << 1);
picintc(1 << 12);
}
else
{
picintc(keyboard_at.last_irq);
}
keyboard_at.last_irq = 0;
break;

108
src/mem.c
View File

@@ -62,6 +62,8 @@ int cachesize=256;
uint8_t *ram,*rom;
uint8_t romext[32768];
uint32_t ram_mapped_addr[64];
static void mem_load_xtide_bios()
{
FILE *f;
@@ -351,7 +353,10 @@ int loadbios()
}
fclose(ff);
fclose(f);
if (enable_xtide)
{
mem_load_atide_bios();
}
return 1;
case ROM_CMDPC30:
f = romfopen("roms/cmdpc30/commodore pc 30 iii even.bin", "rb");
@@ -592,7 +597,10 @@ int loadbios()
fclose(f);
//#endif
biosmask = 0x1ffff;
if (enable_xtide)
{
mem_load_atide115_bios();
}
return 1;
case ROM_IBMPS1_2121:
@@ -617,7 +625,10 @@ int loadbios()
fclose(ff);
fclose(f);
biosmask = 0x7fff;
if (enable_xtide)
{
mem_load_atide_bios();
}
return 1;
case ROM_AMIXT:
@@ -716,7 +727,10 @@ int loadbios()
fread(rom, 0x20000, 1, f);
fclose(f);
biosmask = 0x1ffff;
if (enable_xtide)
{
mem_load_atide_bios();
}
return 1;
case ROM_DTK486:
@@ -1241,6 +1255,12 @@ uint8_t *getpccache(uint32_t a)
{
uint32_t a2=a;
if (a2 < 0x100000 && ram_mapped_addr[a2 >> 14])
{
a = (ram_mapped_addr[a2 >> 14] & MEM_MAP_TO_SHADOW_RAM_MASK) ? a2 : (ram_mapped_addr[a2 >> 14] & ~0x3FFF) + (a2 & 0x3FFF);
return &ram[(uintptr_t)(a & 0xFFFFF000) - (uintptr_t)(a2 & ~0xFFF)];
}
if (cr0>>31)
{
pctrans=1;
@@ -1272,6 +1292,12 @@ uint32_t mem_logical_addr;
uint8_t readmembl(uint32_t addr)
{
mem_logical_addr = addr;
if (addr < 0x100000 && ram_mapped_addr[addr >> 14])
{
addr = (ram_mapped_addr[addr >> 14] & MEM_MAP_TO_SHADOW_RAM_MASK) ? addr : (ram_mapped_addr[addr >> 14] & ~0x3FFF) + (addr & 0x3FFF);
if(addr < mem_size * 1024) return ram[addr];
return 0xFF;
}
if (cr0 >> 31)
{
addr = mmutranslate_read(addr);
@@ -1288,6 +1314,12 @@ void writemembl(uint32_t addr, uint8_t val)
{
mem_logical_addr = addr;
if (addr < 0x100000 && ram_mapped_addr[addr >> 14])
{
addr = (ram_mapped_addr[addr >> 14] & MEM_MAP_TO_SHADOW_RAM_MASK) ? addr : (ram_mapped_addr[addr >> 14] & ~0x3FFF) + (addr & 0x3FFF);
if(addr < mem_size * 1024) ram[addr] = val;
return;
}
if (page_lookup[addr>>12])
{
page_lookup[addr>>12]->write_b(addr, val, page_lookup[addr>>12]);
@@ -1317,6 +1349,12 @@ uint8_t readmemb386l(uint32_t seg, uint32_t addr)
{
return ram[readlookup2[mem_logical_addr >> 12] + (mem_logical_addr & 0xFFF)];
}*/
if (addr < 0x100000 && ram_mapped_addr[addr >> 14])
{
addr = (ram_mapped_addr[addr >> 14] & MEM_MAP_TO_SHADOW_RAM_MASK) ? addr : (ram_mapped_addr[addr >> 14] & ~0x3FFF) + (addr & 0x3FFF);
if(addr < mem_size * 1024) return ram[addr];
return 0xFF;
}
if (cr0 >> 31)
{
@@ -1341,6 +1379,12 @@ void writememb386l(uint32_t seg, uint32_t addr, uint8_t val)
}
mem_logical_addr = addr = addr + seg;
if (addr < 0x100000 && ram_mapped_addr[addr >> 14])
{
addr = (ram_mapped_addr[addr >> 14] & MEM_MAP_TO_SHADOW_RAM_MASK) ? addr : (ram_mapped_addr[addr >> 14] & ~0x3FFF) + (addr & 0x3FFF);
if(addr < mem_size * 1024) ram[addr] = val;
return;
}
if (page_lookup[addr>>12])
{
page_lookup[addr>>12]->write_b(addr, val, page_lookup[addr>>12]);
@@ -1366,6 +1410,10 @@ uint16_t readmemwl(uint32_t seg, uint32_t addr)
uint32_t addr2 = mem_logical_addr = seg + addr;
if ((addr2&0xFFF)>0xFFE)
{
if (addr2 < 0x100000 && ram_mapped_addr[addr2 >> 14] && ram_mapped_addr[(addr2+1) >> 14])
{
return readmembl(seg+addr)|(readmembl(seg+addr+1)<<8);
}
if (cr0>>31)
{
if (mmutranslate_read(addr2) == 0xffffffff) return 0xffff;
@@ -1380,6 +1428,12 @@ uint16_t readmemwl(uint32_t seg, uint32_t addr)
// printf("NULL segment! rw %04X(%08X):%08X %02X %08X\n",CS,cs,cpu_state.pc,opcode,addr);
return -1;
}
if (addr2 < 0x100000 && ram_mapped_addr[addr2 >> 14])
{
addr = (ram_mapped_addr[addr2 >> 14] & MEM_MAP_TO_SHADOW_RAM_MASK) ? addr2 : (ram_mapped_addr[addr2 >> 14] & ~0x3FFF) + (addr2 & 0x3FFF);
if(addr < mem_size * 1024) return *((uint16_t *)&ram[addr]);
return 0xFFFF;
}
if (cr0>>31)
{
addr2 = mmutranslate_read(addr2);
@@ -1404,6 +1458,12 @@ void writememwl(uint32_t seg, uint32_t addr, uint16_t val)
uint32_t addr2 = mem_logical_addr = seg + addr;
if ((addr2&0xFFF)>0xFFE)
{
if (addr2 < 0x100000 && ram_mapped_addr[addr2 >> 14])
{
writemembl(seg+addr,val);
writemembl(seg+addr+1,val>>8);
return;
}
if (cr0>>31)
{
if (mmutranslate_write(addr2) == 0xffffffff) return;
@@ -1428,6 +1488,12 @@ void writememwl(uint32_t seg, uint32_t addr, uint16_t val)
// printf("NULL segment! ww %04X(%08X):%08X %02X %08X\n",CS,cs,cpu_state.pc,opcode,addr);
return;
}
if (addr2 < 0x100000 && ram_mapped_addr[addr2 >> 14])
{
addr = (ram_mapped_addr[addr2 >> 14] & MEM_MAP_TO_SHADOW_RAM_MASK) ? addr2 : (ram_mapped_addr[addr2 >> 14] & ~0x3FFF) + (addr2 & 0x3FFF);
if(addr < mem_size * 1024) *((uint16_t *)&ram[addr]) = val;
return;
}
if (page_lookup[addr2>>12])
{
page_lookup[addr2>>12]->write_w(addr2, val, page_lookup[addr2>>12]);
@@ -1464,6 +1530,10 @@ uint32_t readmemll(uint32_t seg, uint32_t addr)
uint32_t addr2 = mem_logical_addr = seg + addr;
if ((addr2&0xFFF)>0xFFC)
{
if (addr2 < 0x100000 && (ram_mapped_addr[addr2 >> 14] || ram_mapped_addr[(addr2+3) >> 14]))
{
return readmemwl(seg,addr)|(readmemwl(seg,addr+2)<<16);
}
if (cr0>>31)
{
if (mmutranslate_read(addr2) == 0xffffffff) return 0xffffffff;
@@ -1479,6 +1549,12 @@ uint32_t readmemll(uint32_t seg, uint32_t addr)
return -1;
}
if (addr2 < 0x100000 && ram_mapped_addr[addr2 >> 14])
{
addr = (ram_mapped_addr[addr2 >> 14] & MEM_MAP_TO_SHADOW_RAM_MASK) ? addr2 : (ram_mapped_addr[addr2 >> 14] & ~0x3FFF) + (addr2 & 0x3FFF);
if(addr < mem_size * 1024) return *((uint32_t *)&ram[addr]);
return 0xFFFFFFFF;
}
if (cr0>>31)
{
addr2 = mmutranslate_read(addr2);
@@ -1518,6 +1594,12 @@ void writememll(uint32_t seg, uint32_t addr, uint32_t val)
// printf("NULL segment! wl %04X(%08X):%08X %02X %08X\n",CS,cs,cpu_state.pc,opcode,addr);
return;
}
if (addr2 < 0x100000 && ram_mapped_addr[addr2 >> 14])
{
addr = (ram_mapped_addr[addr2 >> 14] & MEM_MAP_TO_SHADOW_RAM_MASK) ? addr2 : (ram_mapped_addr[addr2 >> 14] & ~0x3FFF) + (addr2 & 0x3FFF);
if(addr < mem_size * 1024) *((uint32_t *)&ram[addr]) = val;
return;
}
if (page_lookup[addr2>>12])
{
page_lookup[addr2>>12]->write_l(addr2, val, page_lookup[addr2>>12]);
@@ -1576,10 +1658,16 @@ uint64_t readmemql(uint32_t seg, uint32_t addr)
return -1;
}
if (addr2 < 0x100000 && ram_mapped_addr[addr2 >> 14])
{
addr = (ram_mapped_addr[addr2 >> 14] & MEM_MAP_TO_SHADOW_RAM_MASK) ? addr2 : (ram_mapped_addr[addr2 >> 14] & ~0x3FFF) + (addr2 & 0x3FFF);
if(addr < mem_size * 1024) return *((uint64_t *)&ram[addr]);
return -1;
}
if (cr0>>31)
{
addr2 = mmutranslate_read(addr2);
if (addr2==0xFFFFFFFF) return 0xFFFFFFFF;
if (addr2==0xFFFFFFFF) return -1;
}
addr2&=rammask;
@@ -1612,6 +1700,12 @@ void writememql(uint32_t seg, uint32_t addr, uint64_t val)
// printf("NULL segment! wl %04X(%08X):%08X %02X %08X\n",CS,cs,cpu_state.pc,opcode,addr);
return;
}
if (addr2 < 0x100000 && ram_mapped_addr[addr2 >> 14])
{
addr = (ram_mapped_addr[addr2 >> 14] & MEM_MAP_TO_SHADOW_RAM_MASK) ? addr2 : (ram_mapped_addr[addr2 >> 14] & ~0x3FFF) + (addr2 & 0x3FFF);
if(addr < mem_size * 1024) *((uint64_t *)&ram[addr]) = val;
return;
}
if (page_lookup[addr2>>12])
{
page_lookup[addr2>>12]->write_l(addr2, val, page_lookup[addr2>>12]);
@@ -2069,6 +2163,8 @@ void mem_init()
memset(page_lookup, 0, (1 << 20) * sizeof(page_t *));
memset(ram_mapped_addr, 0, 64 * sizeof(uint32_t));
for (c = 0; c < (((mem_size + 384) * 1024) >> 12); c++)
{
pages[c].mem = &ram[c << 12];
@@ -2078,7 +2174,7 @@ void mem_init()
}
memset(isram, 0, sizeof(isram));
for (c = 0; c < (mem_size / 256); c++)
for (c = 0; c < (mem_size / 64); c++)
{
isram[c] = 1;
if (c >= 0xa && c <= 0xf)
@@ -2101,7 +2197,10 @@ void mem_init()
mem_set_mem_state(0x000000, (mem_size > 640) ? 0xa0000 : mem_size * 1024, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
mem_set_mem_state(0x0c0000, 0x40000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
if (mem_size > 1024)
{
mem_set_mem_state(0x100000, (mem_size - 1024) * 1024, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
}
mem_mapping_add(&ram_low_mapping, 0x00000, (mem_size > 640) ? 0xa0000 : mem_size * 1024, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, ram, MEM_MAPPING_INTERNAL, NULL);
if (mem_size > 1024)
@@ -2156,7 +2255,7 @@ void mem_resize()
}
memset(isram, 0, sizeof(isram));
for (c = 0; c < (mem_size / 256); c++)
for (c = 0; c < (mem_size / 64); c++)
{
isram[c] = 1;
if (c >= 0xa && c <= 0xf)
@@ -2177,7 +2276,10 @@ void mem_resize()
mem_set_mem_state(0x000000, (mem_size > 640) ? 0xa0000 : mem_size * 1024, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
mem_set_mem_state(0x0c0000, 0x40000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
if (mem_size > 1024)
{
mem_set_mem_state(0x100000, (mem_size - 1024) * 1024, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
}
mem_mapping_add(&ram_low_mapping, 0x00000, (mem_size > 640) ? 0xa0000 : mem_size * 1024, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, ram, MEM_MAPPING_INTERNAL, NULL);
if (mem_size > 1024)

5
src/mem.h
View File

@@ -39,6 +39,11 @@ extern int memspeed[11];
extern int nopageerrors;
extern uint32_t biosmask;
#define MEM_MAP_TO_SHADOW_RAM_MASK 1
#define MEM_MAP_TO_RAM_ADDR_MASK 2
extern uint32_t ram_mapped_addr[64];
void mem_mapping_add(mem_mapping_t *mapping,
uint32_t base,
uint32_t size,

4
src/model.c
View File

@@ -379,6 +379,7 @@ void ps1_common_init()
device_add(&ps1_audio_device);
/*PS/1 audio uses ports 200h and 202-207h, so only initialise gameport on 201h*/
if (joystick_type != 7) device_add(&gameport_201_device);
fdc_set_ps1();
}
void ps1_m2011_init()
@@ -391,7 +392,6 @@ void ps1_m2121_init()
{
ps1_common_init();
ps1mb_m2121_init();
fdc_set_ps1();
}
void ps2_m30_286_init()
@@ -403,11 +403,11 @@ void ps2_m30_286_init()
dma16_init();
ide_init();
keyboard_at_init();
mouse_ps2_init();
nvr_init();
pic2_init();
ps2board_init();
fdc_set_dskchg_activelow();
fdc_set_ps1();
}
void at_neat_init()

3
src/ps1.c
View File

@@ -129,6 +129,8 @@ void ps1mb_init()
io_sethandler(0x0322, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
io_sethandler(0x0324, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
if (!enable_xtide)
{
rom_init(&ps1_high_rom,
"roms/ibmps1es/f80000_shell.bin",
0xf80000,
@@ -136,6 +138,7 @@ void ps1mb_init()
0x7ffff,
0,
MEM_MAPPING_EXTERNAL);
}
/* rom_init_interleaved(&ps1_high_rom,
"roms/ibmps1es/ibm_1057757_24-05-90.bin",
"roms/ibmps1es/ibm_1057757_29-15-90.bin",

53
src/scat.c
View File

@@ -22,10 +22,18 @@ void scat_shadow_state_update()
{
int i, val, val2;
// TODO - Segment A000 to BFFF shadow ram enable features and ROM enable features should be implemented later.
for (i = 8; i < 24; i++)
for (i = 0; i < 24; i++)
{
val = ((scat_regs[SCAT_SHADOW_RAM_ENABLE_1 + (i >> 3)] >> (i & 7)) & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTERNAL;
if((scat_regs[SCAT_SHADOW_RAM_ENABLE_1 + (i >> 3)] >> (i & 7)) & 1)
{
val = MEM_READ_INTERNAL;
ram_mapped_addr[i + 40] |= 1;
}
else
{
val = MEM_READ_EXTERNAL;
ram_mapped_addr[i + 40] &= ~1;
}
if (i < 8)
{
val |= ((scat_regs[SCAT_SHADOW_RAM_ENABLE_1 + (i >> 3)] >> (i & 7)) & 1) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTERNAL;
@@ -123,6 +131,7 @@ void scat_set_xms_bound(uint8_t val)
uint32_t get_scat_addr(uint32_t addr, scat_t *p)
{
uint32_t addr2 = addr;
if (p && (scat_regs[SCAT_EMS_CONTROL] & 0x80) && (p->regs_2x9 & 0x80))
{
addr = (addr & 0x3fff) | (((p->regs_2x9 & 3) << 8) | p->regs_2x8) << 14;
@@ -222,6 +231,16 @@ void scat_write(uint16_t port, uint8_t val, void *priv)
pclog("Write SCAT EMS Control Port %04X to %02X at %04X:%04X\n", port, val, CS, cpu_state.pc);
index = scat_ems_reg_2xA & 0x1F;
scat_stat[index].regs_2x8 = val;
base_addr = (index + 16) << 14;
if(index >= 24)
base_addr += 0x30000;
if(scat_stat[index].regs_2x9 & 0x80)
{
ram_mapped_addr[base_addr >> 14] &= 0xFFC000FF;
ram_mapped_addr[base_addr >> 14] |= val << 14;
flushmmucache();
}
}
break;
case 0x209:
@@ -234,18 +253,18 @@ void scat_write(uint16_t port, uint8_t val, void *priv)
if(index >= 24)
base_addr += 0x30000;
ram_mapped_addr[base_addr >> 14] &= 1;
if (val & 0x80)
{
virt_addr = (((scat_stat[index].regs_2x9 & 3) << 8) | scat_stat[index].regs_2x8) << 14;
mem_mapping_enable(&scat_mapping[index]);
mem_mapping_set_exec(&scat_mapping[index], ram + get_scat_addr(virt_addr, &scat_stat[index]));
pclog("Map page %d(address %05X) to address %06X\n", scat_ems_reg_2xA & 0x1f, base_addr, virt_addr);
ram_mapped_addr[base_addr >> 14] |= virt_addr | 2;
}
else
{
mem_mapping_disable(&scat_mapping[index]);
pclog("Unmap page %d(address %06X)\n", scat_ems_reg_2xA & 0x1f, base_addr);
}
flushmmucache();
if (scat_ems_reg_2xA & 0x80)
{
@@ -267,6 +286,16 @@ void scat_write(uint16_t port, uint8_t val, void *priv)
pclog("Write SCAT EMS Control Port %04X to %02X at %04X:%04X\n", port, val, CS, cpu_state.pc);
index = scat_ems_reg_2xA & 0x1F;
scat_stat[index].regs_2x8 = val;
base_addr = (index + 16) << 14;
if(index >= 24)
base_addr += 0x30000;
if(scat_stat[index].regs_2x9 & 0x80)
{
ram_mapped_addr[base_addr >> 14] &= 0xFFC000FF;
ram_mapped_addr[base_addr >> 14] |= val << 14;
flushmmucache();
}
}
break;
case 0x219:
@@ -282,15 +311,14 @@ void scat_write(uint16_t port, uint8_t val, void *priv)
if (val & 0x80)
{
virt_addr = (((scat_stat[index].regs_2x9 & 3) << 8) | scat_stat[index].regs_2x8) << 14;
mem_mapping_enable(&scat_mapping[index]);
mem_mapping_set_exec(&scat_mapping[index], ram + get_scat_addr(virt_addr, &scat_stat[index]));
pclog("Map page %d(address %05X) to address %06X\n", scat_ems_reg_2xA & 0x1f, base_addr, virt_addr);
ram_mapped_addr[base_addr >> 14] |= virt_addr | 2;
}
else
{
mem_mapping_disable(&scat_mapping[index]);
pclog("Unmap page %d(address %05X)\n", scat_ems_reg_2xA & 0x1f, base_addr);
}
flushmmucache();
if (scat_ems_reg_2xA & 0x80)
{
@@ -454,6 +482,11 @@ void scat_init()
scat_regs[i] = 0xff;
}
for (i = 0; i < 64; i++)
{
ram_mapped_addr[i] = 0;
}
scat_regs[SCAT_DMA_WAIT_STATE_CONTROL] = 0;
scat_regs[SCAT_VERSION] = 10;
scat_regs[SCAT_CLOCK_CONTROL] = 2;
@@ -473,8 +506,6 @@ void scat_init()
{
scat_stat[i].regs_2x8 = 0xff;
scat_stat[i].regs_2x9 = 0x03;
mem_mapping_add(&scat_mapping[i], (i + (i >= 24 ? 28 : 16)) << 14, 0x04000, mem_read_scatems, mem_read_scatemsw, mem_read_scatemsl, mem_write_scatems, mem_write_scatemsw, mem_write_scatemsl, ram + ((i + (i >= 24 ? 28 : 16)) << 14), 0, &scat_stat[i]);
mem_mapping_disable(&scat_mapping[i]);
}
// TODO - Only normal CPU accessing address FF0000 to FFFFFF mapped to ROM. Normal CPU accessing address FC0000 to FEFFFF map to ROM should be implemented later.

176
src/vid_nv_riva128.c
View File

@@ -457,8 +457,7 @@ static void riva128_pmc_interrupt(int num, void *p)
riva128->pmc.intr |= (1 << num);
// picint(1 << riva128->pci_regs[0x3c]);
picint(1 << 3);
picint(1 << riva128->pci_regs[0x3c]);
}
static uint8_t riva128_pbus_read(uint32_t addr, void *p)
@@ -2379,8 +2378,7 @@ static uint8_t riva128_pci_read(int func, int addr, void *p)
break;
case 0x3c:
// ret = riva128->pci_regs[0x3c];
ret = 0x03;
ret = riva128->pci_regs[0x3c];
break;
case 0x3d:
@@ -2522,9 +2520,9 @@ static void riva128_pci_write(int func, int addr, uint8_t val, void *p)
}
return;
case 0x3c:
/* case 0x3c:
riva128->pci_regs[0x3c] = val & 0x0f;
return;
return; */
case 0x40:
case 0x41:
@@ -2631,9 +2629,9 @@ static void rivatnt_pci_write(int func, int addr, uint8_t val, void *p)
}
return;
case 0x3c:
/* case 0x3c:
riva128->pci_regs[0x3c] = val & 0x0f;
return;
return; */
case 0x40:
case 0x41:
@@ -2798,7 +2796,7 @@ static void *riva128_init()
riva128->pci_regs[0x32] = 0x0c;
riva128->pci_regs[0x33] = 0x00;
//riva128->pci_regs[0x3c] = 3;
riva128->pci_regs[0x3c] = device_get_config_int("irq");
riva128->pmc.intr = 0;
riva128->pbus.intr = 0;
@@ -2942,6 +2940,58 @@ static device_config_t riva128zx_config[] =
},
.default_int = 4
},
{
.name = "irq",
.description = "IRQ",
.type = CONFIG_SELECTION,
.selection =
{
{
.description = "IRQ 3",
.value = 3
},
{
.description = "IRQ 4",
.value = 4
},
{
.description = "IRQ 5",
.value = 5
},
{
.description = "IRQ 7",
.value = 7
},
{
.description = "IRQ 9",
.value = 9
},
{
.description = "IRQ 10",
.value = 10
},
{
.description = "IRQ 11",
.value = 11
},
{
.description = "IRQ 12",
.value = 12
},
{
.description = "IRQ 14",
.value = 14
},
{
.description = "IRQ 15",
.value = 15
},
{
.description = ""
}
},
.default_int = 3
},
{
.type = -1
}
@@ -3020,7 +3070,7 @@ static void *rivatnt_init()
riva128->pci_regs[0x32] = 0x0c;
riva128->pci_regs[0x33] = 0x00;
//riva128->pci_regs[0x3c] = 3;
riva128->pci_regs[0x3c] = device_get_config_int("irq");
riva128->pmc.intr = 0;
riva128->pbus.intr = 0;
@@ -3108,6 +3158,58 @@ static device_config_t rivatnt_config[] =
},
.default_int = 16
},
{
.name = "irq",
.description = "IRQ",
.type = CONFIG_SELECTION,
.selection =
{
{
.description = "IRQ 3",
.value = 3
},
{
.description = "IRQ 4",
.value = 4
},
{
.description = "IRQ 5",
.value = 5
},
{
.description = "IRQ 7",
.value = 7
},
{
.description = "IRQ 9",
.value = 9
},
{
.description = "IRQ 10",
.value = 10
},
{
.description = "IRQ 11",
.value = 11
},
{
.description = "IRQ 12",
.value = 12
},
{
.description = "IRQ 14",
.value = 14
},
{
.description = "IRQ 15",
.value = 15
},
{
.description = ""
}
},
.default_int = 3
},
{
.type = -1
}
@@ -3199,7 +3301,7 @@ static void *rivatnt2_init()
riva128->pci_regs[0x32] = 0x0c;
riva128->pci_regs[0x33] = 0x00;
//riva128->pci_regs[0x3c] = 3;
riva128->pci_regs[0x3c] = device_get_config_int("irq");
riva128->pmc.intr = 0;
riva128->pbus.intr = 0;
@@ -3312,6 +3414,58 @@ static device_config_t rivatnt2_config[] =
},
.default_int = 32
},
{
.name = "irq",
.description = "IRQ",
.type = CONFIG_SELECTION,
.selection =
{
{
.description = "IRQ 3",
.value = 3
},
{
.description = "IRQ 4",
.value = 4
},
{
.description = "IRQ 5",
.value = 5
},
{
.description = "IRQ 7",
.value = 7
},
{
.description = "IRQ 9",
.value = 9
},
{
.description = "IRQ 10",
.value = 10
},
{
.description = "IRQ 11",
.value = 11
},
{
.description = "IRQ 12",
.value = 12
},
{
.description = "IRQ 14",
.value = 14
},
{
.description = "IRQ 15",
.value = 15
},
{
.description = ""
}
},
.default_int = 3
},
{
.type = -1
}

2
src/vid_olivetti_m24.c
View File

@@ -160,7 +160,7 @@ void m24_poll(void *p)
m24->sc = (m24->sc << 1) & 7;
if (m24->dispon)
{
pclog("dispon %i\n", m24->linepos);
// pclog("dispon %i\n", m24->linepos);
if (m24->displine < m24->firstline)
{
m24->firstline = m24->displine;

41
src/vid_s3.c
View File

@@ -20,7 +20,7 @@
enum
{
S3_VISION864,
S3_VISION964,
/* S3_VISION964, */
S3_TRIO32,
S3_TRIO64
};
@@ -71,7 +71,7 @@ typedef struct s3_t
svga_t svga;
sdac_ramdac_t ramdac;
bt485_ramdac_t bt485_ramdac;
// bt485_ramdac_t bt485_ramdac;
uint8_t bank;
uint8_t ma_ext;
@@ -789,11 +789,11 @@ void s3_out(uint16_t addr, uint8_t val, void *p)
case 0x3C6: case 0x3C7: case 0x3C8: case 0x3C9:
// pclog("Write RAMDAC %04X %02X %04X:%04X\n", addr, val, CS, pc);
if (s3->chip != S3_VISION964)
/* if (s3->chip != S3_VISION964) */
sdac_ramdac_out(addr, val, &s3->ramdac, svga);
else
/* else
bt485_ramdac_out(addr, val, &s3->bt485_ramdac, svga);
return;
return; */
case 0x3D4:
svga->crtcreg = val & 0x7f;
@@ -906,6 +906,7 @@ void s3_out(uint16_t addr, uint8_t val, void *p)
}
}
break;
#if 0
case 0x55: case 0x43:
if (s3->chip == S3_VISION964)
{
@@ -922,6 +923,7 @@ void s3_out(uint16_t addr, uint8_t val, void *p)
pclog("RS2 is now %i, RS3 is now %i\n", s3->bt485_ramdac.rs2, s3->bt485_ramdac.rs3);
}
break;
#endif
// pclog("Write CRTC R%02X %02X\n", crtcreg, val);
}
if (old != val)
@@ -960,10 +962,10 @@ uint8_t s3_in(uint16_t addr, void *p)
case 0x3c6: case 0x3c7: case 0x3c8: case 0x3c9:
// pclog("Read RAMDAC %04X %04X:%04X\n", addr, CS, pc);
if (s3->chip != S3_VISION964)
// if (s3->chip != S3_VISION964)
return sdac_ramdac_in(addr, &s3->ramdac, svga);
else
return bt485_ramdac_in(addr, &s3->bt485_ramdac, svga);
/* else
return bt485_ramdac_in(addr, &s3->bt485_ramdac, svga); */
case 0x3d4:
return svga->crtcreg;
@@ -2287,7 +2289,7 @@ static void *s3_init(char *bios_fn, int chip)
svga->crtc[0x36] = 1 | (3 << 2) | (1 << 4) | (vram_sizes[vram] << 5);
/* Set video BIOS to 32k (bit 2 = set). */
svga->crtc[0x37] = 5 | (7 << 5);
if (s3->chip == S3_VISION964) svga->crtc[0x37] |= 0xe;
// if (s3->chip == S3_VISION964) svga->crtc[0x37] |= 0xe;
s3_io_set(s3);
@@ -2315,7 +2317,7 @@ void *s3_bahamas64_init()
s3_t *s3 = s3_init("roms/bahamas64.BIN", S3_VISION864);
s3->id = 0xc0; /*Vision864P*/
s3->id_ext = s3->id_ext_pci = 0xc1;
s3->id_ext = s3->id_ext_pci = 0xc0;
s3->packed_mmio = 0;
s3->getclock = sdac_getclock;
@@ -2393,7 +2395,7 @@ void *s3_phoenix_vision864_init()
{
s3_t *s3 = s3_init("roms/86c864p.bin", S3_VISION864);
s3->id = 0xc0; /*Vision864P*/
s3->id = 0xc1; /*Vision864P*/
s3->id_ext = s3->id_ext_pci = 0xc1;
s3->packed_mmio = 0;
@@ -2408,12 +2410,12 @@ int s3_phoenix_vision864_available()
return rom_present("roms/86c864p.BIN");
}
void *s3_diamond_stealth64_init()
/* void *s3_diamond_stealth64_init()
{
s3_t *s3 = s3_init("roms/STEALT64.BIN", S3_VISION864);
svga_t *svga = &s3->svga;
s3->id = 0xc0; /*Vision864P*/
s3->id = 0xc0;
s3->id_ext = s3->id_ext_pci = 0xc1;
s3->packed_mmio = 0;
@@ -2432,7 +2434,7 @@ void *s3_miro_vision964_init()
{
s3_t *s3 = s3_init("roms/mirocrystal.VBI", S3_VISION964);
s3->id = 0xd0; /*Vision964P*/
s3->id = 0xd0;
s3->id_ext = s3->id_ext_pci = 0xd1;
s3->packed_mmio = 1;
@@ -2445,7 +2447,7 @@ void *s3_miro_vision964_init()
int s3_miro_vision964_available()
{
return rom_present("roms/mirocrystal.VBI");
}
} */
void s3_close(void *p)
{
@@ -2649,7 +2651,7 @@ static device_config_t s3_phoenix_vision864_config[] =
}
};
static device_config_t s3_diamond_stealth64_config[] =
/* static device_config_t s3_diamond_stealth64_config[] =
{
{
.name = "memory",
@@ -2720,7 +2722,6 @@ static device_config_t s3_miro_vision964_config[] =
.description = "8 MB",
.value = 8
},
/*Vision864 also supports 8 MB, however the Paradise BIOS is buggy (VESA modes don't work correctly)*/
{
.description = ""
}
@@ -2730,7 +2731,7 @@ static device_config_t s3_miro_vision964_config[] =
{
.type = -1
}
};
}; */
device_t s3_bahamas64_device =
{
@@ -2797,7 +2798,7 @@ device_t s3_phoenix_vision864_device =
s3_phoenix_vision864_config
};
device_t s3_diamond_stealth64_device =
/* device_t s3_diamond_stealth64_device =
{
"S3 Vision864 (Diamond Stealth64)",
0,
@@ -2821,4 +2822,4 @@ device_t s3_miro_vision964_device =
s3_force_redraw,
s3_add_status_info,
s3_miro_vision964_config
};
}; */

4
src/vid_s3.h
View File

@@ -6,5 +6,5 @@ device_t s3_9fx_device;
device_t s3_phoenix_trio32_device;
device_t s3_phoenix_trio64_device;
device_t s3_phoenix_vision864_device;
device_t s3_diamond_stealth64_device;
device_t s3_miro_vision964_device;
/* device_t s3_diamond_stealth64_device;
device_t s3_miro_vision964_device; */

61
src/vid_s3_virge.c
View File

@@ -3686,8 +3686,7 @@ static uint8_t s3_virge_pci_read(int func, int addr, void *p)
case 0x32: ret = virge->pci_regs[0x32]; break;
case 0x33: ret = virge->pci_regs[0x33]; break;
// case 0x3c: ret = virge->pci_regs[0x3c]; break;
case 0x3c: ret = 0x03; break;
case 0x3c: ret = virge->pci_regs[0x3c]; break;
case 0x3d: ret = 0x01; break; /*INTA*/
@@ -3749,9 +3748,9 @@ static void s3_virge_pci_write(int func, int addr, uint8_t val, void *p)
mem_mapping_disable(&virge->bios_rom.mapping);
}
return;
case 0x3c:
/* case 0x3c:
virge->pci_regs[0x3c] = val;
return;
return; */
}
}
@@ -3809,6 +3808,7 @@ static void *s3_virge_init()
virge->pci_regs[6] = 0;
virge->pci_regs[7] = 2;
virge->pci_regs[0x32] = 0x0c;
virge->pci_regs[0x3c] = device_get_config_int("irq");
virge->pci_regs[0x3d] = 1;
virge->pci_regs[0x3e] = 4;
virge->pci_regs[0x3f] = 0xff;
@@ -3903,6 +3903,7 @@ static void *s3_virge_375_init()
virge->pci_regs[6] = 0;
virge->pci_regs[7] = 2;
virge->pci_regs[0x32] = 0x0c;
virge->pci_regs[0x3c] = device_get_config_int("irq");
virge->pci_regs[0x3d] = 1;
virge->pci_regs[0x3e] = 4;
virge->pci_regs[0x3f] = 0xff;
@@ -4043,6 +4044,58 @@ static device_config_t s3_virge_config[] =
.type = CONFIG_BINARY,
.default_int = 1
},
{
.name = "irq",
.description = "IRQ",
.type = CONFIG_SELECTION,
.selection =
{
{
.description = "IRQ 3",
.value = 3
},
{
.description = "IRQ 4",
.value = 4
},
{
.description = "IRQ 5",
.value = 5
},
{
.description = "IRQ 7",
.value = 7
},
{
.description = "IRQ 9",
.value = 9
},
{
.description = "IRQ 10",
.value = 10
},
{
.description = "IRQ 11",
.value = 11
},
{
.description = "IRQ 12",
.value = 12
},
{
.description = "IRQ 14",
.value = 14
},
{
.description = "IRQ 15",
.value = 15
},
{
.description = ""
}
},
.default_int = 3
},
{
.type = -1
}

22
src/vid_svga.c
View File

@@ -382,22 +382,40 @@ uint8_t svga_in(uint16_t addr, void *p)
case 0x3C1:
return svga->attrregs[svga->attraddr];
case 0x3c2:
if ((romset == ROM_IBMPS1_2011) || (romset == ROM_IBMPS1_2121) || (romset == ROM_IBMPS2_M30_286))
{
if ((svga->vgapal[0].r + svga->vgapal[0].g + svga->vgapal[0].b) >= 0x50)
{
temp = 0;
}
else
{
temp = 0x10;
}
}
else
{
if (gfxcard == GFX_RIVA128)
{
if ((svga->vgapal[0].r + svga->vgapal[0].g + svga->vgapal[0].b) >= 0x4e)
{
temp = 0;
}
else
{
temp = 0x10;
}
}
else
{
if (svga_get_input_status_0_ss(svga))
{
temp |= 0x10;
temp = 0x10;
}
else
{
temp &= ~0x10;
temp = 0;
}
}
}
return temp;

4
src/video.c
View File

@@ -71,7 +71,7 @@ static VIDEO_CARD video_cards[] =
{"CGA", "cga", &cga_device, GFX_CGA},
{"Cirrus Logic CL-GD5429", "cl_gd5429", &gd5429_device, GFX_CL_GD5429},
{"Diamond Stealth 32 (Tseng ET4000/w32p)", "stealth32", &et4000w32p_device, GFX_ET4000W32},
{"Diamond Stealth 64 DRAM (S3 Vision864)", "stealth64d", &s3_diamond_stealth64_device,GFX_STEALTH64},
/* {"Diamond Stealth 64 DRAM (S3 Vision864)", "stealth64d", &s3_diamond_stealth64_device,GFX_STEALTH64}, */
{"Diamond Stealth 3D 2000 (S3 ViRGE)", "stealth3d_2000", &s3_virge_device, GFX_VIRGE},
{"EGA", "ega", &ega_device, GFX_EGA},
{"Chips & Technologies SuperEGA", "superega", &sega_device, GFX_SUPER_EGA},
@@ -82,7 +82,7 @@ static VIDEO_CARD video_cards[] =
{"Hercules Plus", "hercules_plus", &herculesplus_device, GFX_HERCULESPLUS},
{"Hercules InColor", "incolor", &incolor_device, GFX_INCOLOR},
{"MDA", "mda", &mda_device, GFX_MDA},
{"Miro Crystal S3 Vision964", "mc_vision964", &s3_miro_vision964_device, GFX_MIRO_VISION964},
/* {"Miro Crystal S3 Vision964", "mc_vision964", &s3_miro_vision964_device, GFX_MIRO_VISION964}, */
{"Number Nine 9FX (S3 Trio64)", "n9_9fx", &s3_9fx_device, GFX_N9_9FX},
{"nVidia RIVA 128 (Experimental)", "nv_riva128", &riva128_device, GFX_RIVA128},
{"nVidia RIVA TNT (Experimental)", "nv_rivatnt", &rivatnt_device, GFX_RIVATNT},

17
src/win-config.c
View File

@@ -33,11 +33,11 @@ static int settings_network_to_list[20], settings_list_to_network[20];
static int mouse_valid(int type, int model)
{
if ((type & MOUSE_TYPE_IF_MASK) == MOUSE_TYPE_PS2 && !(models[model].flags & MODEL_PS2))
if (((type & MOUSE_TYPE_IF_MASK) == MOUSE_TYPE_PS2) && !(models[model].flags & MODEL_PS2))
return 0;
if ((type & MOUSE_TYPE_IF_MASK) == MOUSE_TYPE_AMSTRAD && !(models[model].flags & MODEL_AMSTRAD))
if (((type & MOUSE_TYPE_IF_MASK) == MOUSE_TYPE_AMSTRAD) && !(models[model].flags & MODEL_AMSTRAD))
return 0;
if ((type & MOUSE_TYPE_IF_MASK) == MOUSE_TYPE_OLIM24 && !(models[model].flags & MODEL_OLIM24))
if (((type & MOUSE_TYPE_IF_MASK) == MOUSE_TYPE_OLIM24) && !(models[model].flags & MODEL_OLIM24))
return 0;
return 1;
}
@@ -221,13 +221,13 @@ static BOOL CALLBACK config_dlgproc(HWND hdlg, UINT message, WPARAM wParam, LPAR
h = GetDlgItem(hdlg, IDC_MEMSPIN);
SendMessage(h, UDM_SETBUDDY, (WPARAM)GetDlgItem(hdlg, IDC_MEMTEXT), 0);
SendMessage(h, UDM_SETRANGE, 0, (models[romstomodel[romset]].min_ram << 16) | models[romstomodel[romset]].max_ram);
if (!models[model].flags & MODEL_AT)
SendMessage(h, UDM_SETPOS, 0, mem_size);
else
SendMessage(h, UDM_SETPOS, 0, mem_size / 1024);
accel.nSec = 0;
accel.nInc = models[model].ram_granularity;
SendMessage(h, UDM_SETACCEL, 1, (LPARAM)&accel);
if (!(models[model].flags & MODEL_AT))
SendMessage(h, UDM_SETPOS, 0, mem_size);
else
SendMessage(h, UDM_SETPOS, 0, mem_size / 1024);
h = GetDlgItem(hdlg, IDC_CONFIGUREMOD);
if (model_getdevice(model))
@@ -339,7 +339,7 @@ static BOOL CALLBACK config_dlgproc(HWND hdlg, UINT message, WPARAM wParam, LPAR
SendMessage(h, CB_ADDSTRING, 0, (LPARAM)(LPCSTR)"7 W/S");
SendMessage(h, CB_SETCURSEL, cpu_waitstates, 0);
cpu_type = models[romstomodel[romset]].cpu[cpu_manufacturer].cpus[cpu].cpu_type;
if (cpu_type >= CPU_286 && cpu_type <= CPU_386DX)
if ((cpu_type >= CPU_286) && (cpu_type <= CPU_386DX))
EnableWindow(h, TRUE);
else
EnableWindow(h, FALSE);
@@ -355,6 +355,7 @@ static BOOL CALLBACK config_dlgproc(HWND hdlg, UINT message, WPARAM wParam, LPAR
break;
type = mouse_get_type(c);
settings_mouse_to_list[c] = d;
if (mouse_valid(type, model))

7
src/win-d3d-fs.cc
View File

@@ -111,11 +111,18 @@ void cgapal_rebuild()
{
int c;
for (c = 0; c < 256; c++)
{
pal_lookup[c] = makecol(video_6to8[cgapal[c].r], video_6to8[cgapal[c].g], video_6to8[cgapal[c].b]);
}
if ((cga_palette > 1) && (cga_palette < 8))
{
for (c = 0; c < 16; c++)
{
pal_lookup[c] = makecol(video_6to8[cgapal_mono[cga_palette - 1][c].r], video_6to8[cgapal_mono[cga_palette - 1][c].g], video_6to8[cgapal_mono[cga_palette - 1][c].b]);
pal_lookup[c + 16] = makecol(video_6to8[cgapal_mono[cga_palette - 1][c].r], video_6to8[cgapal_mono[cga_palette - 1][c].g], video_6to8[cgapal_mono[cga_palette - 1][c].b]);
pal_lookup[c + 32] = makecol(video_6to8[cgapal_mono[cga_palette - 1][c].r], video_6to8[cgapal_mono[cga_palette - 1][c].g], video_6to8[cgapal_mono[cga_palette - 1][c].b]);
pal_lookup[c + 48] = makecol(video_6to8[cgapal_mono[cga_palette - 1][c].r], video_6to8[cgapal_mono[cga_palette - 1][c].g], video_6to8[cgapal_mono[cga_palette - 1][c].b]);
}
}
if (cga_palette == 8)
{