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Finished the ALi M15xx and removed from Dev branch.

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This commit is contained in:
OBattler
2021-07-01 01:43:59 +02:00
parent fd4817a87b
commit 15279e4964
13 changed files with 236 additions and 213 deletions
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68
src/acpi.c
View File

@@ -106,7 +106,10 @@ acpi_raise_smi(void *priv, int do_smi)
if (do_smi) if (do_smi)
smi_line = 1; smi_line = 1;
/* Clear bit 16 of GLBCTL. */ /* Clear bit 16 of GLBCTL. */
if (dev->vendor == VEN_INTEL)
dev->regs.glbctl &= ~0x00010000; dev->regs.glbctl &= ~0x00010000;
else
dev->regs.ali_soft_smi = 1;
} else if (dev->vendor == VEN_SMC) { } else if (dev->vendor == VEN_SMC) {
if (do_smi) if (do_smi)
smi_line = 1; smi_line = 1;
@@ -172,8 +175,7 @@ acpi_reg_read_ali(int size, uint16_t addr, void *p)
shift16 = (addr & 1) << 3; shift16 = (addr & 1) << 3;
shift32 = (addr & 3) << 3; shift32 = (addr & 3) << 3;
switch(addr) switch(addr) {
{
case 0x10: case 0x11: case 0x12: case 0x13: case 0x10: case 0x11: case 0x12: case 0x13:
/* PCNTRL - Processor Control Register (IO) */ /* PCNTRL - Processor Control Register (IO) */
ret = (dev->regs.pcntrl >> shift16) & 0xff; ret = (dev->regs.pcntrl >> shift16) & 0xff;
@@ -196,20 +198,13 @@ acpi_reg_read_ali(int size, uint16_t addr, void *p)
break; break;
case 0x1d: case 0x1c: case 0x1d: case 0x1c:
/* GPE1_STS - General Purpose Event1 Status Register */ /* GPE1_STS - General Purpose Event1 Status Register */
ret = (dev->regs.gpsts >> shift16) & 0xff; ret = (dev->regs.gpsts1 >> shift16) & 0xff;
break; break;
case 0x1f: case 0x1e: case 0x1f: case 0x1e:
/* GPE1_EN - General Purpose Event1 Enable Register */ /* GPE1_EN - General Purpose Event1 Enable Register */
ret = (dev->regs.gpen1 >> shift16) & 0xff; ret = (dev->regs.gpen1 >> shift16) & 0xff;
break; break;
case 0x20: case 0x20 ... 0x27:
case 0x21:
case 0x22:
case 0x23:
case 0x24:
case 0x25:
case 0x26:
case 0x27:
/* GPE1_CTL - General Purpose Event1 Control Register */ /* GPE1_CTL - General Purpose Event1 Control Register */
ret = (dev->regs.gpcntrl >> shift32) & 0xff; ret = (dev->regs.gpcntrl >> shift32) & 0xff;
break; break;
@@ -221,6 +216,7 @@ acpi_reg_read_ali(int size, uint16_t addr, void *p)
ret = acpi_reg_read_common_regs(size, addr, p); ret = acpi_reg_read_common_regs(size, addr, p);
break; break;
} }
#ifdef ENABLE_ACPI_LOG #ifdef ENABLE_ACPI_LOG
if (size != 1) if (size != 1)
acpi_log("(%i) ACPI Read (%i) %02X: %02X\n", in_smm, size, addr, ret); acpi_log("(%i) ACPI Read (%i) %02X: %02X\n", in_smm, size, addr, ret);
@@ -304,6 +300,7 @@ acpi_reg_read_intel(int size, uint16_t addr, void *p)
return ret; return ret;
} }
static uint32_t static uint32_t
acpi_reg_read_sis(int size, uint16_t addr, void *p) acpi_reg_read_sis(int size, uint16_t addr, void *p)
{ {
@@ -719,20 +716,13 @@ acpi_reg_write_ali(int size, uint16_t addr, uint8_t val, void *p)
break; break;
case 0x1d: case 0x1c: case 0x1d: case 0x1c:
/* GPE1_STS - General Purpose Event1 Status Register */ /* GPE1_STS - General Purpose Event1 Status Register */
dev->regs.gpsts &= ~((val << shift16) & 0x0c01); dev->regs.gpsts1 &= ~((val << shift16) & 0x0c01);
break; break;
case 0x1f: case 0x1e: case 0x1f: case 0x1e:
/* GPE1_EN - General Purpose Event1 Enable Register */ /* GPE1_EN - General Purpose Event1 Enable Register */
dev->regs.gpen = ((dev->regs.gpen & ~(0xff << shift16)) | (val << shift16)) & 0x0c01; dev->regs.gpen1 = ((dev->regs.gpen & ~(0xff << shift16)) | (val << shift16)) & 0x0c01;
break; break;
case 0x20: case 0x20 ... 0x27:
case 0x21:
case 0x22:
case 0x23:
case 0x24:
case 0x25:
case 0x26:
case 0x27:
/* GPE1_CTL - General Purpose Event1 Control Register */ /* GPE1_CTL - General Purpose Event1 Control Register */
dev->regs.gpcntrl = ((dev->regs.gpcntrl & ~(0xff << shift32)) | (val << shift32)) & 0x00000001; dev->regs.gpcntrl = ((dev->regs.gpcntrl & ~(0xff << shift32)) | (val << shift32)) & 0x00000001;
break; break;
@@ -744,10 +734,10 @@ acpi_reg_write_ali(int size, uint16_t addr, uint8_t val, void *p)
acpi_reg_write_common_regs(size, addr, val, p); acpi_reg_write_common_regs(size, addr, val, p);
/* Setting GBL_RLS also sets BIOS_STS and generates SMI. */ /* Setting GBL_RLS also sets BIOS_STS and generates SMI. */
if ((addr == 0x00) && !(dev->regs.pmsts & 0x20)) if ((addr == 0x00) && !(dev->regs.pmsts & 0x20))
dev->regs.glbctl &= ~0x0002; dev->regs.gpcntrl &= ~0x0002;
else if ((addr == 0x04) && (dev->regs.pmcntrl & 0x0004)) { else if ((addr == 0x04) && (dev->regs.pmcntrl & 0x0004)) {
dev->regs.glbsts |= 0x01; dev->regs.gpsts1 |= 0x01;
if (dev->regs.glben & 0x02) if (dev->regs.gpen1 & 0x01)
acpi_raise_smi(dev, 1); acpi_raise_smi(dev, 1);
} }
} }
@@ -1524,29 +1514,31 @@ static void
acpi_apm_out(uint16_t port, uint8_t val, void *p) acpi_apm_out(uint16_t port, uint8_t val, void *p)
{ {
acpi_t *dev = (acpi_t *) p; acpi_t *dev = (acpi_t *) p;
uint16_t old_port = port;
acpi_log("[%04X:%08X] APM write: %04X = %02X (AX = %04X, BX = %04X, CX = %04X)\n", CS, cpu_state.pc, port, val, AX, BX, CX); acpi_log("[%04X:%08X] APM write: %04X = %02X (AX = %04X, BX = %04X, CX = %04X)\n", CS, cpu_state.pc, port, val, AX, BX, CX);
port &= 0x0001; port &= 0x0001;
if ((old_port == 0x00b1) && (dev->vendor == VEN_ALI)) { if (dev->vendor == VEN_ALI) {
pclog("ALi SOFT SMI# status set\n"); if (port == 0x0001) {
acpi_log("ALi SOFT SMI# status set (%i)\n", dev->apm->do_smi);
dev->apm->cmd = val; dev->apm->cmd = val;
dev->regs.ali_soft_smi = 1;
// acpi_raise_smi(dev, dev->apm->do_smi); // acpi_raise_smi(dev, dev->apm->do_smi);
if (dev->apm->do_smi) if (dev->apm->do_smi)
smi_line = 1; smi_line = 1;
} else if (port == 0x0000) { dev->regs.ali_soft_smi = 1;
} else if (port == 0x0003)
dev->apm->stat = val;
} else {
if (port == 0x0000) {
dev->apm->cmd = val; dev->apm->cmd = val;
if (dev->vendor != VEN_ALI) {
if (dev->vendor == VEN_INTEL) if (dev->vendor == VEN_INTEL)
dev->regs.glbsts |= 0x20; dev->regs.glbsts |= 0x20;
acpi_raise_smi(dev, dev->apm->do_smi); acpi_raise_smi(dev, dev->apm->do_smi);
}
} else } else
dev->apm->stat = val; dev->apm->stat = val;
} }
}
static uint8_t static uint8_t
@@ -1554,16 +1546,20 @@ acpi_apm_in(uint16_t port, void *p)
{ {
acpi_t *dev = (acpi_t *) p; acpi_t *dev = (acpi_t *) p;
uint8_t ret = 0xff; uint8_t ret = 0xff;
uint16_t old_port = port;
port &= 0x0001; port &= 0x0001;
if ((old_port == 0x00b1) && (dev->vendor == VEN_ALI)) if (dev->vendor == VEN_ALI) {
if (port == 0x0001)
ret = dev->apm->cmd; ret = dev->apm->cmd;
else if (port == 0x0000) else if (port == 0x0003)
ret = dev->apm->stat;
} else {
if (port == 0x0000)
ret = dev->apm->cmd; ret = dev->apm->cmd;
else else
ret = dev->apm->stat; ret = dev->apm->stat;
}
acpi_log("[%04X:%08X] APM read: %04X = %02X\n", CS, cpu_state.pc, port, ret); acpi_log("[%04X:%08X] APM read: %04X = %02X\n", CS, cpu_state.pc, port, ret);
@@ -1660,8 +1656,8 @@ acpi_init(const device_t *info)
dev->irq_mode = 2; dev->irq_mode = 2;
dev->apm = device_add(&apm_pci_acpi_device); dev->apm = device_add(&apm_pci_acpi_device);
if (dev->vendor == VEN_ALI) { if (dev->vendor == VEN_ALI) {
pclog("Setting I/O handler at port B1\n"); acpi_log("Setting I/O handler at port B1\n");
io_sethandler(0x00b1, 0x0001, acpi_apm_in, NULL, NULL, acpi_apm_out, NULL, NULL, dev); io_sethandler(0x00b1, 0x0003, acpi_apm_in, NULL, NULL, acpi_apm_out, NULL, NULL, dev);
} else } else
io_sethandler(0x00b2, 0x0002, acpi_apm_in, NULL, NULL, acpi_apm_out, NULL, NULL, dev); io_sethandler(0x00b2, 0x0002, acpi_apm_in, NULL, NULL, acpi_apm_out, NULL, NULL, dev);
} else if (dev->vendor == VEN_VIA) { } else if (dev->vendor == VEN_VIA) {

13
src/chipset/CMakeLists.txt
View File

@@ -13,10 +13,10 @@
# Copyright 2020,2021 David Hrdlička. # Copyright 2020,2021 David Hrdlička.
# #
add_library(chipset OBJECT acc2168.c cs8230.c ali1217.c ali1429.c ali1489.c headland.c add_library(chipset OBJECT acc2168.c cs8230.c ali1217.c ali1429.c ali1489.c ali1531.c ali1543.c
intel_82335.c cs4031.c intel_420ex.c intel_4x0.c intel_sio.c intel_piix.c ../ioapic.c headland.c intel_82335.c cs4031.c intel_420ex.c intel_4x0.c intel_sio.c intel_piix.c
neat.c opti283.c opti291.c opti391.c opti495.c opti822.c opti895.c opti5x7.c scamp.c ../ioapic.c neat.c opti283.c opti291.c opti391.c opti495.c opti822.c opti895.c opti5x7.c
scat.c sis_85c310.c sis_85c4xx.c sis_85c496.c sis_85c50x.c sis_5511.c sis_5571.c scamp.c scat.c sis_85c310.c sis_85c4xx.c sis_85c496.c sis_85c50x.c sis_5511.c sis_5571.c
via_vt82c49x.c via_vt82c505.c sis_85c310.c sis_85c4xx.c sis_85c496.c sis_85c50x.c via_vt82c49x.c via_vt82c505.c sis_85c310.c sis_85c4xx.c sis_85c496.c sis_85c50x.c
gc100.c stpc.c gc100.c stpc.c
via_apollo.c via_pipc.c vl82c480.c wd76c10.c) via_apollo.c via_pipc.c vl82c480.c wd76c10.c)
@@ -25,11 +25,6 @@ if(I450KX)
target_sources(chipset PRIVATE intel_i450kx.c) target_sources(chipset PRIVATE intel_i450kx.c)
endif() endif()
if(M154X)
target_sources(chipset PRIVATE ali1531.c)
target_sources(chipset PRIVATE ali1543.c)
endif()
if(M6117) if(M6117)
target_sources(chipset PRIVATE ali6117.c) target_sources(chipset PRIVATE ali6117.c)
endif() endif()

29
src/chipset/ali1531.c
View File

@@ -34,6 +34,7 @@
#include <86box/chipset.h> #include <86box/chipset.h>
typedef struct ali1531_t typedef struct ali1531_t
{ {
uint8_t pci_conf[256]; uint8_t pci_conf[256];
@@ -42,24 +43,46 @@ typedef struct ali1531_t
} ali1531_t; } ali1531_t;
#ifdef ENABLE_ALI1531_LOG
int ali1531_do_log = ENABLE_ALI1531_LOG;
static void static void
ali1531_smm_recalc(uint8_t val, ali1531_t *dev) ali1531_log(const char *fmt, ...)
{
va_list ap;
if (ali1531_do_log)
{
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define ali1531_log(fmt, ...)
#endif
static void
ali1531_smram_recalc(uint8_t val, ali1531_t *dev)
{ {
smram_disable_all(); smram_disable_all();
if (val & 1) { if (val & 1) {
switch (val & 0x0c) { switch (val & 0x0c) {
case 0x00: case 0x00:
ali1531_log("SMRAM: D0000 -> B0000 (%i)\n", val & 2);
smram_enable(dev->smram, 0xd0000, 0xb0000, 0x10000, val & 2, 1); smram_enable(dev->smram, 0xd0000, 0xb0000, 0x10000, val & 2, 1);
if (val & 0x10) if (val & 0x10)
mem_set_mem_state_smram_ex(1, 0xd0000, 0x10000, 0x02); mem_set_mem_state_smram_ex(1, 0xd0000, 0x10000, 0x02);
break; break;
case 0x04: case 0x04:
ali1531_log("SMRAM: A0000 -> A0000 (%i)\n", val & 2);
smram_enable(dev->smram, 0xa0000, 0xa0000, 0x20000, val & 2, 1); smram_enable(dev->smram, 0xa0000, 0xa0000, 0x20000, val & 2, 1);
if (val & 0x10) if (val & 0x10)
mem_set_mem_state_smram_ex(1, 0xa0000, 0x20000, 0x02); mem_set_mem_state_smram_ex(1, 0xa0000, 0x20000, 0x02);
break; break;
case 0x08: case 0x08:
ali1531_log("SMRAM: 30000 -> B0000 (%i)\n", val & 2);
smram_enable(dev->smram, 0x30000, 0xb0000, 0x10000, val & 2, 1); smram_enable(dev->smram, 0x30000, 0xb0000, 0x10000, val & 2, 1);
if (val & 0x10) if (val & 0x10)
mem_set_mem_state_smram_ex(1, 0x30000, 0x10000, 0x02); mem_set_mem_state_smram_ex(1, 0x30000, 0x10000, 0x02);
@@ -95,7 +118,7 @@ ali1531_shadow_recalc(int cur_reg, ali1531_t *dev)
shadowbios_write |= 1; shadowbios_write |= 1;
} }
pclog("%08X-%08X shadow: R%c, W%c\n", base, base + 0x00003fff, ali1531_log("%08X-%08X shadow: R%c, W%c\n", base, base + 0x00003fff,
(dev->pci_conf[r_reg] & (1 << bit)) ? 'I' : 'E', (dev->pci_conf[w_reg] & (1 << bit)) ? 'I' : 'E'); (dev->pci_conf[r_reg] & (1 << bit)) ? 'I' : 'E', (dev->pci_conf[w_reg] & (1 << bit)) ? 'I' : 'E');
mem_set_mem_state_both(base, 0x00004000, flags); mem_set_mem_state_both(base, 0x00004000, flags);
} }
@@ -181,7 +204,7 @@ ali1531_write(int func, int addr, uint8_t val, void *priv)
case 0x48: /* SMRAM */ case 0x48: /* SMRAM */
dev->pci_conf[addr] = val; dev->pci_conf[addr] = val;
ali1531_smm_recalc((val >> 1) & 7, dev); ali1531_smram_recalc(val, dev);
break; break;
case 0x49: case 0x49:

213
src/chipset/ali1543.c
View File

@@ -50,25 +50,6 @@
#include <86box/chipset.h> #include <86box/chipset.h>
#ifdef ENABLE_ALI1543_LOG
int ali1543_do_log = ENABLE_ALI1543_LOG;
static void
ali1543_log(const char *fmt, ...)
{
va_list ap;
if (ali1543_do_log)
{
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define ali1543_log(fmt, ...)
#endif
typedef struct ali1543_t typedef struct ali1543_t
{ {
uint8_t pci_conf[256], pmu_conf[256], usb_conf[256], ide_conf[256], uint8_t pci_conf[256], pmu_conf[256], usb_conf[256], ide_conf[256],
@@ -103,6 +84,25 @@ int ali1533_irq_routing[16] = { PCI_IRQ_DISABLED, 9, 3, 10,
1, 11, PCI_IRQ_DISABLED, 12, PCI_IRQ_DISABLED, 14, PCI_IRQ_DISABLED, 15 }; 1, 11, PCI_IRQ_DISABLED, 12, PCI_IRQ_DISABLED, 14, PCI_IRQ_DISABLED, 15 };
#ifdef ENABLE_ALI1543_LOG
int ali1543_do_log = ENABLE_ALI1543_LOG;
static void
ali1543_log(const char *fmt, ...)
{
va_list ap;
if (ali1543_do_log)
{
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define ali1543_log(fmt, ...)
#endif
static void static void
ali1533_ddma_handler(ali1543_t *dev) ali1533_ddma_handler(ali1543_t *dev)
{ {
@@ -124,6 +124,9 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
ali1543_log("M1533: dev->pci_conf[%02x] = %02x\n", addr, val); ali1543_log("M1533: dev->pci_conf[%02x] = %02x\n", addr, val);
if (func > 0)
return;
switch (addr) { switch (addr) {
case 0x04: /* Command Register */ case 0x04: /* Command Register */
if (!(dev->pci_conf[0x5f] & 0x08)) if (!(dev->pci_conf[0x5f] & 0x08))
@@ -186,7 +189,7 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
soft_reset_pci = !!(val & 0x80); soft_reset_pci = !!(val & 0x80);
sff_set_irq_level(dev->ide_controller[0], 0, !(val & 0x10)); sff_set_irq_level(dev->ide_controller[0], 0, !(val & 0x10));
sff_set_irq_level(dev->ide_controller[1], 0, !(val & 0x10)); sff_set_irq_level(dev->ide_controller[1], 0, !(val & 0x10));
pclog("INTAJ = IRQ %i\n", ali1533_irq_routing[val & 0x0f]); ali1543_log("INTAJ = IRQ %i\n", ali1533_irq_routing[val & 0x0f]);
pci_set_mirq_routing(PCI_MIRQ0, ali1533_irq_routing[val & 0x0f]); pci_set_mirq_routing(PCI_MIRQ0, ali1533_irq_routing[val & 0x0f]);
pci_set_mirq_routing(PCI_MIRQ2, ali1533_irq_routing[val & 0x0f]); pci_set_mirq_routing(PCI_MIRQ2, ali1533_irq_routing[val & 0x0f]);
break; break;
@@ -221,7 +224,7 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
case 0x4d: /* MBIRQ0(SIRQI#), MBIRQ1(SIRQII#) Interrupt to ISA IRQ routing table */ case 0x4d: /* MBIRQ0(SIRQI#), MBIRQ1(SIRQII#) Interrupt to ISA IRQ routing table */
dev->pci_conf[addr] = val; dev->pci_conf[addr] = val;
pclog("SIRQI = IRQ %i; SIRQII = IRQ %i\n", ali1533_irq_routing[(val >> 4) & 0x0f], ali1533_irq_routing[val & 0x0f]); ali1543_log("SIRQI = IRQ %i; SIRQII = IRQ %i\n", ali1533_irq_routing[(val >> 4) & 0x0f], ali1533_irq_routing[val & 0x0f]);
// pci_set_mirq_routing(PCI_MIRQ0, ali1533_irq_routing[(val >> 4) & 0x0f]); // pci_set_mirq_routing(PCI_MIRQ0, ali1533_irq_routing[(val >> 4) & 0x0f]);
// pci_set_mirq_routing(PCI_MIRQ1, ali1533_irq_routing[val & 0x0f]); // pci_set_mirq_routing(PCI_MIRQ1, ali1533_irq_routing[val & 0x0f]);
break; break;
@@ -258,6 +261,7 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
TODO: What is IDSEL address? */ TODO: What is IDSEL address? */
case 0x58: case 0x58:
dev->pci_conf[addr] = val & 0x7f; dev->pci_conf[addr] = val & 0x7f;
ali1543_log("PCI58: %02X\n", val);
dev->ide_dev_enable = !!(val & 0x40); dev->ide_dev_enable = !!(val & 0x40);
switch (val & 0x30) { switch (val & 0x30) {
case 0x00: case 0x00:
@@ -273,8 +277,7 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
dev->ide_slot = 0x0d; /* A24 = slot 13 */ dev->ide_slot = 0x0d; /* A24 = slot 13 */
break; break;
} }
pclog("IDE slot = %02X (A%0i)\n", dev->ide_slot, dev->ide_slot + 11 - 5); ali1543_log("IDE slot = %02X (A%0i)\n", dev->ide_slot, dev->ide_slot + 11 - 5);
// ali5229_ide_handler(dev);
ali5229_ide_irq_handler(dev); ali5229_ide_irq_handler(dev);
break; break;
@@ -340,7 +343,7 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
dev->pmu_slot = 0x04; /* A15 = slot 04 */ dev->pmu_slot = 0x04; /* A15 = slot 04 */
break; break;
} }
pclog("PMU slot = %02X (A%0i)\n", dev->pmu_slot, dev->pmu_slot + 11 - 5); ali1543_log("PMU slot = %02X (A%0i)\n", dev->pmu_slot, dev->pmu_slot + 11 - 5);
switch (val & 0x03) { switch (val & 0x03) {
case 0x00: case 0x00:
dev->usb_slot = 0x14; /* A31 = slot 20 */ dev->usb_slot = 0x14; /* A31 = slot 20 */
@@ -355,7 +358,7 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
dev->usb_slot = 0x01; /* A12 = slot 01 */ dev->usb_slot = 0x01; /* A12 = slot 01 */
break; break;
} }
pclog("USB slot = %02X (A%0i)\n", dev->usb_slot, dev->usb_slot + 11 - 5); ali1543_log("USB slot = %02X (A%0i)\n", dev->usb_slot, dev->usb_slot + 11 - 5);
break; break;
case 0x73: /* DDMA Base Address */ case 0x73: /* DDMA Base Address */
@@ -373,7 +376,7 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
dev->pci_conf[addr] = val & 0x1f; dev->pci_conf[addr] = val & 0x1f;
sff_set_irq_level(dev->ide_controller[0], 1, !(val & 0x10)); sff_set_irq_level(dev->ide_controller[0], 1, !(val & 0x10));
sff_set_irq_level(dev->ide_controller[1], 1, !(val & 0x10)); sff_set_irq_level(dev->ide_controller[1], 1, !(val & 0x10));
pclog("INTBJ = IRQ %i\n", ali1533_irq_routing[val & 0x0f]); ali1543_log("INTBJ = IRQ %i\n", ali1533_irq_routing[val & 0x0f]);
pci_set_mirq_routing(PCI_MIRQ1, ali1533_irq_routing[val & 0x0f]); pci_set_mirq_routing(PCI_MIRQ1, ali1533_irq_routing[val & 0x0f]);
pci_set_mirq_routing(PCI_MIRQ3, ali1533_irq_routing[val & 0x0f]); pci_set_mirq_routing(PCI_MIRQ3, ali1533_irq_routing[val & 0x0f]);
break; break;
@@ -399,12 +402,16 @@ ali1533_read(int func, int addr, void *priv)
ali1543_t *dev = (ali1543_t *)priv; ali1543_t *dev = (ali1543_t *)priv;
uint8_t ret = 0xff; uint8_t ret = 0xff;
if (func == 0) {
if (((dev->pci_conf[0x42] & 0x80) && (addr >= 0x40)) || ((dev->pci_conf[0x5f] & 8) && (addr == 4))) if (((dev->pci_conf[0x42] & 0x80) && (addr >= 0x40)) || ((dev->pci_conf[0x5f] & 8) && (addr == 4)))
ret = 0x00; ret = 0x00;
else { else {
ret = dev->pci_conf[addr]; ret = dev->pci_conf[addr];
if (addr == 0x41) if (addr == 0x41)
ret |= (keyboard_at_get_mouse_scan() << 2); ret |= (keyboard_at_get_mouse_scan() << 2);
else if (addr == 0x58)
ret = (ret & 0xbf) | (dev->ide_dev_enable ? 0x40 : 0x00);
}
} }
return ret; return ret;
@@ -425,7 +432,7 @@ ali5229_ide_irq_handler(ali1543_t *dev)
if (dev->ide_conf[0x09] & (1 ^ bit)) { if (dev->ide_conf[0x09] & (1 ^ bit)) {
/* Primary IDE is native. */ /* Primary IDE is native. */
pclog("Primary IDE IRQ mode: Native, Native\n"); ali1543_log("Primary IDE IRQ mode: Native, Native\n");
sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 4); sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 4);
sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 4); sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 4);
} else { } else {
@@ -433,25 +440,25 @@ ali5229_ide_irq_handler(ali1543_t *dev)
switch (dev->pci_conf[0x58] & 0x03) { switch (dev->pci_conf[0x58] & 0x03) {
case 0x00: case 0x00:
/* SIRQI, SIRQII */ /* SIRQI, SIRQII */
pclog("Primary IDE IRQ mode: SIRQI, SIRQII\n"); ali1543_log("Primary IDE IRQ mode: SIRQI, SIRQII\n");
sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 2); sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 2);
sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 5); sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 5);
break; break;
case 0x01: case 0x01:
/* IRQ14, IRQ15 */ /* IRQ14, IRQ15 */
pclog("Primary IDE IRQ mode: IRQ14, IRQ15\n"); ali1543_log("Primary IDE IRQ mode: IRQ14, IRQ15\n");
sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0); sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0);
sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 0); sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 0);
break; break;
case 0x02: case 0x02:
/* IRQ14, SIRQII */ /* IRQ14, SIRQII */
pclog("Primary IDE IRQ mode: IRQ14, SIRQII\n"); ali1543_log("Primary IDE IRQ mode: IRQ14, SIRQII\n");
sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0); sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0);
sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 5); sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 5);
break; break;
case 0x03: case 0x03:
/* IRQ14, SIRQI */ /* IRQ14, SIRQI */
pclog("Primary IDE IRQ mode: IRQ14, SIRQI\n"); ali1543_log("Primary IDE IRQ mode: IRQ14, SIRQI\n");
sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0); sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0);
sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 2); sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 2);
break; break;
@@ -462,7 +469,7 @@ ali5229_ide_irq_handler(ali1543_t *dev)
if (dev->ide_conf[0x09] & (4 ^ bit)) { if (dev->ide_conf[0x09] & (4 ^ bit)) {
/* Secondary IDE is native. */ /* Secondary IDE is native. */
pclog("Secondary IDE IRQ mode: Native, Native\n"); ali1543_log("Secondary IDE IRQ mode: Native, Native\n");
sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 4); sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 4);
sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 4); sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 4);
} else { } else {
@@ -470,25 +477,25 @@ ali5229_ide_irq_handler(ali1543_t *dev)
switch (dev->pci_conf[0x58] & 0x03) { switch (dev->pci_conf[0x58] & 0x03) {
case 0x00: case 0x00:
/* SIRQI, SIRQII */ /* SIRQI, SIRQII */
pclog("Secondary IDE IRQ mode: SIRQI, SIRQII\n"); ali1543_log("Secondary IDE IRQ mode: SIRQI, SIRQII\n");
sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 2); sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 2);
sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 5); sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 5);
break; break;
case 0x01: case 0x01:
/* IRQ14, IRQ15 */ /* IRQ14, IRQ15 */
pclog("Secondary IDE IRQ mode: IRQ14, IRQ15\n"); ali1543_log("Secondary IDE IRQ mode: IRQ14, IRQ15\n");
sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0); sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0);
sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 0); sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 0);
break; break;
case 0x02: case 0x02:
/* IRQ14, SIRQII */ /* IRQ14, SIRQII */
pclog("Secondary IDE IRQ mode: IRQ14, SIRQII\n"); ali1543_log("Secondary IDE IRQ mode: IRQ14, SIRQII\n");
sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0); sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0);
sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 5); sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 5);
break; break;
case 0x03: case 0x03:
/* IRQ14, SIRQI */ /* IRQ14, SIRQI */
pclog("Secondary IDE IRQ mode: IRQ14, SIRQI\n"); ali1543_log("Secondary IDE IRQ mode: IRQ14, SIRQI\n");
sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0); sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0);
sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 2); sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 2);
break; break;
@@ -535,33 +542,20 @@ ali5229_ide_handler(ali1543_t *dev)
if (dev->ide_conf[0x52] & 0x10) if (dev->ide_conf[0x52] & 0x10)
ch ^= 8; ch ^= 8;
#if 0 ali1543_log("ali5229_ide_handler(): Disabling primary IDE...\n");
/* Both channels use one port */
if (dev->ide_conf[0x52] & 0x40) {
current_pri_base = current_sec_base;
current_pri_side = current_sec_side;
}
if (dev->ide_conf[0x52] & 0x20) {
current_sec_base = current_pri_base;
current_sec_side = current_pri_side;
}
#endif
pclog("ali5229_ide_handler(): Disabling primary IDE...\n");
ide_pri_disable(); ide_pri_disable();
pclog("ali5229_ide_handler(): Disabling secondary IDE...\n"); ali1543_log("ali5229_ide_handler(): Disabling secondary IDE...\n");
ide_sec_disable(); ide_sec_disable();
if ((dev->ide_conf[0x04] & 0x01) && (dev->ide_conf[0x50] & 0x01)) { if (dev->ide_conf[0x04] & 0x01) {
/* Primary Channel Setup */ /* Primary Channel Setup */
if (dev->ide_conf[0x09] & 0x20) { if (dev->ide_conf[0x09] & 0x20) {
pclog("ali5229_ide_handler(): Primary IDE base now %04X...\n", current_pri_base); ali1543_log("ali5229_ide_handler(): Primary IDE base now %04X...\n", current_pri_base);
ide_set_base(0, current_pri_base); ide_set_base(0, current_pri_base);
pclog("ali5229_ide_handler(): Primary IDE side now %04X...\n", current_pri_side); ali1543_log("ali5229_ide_handler(): Primary IDE side now %04X...\n", current_pri_side);
ide_set_side(0, current_pri_side); ide_set_side(0, current_pri_side);
pclog("ali5229_ide_handler(): Enabling primary IDE...\n"); ali1543_log("ali5229_ide_handler(): Enabling primary IDE...\n");
ide_pri_enable(); ide_pri_enable();
sff_bus_master_handler(dev->ide_controller[0], dev->ide_conf[0x04] & 0x01, ((dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8)) + (0 ^ ch)); sff_bus_master_handler(dev->ide_controller[0], dev->ide_conf[0x04] & 0x01, ((dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8)) + (0 ^ ch));
@@ -570,12 +564,12 @@ ali5229_ide_handler(ali1543_t *dev)
/* Secondary Channel Setup */ /* Secondary Channel Setup */
if (dev->ide_conf[0x09] & 0x10) { if (dev->ide_conf[0x09] & 0x10) {
pclog("ali5229_ide_handler(): Secondary IDE base now %04X...\n", current_sec_base); ali1543_log("ali5229_ide_handler(): Secondary IDE base now %04X...\n", current_sec_base);
ide_set_base(1, current_sec_base); ide_set_base(1, current_sec_base);
pclog("ali5229_ide_handler(): Secondary IDE side now %04X...\n", current_sec_side); ali1543_log("ali5229_ide_handler(): Secondary IDE side now %04X...\n", current_sec_side);
ide_set_side(1, current_sec_side); ide_set_side(1, current_sec_side);
pclog("ali5229_ide_handler(): Enabling secondary IDE...\n"); ali1543_log("ali5229_ide_handler(): Enabling secondary IDE...\n");
ide_sec_enable(); ide_sec_enable();
sff_bus_master_handler(dev->ide_controller[1], dev->ide_conf[0x04] & 0x01, (((dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8))) + (8 ^ ch)); sff_bus_master_handler(dev->ide_controller[1], dev->ide_conf[0x04] & 0x01, (((dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8))) + (8 ^ ch));
@@ -623,7 +617,7 @@ ali5229_chip_reset(ali1543_t *dev)
dev->ide_conf[0x67] = 0x01; dev->ide_conf[0x67] = 0x01;
dev->ide_conf[0x78] = 0x21; dev->ide_conf[0x78] = 0x21;
ali5229_write(0, 0x04, 0x00, dev); ali5229_write(0, 0x04, 0x01, dev);
ali5229_write(0, 0x10, 0xf1, dev); ali5229_write(0, 0x10, 0xf1, dev);
ali5229_write(0, 0x11, 0x01, dev); ali5229_write(0, 0x11, 0x01, dev);
ali5229_write(0, 0x14, 0xf5, dev); ali5229_write(0, 0x14, 0xf5, dev);
@@ -635,10 +629,12 @@ ali5229_chip_reset(ali1543_t *dev)
ali5229_write(0, 0x20, 0x01, dev); ali5229_write(0, 0x20, 0x01, dev);
ali5229_write(0, 0x21, 0xf0, dev); ali5229_write(0, 0x21, 0xf0, dev);
ali5229_write(0, 0x4d, 0x00, dev); ali5229_write(0, 0x4d, 0x00, dev);
dev->ide_conf[0x09] = 0xfa;
ali5229_write(0, 0x09, 0xfa, dev); ali5229_write(0, 0x09, 0xfa, dev);
ali5229_write(0, 0x50, 0x00, dev);
ali5229_write(0, 0x52, 0x00, dev); ali5229_write(0, 0x52, 0x00, dev);
ali5229_write(0, 0x50, 0x00, dev);
sff_set_slot(dev->ide_controller[0], dev->ide_slot); sff_set_slot(dev->ide_controller[0], dev->ide_slot);
sff_set_slot(dev->ide_controller[1], dev->ide_slot); sff_set_slot(dev->ide_controller[1], dev->ide_slot);
sff_bus_master_reset(dev->ide_controller[0], (dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8)); sff_bus_master_reset(dev->ide_controller[0], (dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8));
@@ -653,16 +649,29 @@ ali5229_write(int func, int addr, uint8_t val, void *priv)
ali1543_t *dev = (ali1543_t *)priv; ali1543_t *dev = (ali1543_t *)priv;
ali1543_log("M5229: dev->ide_conf[%02x] = %02x\n", addr, val); ali1543_log("M5229: dev->ide_conf[%02x] = %02x\n", addr, val);
if (func > 0)
return;
if (!dev->ide_dev_enable) if (!dev->ide_dev_enable)
return; return;
switch (addr) { switch (addr) {
case 0x04: /* COM - Command Register */ case 0x04: /* COM - Command Register */
dev->ide_conf[addr] = val; ali1543_log("IDE04: %02X\n", val);
dev->ide_conf[addr] = val & 0x45;
ali5229_ide_handler(dev); ali5229_ide_handler(dev);
break; break;
case 0x05:
dev->ide_conf[addr] = val & 0x01;
break;
case 0x07:
dev->ide_conf[addr] &= ~(val & 0xf1);
break;
case 0x09: /* Control */ case 0x09: /* Control */
ali1543_log("IDE09: %02X\n", val);
#ifdef M1543_C #ifdef M1543_C
val &= ~(dev->ide_conf[0x43]); val &= ~(dev->ide_conf[0x43]);
val |= (dev->ide_conf[addr] & dev->ide_conf[0x43]); val |= (dev->ide_conf[addr] & dev->ide_conf[0x43]);
@@ -716,7 +725,9 @@ ali5229_write(int func, int addr, uint8_t val, void *priv)
break; break;
case 0x50: /* Configuration */ case 0x50: /* Configuration */
ali1543_log("IDE50: %02X\n", val);
dev->ide_conf[addr] = val & 0x2b; dev->ide_conf[addr] = val & 0x2b;
dev->ide_dev_enable = !!(val & 0x01);
break; break;
case 0x51: case 0x51:
@@ -774,10 +785,12 @@ ali5229_read(int func, int addr, void *priv)
ali1543_t *dev = (ali1543_t *)priv; ali1543_t *dev = (ali1543_t *)priv;
uint8_t ret = 0xff; uint8_t ret = 0xff;
if (dev->ide_dev_enable) { if (dev->ide_dev_enable && (func == 0)) {
ret = dev->ide_conf[addr]; ret = dev->ide_conf[addr];
if ((addr == 0x09) && !(dev->ide_conf[0x50] & 0x02)) if ((addr == 0x09) && !(dev->ide_conf[0x50] & 0x02))
ret &= 0x0f; ret &= 0x0f;
else if (addr == 0x50)
ret = (ret & 0xfe) | (dev->ide_dev_enable ? 0x01 : 0x00);
else if (addr == 0x75) else if (addr == 0x75)
ret = ide_read_ali_75(); ret = ide_read_ali_75();
else if (addr == 0x76) else if (addr == 0x76)
@@ -794,6 +807,9 @@ ali5237_write(int func, int addr, uint8_t val, void *priv)
ali1543_t *dev = (ali1543_t *)priv; ali1543_t *dev = (ali1543_t *)priv;
ali1543_log("M5237: dev->usb_conf[%02x] = %02x\n", addr, val); ali1543_log("M5237: dev->usb_conf[%02x] = %02x\n", addr, val);
if (func > 0)
return;
if (!dev->usb_dev_enable) if (!dev->usb_dev_enable)
return; return;
@@ -845,7 +861,7 @@ ali5237_read(int func, int addr, void *priv)
ali1543_t *dev = (ali1543_t *)priv; ali1543_t *dev = (ali1543_t *)priv;
uint8_t ret = 0xff; uint8_t ret = 0xff;
if (dev->usb_dev_enable) if (dev->usb_dev_enable && (func == 0))
ret = dev->usb_conf[addr]; ret = dev->usb_conf[addr];
return ret; return ret;
@@ -858,11 +874,18 @@ ali7101_write(int func, int addr, uint8_t val, void *priv)
ali1543_t *dev = (ali1543_t *)priv; ali1543_t *dev = (ali1543_t *)priv;
ali1543_log("M7101: dev->pmu_conf[%02x] = %02x\n", addr, val); ali1543_log("M7101: dev->pmu_conf[%02x] = %02x\n", addr, val);
if (func > 0)
return;
if (!dev->pmu_dev_enable) if (!dev->pmu_dev_enable)
return; return;
if ((dev->pmu_conf[0xc9] & 0x01) && (addr >= 0x40) && (addr != 0xc9))
return;
switch (addr) { switch (addr) {
case 0x04: /* Enable PMU */ case 0x04: /* Enable PMU */
ali1543_log("PMU04: %02X\n", val);
dev->pmu_conf[addr] = val & 0x01; dev->pmu_conf[addr] = val & 0x01;
acpi_update_io_mapping(dev->acpi, (dev->pmu_conf[0x11] << 8) | (dev->pmu_conf[0x10] & 0xc0), dev->pmu_conf[0x04] & 1); acpi_update_io_mapping(dev->acpi, (dev->pmu_conf[0x11] << 8) | (dev->pmu_conf[0x10] & 0xc0), dev->pmu_conf[0x04] & 1);
smbus_piix4_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xe0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1)); smbus_piix4_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xe0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1));
@@ -904,9 +927,8 @@ ali7101_write(int func, int addr, uint8_t val, void *priv)
break; break;
case 0x41: case 0x41:
dev->pmu_conf[addr] = val & 0x10; dev->pmu_conf[addr] = val & 0x10;
pclog("PMU41: %02X\n", val); ali1543_log("PMU41: %02X\n", val);
// apm_set_do_smi(dev->acpi->apm, (dev->pmu_conf[0x77] & 0x08) && (dev->pmu_conf[0x41] & 0x10)); apm_set_do_smi(dev->acpi->apm, (dev->pmu_conf[0x77] & 0x08) && (dev->pmu_conf[0x41] & 0x10));
apm_set_do_smi(dev->acpi->apm, dev->pmu_conf[0x41] & 0x10);
break; break;
/* TODO: Is the status R/W or R/WC? */ /* TODO: Is the status R/W or R/WC? */
@@ -1031,8 +1053,8 @@ ali7101_write(int func, int addr, uint8_t val, void *priv)
/* TODO: If bit 1 is clear, then status bit is set even if SMI is disabled. */ /* TODO: If bit 1 is clear, then status bit is set even if SMI is disabled. */
dev->pmu_conf[addr] = val; dev->pmu_conf[addr] = val;
pic_set_smi_irq_mask(8, (dev->pmu_conf[0x77] & 0x08) && (dev->pmu_conf[0x40] & 0x03)); pic_set_smi_irq_mask(8, (dev->pmu_conf[0x77] & 0x08) && (dev->pmu_conf[0x40] & 0x03));
pclog("PMU77: %02X\n", val); ali1543_log("PMU77: %02X\n", val);
// apm_set_do_smi(dev->acpi->apm, (dev->pmu_conf[0x77] & 0x08) && (dev->pmu_conf[0x41] & 0x10)); apm_set_do_smi(dev->acpi->apm, (dev->pmu_conf[0x77] & 0x08) && (dev->pmu_conf[0x41] & 0x10));
break; break;
case 0x78: case 0x78:
@@ -1172,7 +1194,10 @@ ali7101_read(int func, int addr, void *priv)
ali1543_t *dev = (ali1543_t *)priv; ali1543_t *dev = (ali1543_t *)priv;
uint8_t ret = 0xff; uint8_t ret = 0xff;
if (dev->pmu_dev_enable) { if (dev->pmu_dev_enable && (func == 0)) {
if ((dev->pmu_conf[0xc9] & 0x01) && (addr >= 0x40) && (addr != 0xc9))
return 0xff;
/* TODO: C4, C5 = GPIREG (masks: 0D, 0E) */ /* TODO: C4, C5 = GPIREG (masks: 0D, 0E) */
if (addr == 0x43) if (addr == 0x43)
ret = acpi_ali_soft_smi_status_read(dev->acpi) ? 0x10 : 0x00; ret = acpi_ali_soft_smi_status_read(dev->acpi) ? 0x10 : 0x00;
@@ -1225,7 +1250,7 @@ ali1533_sio_fdc_handler(ali1543_t *dev)
fdc_remove(dev->fdc_controller); fdc_remove(dev->fdc_controller);
if (dev->device_regs[0][0x30] & 1) { if (dev->device_regs[0][0x30] & 1) {
pclog("New FDC base address: %04X\n", dev->device_regs[0][0x61] | (dev->device_regs[0][0x60] << 8)); ali1543_log("New FDC base address: %04X\n", dev->device_regs[0][0x61] | (dev->device_regs[0][0x60] << 8));
fdc_set_base(dev->fdc_controller, dev->device_regs[0][0x61] | (dev->device_regs[0][0x60] << 8)); fdc_set_base(dev->fdc_controller, dev->device_regs[0][0x61] | (dev->device_regs[0][0x60] << 8));
fdc_set_irq(dev->fdc_controller, dev->device_regs[0][0x70] & 0xf); fdc_set_irq(dev->fdc_controller, dev->device_regs[0][0x70] & 0xf);
fdc_set_dma_ch(dev->fdc_controller, dev->device_regs[0][0x74] & 0x07); fdc_set_dma_ch(dev->fdc_controller, dev->device_regs[0][0x74] & 0x07);
@@ -1348,26 +1373,10 @@ ali1543_reset(void *priv)
ali1543_t *dev = (ali1543_t *)priv; ali1543_t *dev = (ali1543_t *)priv;
int i; int i;
/* M1533 */ /* Temporarily enable everything. Register writes will disable the devices. */
dev->pci_conf[0x00] = 0xb9; dev->ide_dev_enable = 1;
dev->pci_conf[0x01] = 0x10; dev->usb_dev_enable = 1;
dev->pci_conf[0x02] = 0x33; dev->pmu_dev_enable = 1;
dev->pci_conf[0x03] = 0x15;
dev->pci_conf[0x04] = 0x0f;
dev->pci_conf[0x07] = 0x02;
dev->pci_conf[0x0a] = 0x01;
dev->pci_conf[0x0b] = 0x06;
ali1533_write(0, 0x48, 0x00, dev); // Disables all IRQ's
ali1533_write(0, 0x44, 0x00, dev);
ali1533_write(0, 0x4d, 0x00, dev);
ali1533_write(0, 0x53, 0x00, dev);
ali1533_write(0, 0x58, 0x00, dev);
ali1533_write(0, 0x5f, 0x00, dev);
ali1533_write(0, 0x72, 0x00, dev);
ali1533_write(0, 0x74, 0x00, dev);
ali1533_write(0, 0x75, 0x00, dev);
ali1533_write(0, 0x76, 0x00, dev);
/* M5229 */ /* M5229 */
ali5229_chip_reset(dev); ali5229_chip_reset(dev);
@@ -1427,6 +1436,28 @@ ali1543_reset(void *priv)
ali7101_write(0, 0xc3, 0x00, dev); ali7101_write(0, 0xc3, 0x00, dev);
ali7101_write(0, 0xe0, 0x00, dev); ali7101_write(0, 0xe0, 0x00, dev);
/* Do the bridge last due to device deactivations. */
/* M1533 */
dev->pci_conf[0x00] = 0xb9;
dev->pci_conf[0x01] = 0x10;
dev->pci_conf[0x02] = 0x33;
dev->pci_conf[0x03] = 0x15;
dev->pci_conf[0x04] = 0x0f;
dev->pci_conf[0x07] = 0x02;
dev->pci_conf[0x0a] = 0x01;
dev->pci_conf[0x0b] = 0x06;
ali1533_write(0, 0x48, 0x00, dev); // Disables all IRQ's
ali1533_write(0, 0x44, 0x00, dev);
ali1533_write(0, 0x4d, 0x00, dev);
ali1533_write(0, 0x53, 0x00, dev);
ali1533_write(0, 0x58, 0x00, dev);
ali1533_write(0, 0x5f, 0x00, dev);
ali1533_write(0, 0x72, 0x00, dev);
ali1533_write(0, 0x74, 0x00, dev);
ali1533_write(0, 0x75, 0x00, dev);
ali1533_write(0, 0x76, 0x00, dev);
/* M1543 Super I/O */ /* M1543 Super I/O */
memset(dev->sio_regs, 0x00, sizeof(dev->sio_regs)); memset(dev->sio_regs, 0x00, sizeof(dev->sio_regs));
for (i = 0; i < 8; i++) for (i = 0; i < 8; i++)
@@ -1464,6 +1495,8 @@ ali1543_reset(void *priv)
ali1533_sio_uart_handler(0, dev); ali1533_sio_uart_handler(0, dev);
ali1533_sio_uart_handler(1, dev); ali1533_sio_uart_handler(1, dev);
ali1533_sio_lpt_handler(dev); ali1533_sio_lpt_handler(dev);
unmask_a20_in_smm = 1;
} }

1
src/cpu/386_common.c
View File

@@ -306,7 +306,6 @@ enum SMMRAM_Fields_AMD_K {
}; };
#define ENABLE_386_COMMON_LOG 1
#ifdef ENABLE_386_COMMON_LOG #ifdef ENABLE_386_COMMON_LOG
int x386_common_do_log = ENABLE_386_COMMON_LOG; int x386_common_do_log = ENABLE_386_COMMON_LOG;

1
src/device/postcard.c
View File

@@ -40,7 +40,6 @@ static char postcard_str[UISTR_LEN]; /* UI output string */
extern void ui_sb_bugui(char *__str); extern void ui_sb_bugui(char *__str);
#define ENABLE_POSTCARD_LOG 1
#ifdef ENABLE_POSTCARD_LOG #ifdef ENABLE_POSTCARD_LOG
int postcard_do_log = ENABLE_POSTCARD_LOG; int postcard_do_log = ENABLE_POSTCARD_LOG;

10
src/disk/hdc_ide_sff8038i.c
View File

@@ -501,24 +501,24 @@ sff_set_irq_mode(sff8038i_t *dev, int channel, int irq_mode)
case 0: case 0:
default: default:
/* Legacy IRQ mode. */ /* Legacy IRQ mode. */
pclog("[%08X] Setting channel %i to legacy IRQ %i\n", dev, channel, 14 + channel); sff_log("[%08X] Setting channel %i to legacy IRQ %i\n", dev, channel, 14 + channel);
break; break;
case 1: case 1:
/* Native PCI IRQ mode with interrupt pin. */ /* Native PCI IRQ mode with interrupt pin. */
pclog("[%08X] Setting channel %i to native PCI INT%c\n", dev, channel, '@' + dev->irq_pin); sff_log("[%08X] Setting channel %i to native PCI INT%c\n", dev, channel, '@' + dev->irq_pin);
break; break;
case 2: case 2:
case 5: case 5:
/* MIRQ 0 or 1. */ /* MIRQ 0 or 1. */
pclog("[%08X] Setting channel %i to PCI MIRQ%i\n", dev, channel, irq_mode & 1); sff_log("[%08X] Setting channel %i to PCI MIRQ%i\n", dev, channel, irq_mode & 1);
break; break;
case 3: case 3:
/* Native PCI IRQ mode with specified interrupt line. */ /* Native PCI IRQ mode with specified interrupt line. */
pclog("[%08X] Setting channel %i to native PCI IRQ %i\n", dev, channel, dev->irq_line); sff_log("[%08X] Setting channel %i to native PCI IRQ %i\n", dev, channel, dev->irq_line);
break; break;
case 4: case 4:
/* ALi Aladdin Native PCI INTAJ mode. */ /* ALi Aladdin Native PCI INTAJ mode. */
pclog("[%08X] Setting channel %i to INT%cJ\n", dev, channel, 'A' + channel); sff_log("[%08X] Setting channel %i to INT%cJ\n", dev, channel, 'A' + channel);
break; break;
} }
} }

2
src/include/86box/chipset.h
View File

@@ -25,10 +25,8 @@ extern const device_t acc2168_device;
extern const device_t ali1217_device; extern const device_t ali1217_device;
extern const device_t ali1429_device; extern const device_t ali1429_device;
extern const device_t ali1489_device; extern const device_t ali1489_device;
#if defined(DEV_BRANCH) && defined(USE_M154X)
extern const device_t ali1531_device; extern const device_t ali1531_device;
extern const device_t ali1543_device; extern const device_t ali1543_device;
#endif
#if defined(DEV_BRANCH) && defined(USE_M6117) #if defined(DEV_BRANCH) && defined(USE_M6117)
extern const device_t ali6117d_device; extern const device_t ali6117d_device;
#endif #endif

2
src/include/86box/machine.h
View File

@@ -493,10 +493,8 @@ extern int machine_at_ficpa2012_init(const machine_t *);
extern int machine_at_r534f_init(const machine_t *); extern int machine_at_r534f_init(const machine_t *);
extern int machine_at_ms5146_init(const machine_t *); extern int machine_at_ms5146_init(const machine_t *);
#if defined(DEV_BRANCH) && defined(USE_M154X)
extern int machine_at_m560_init(const machine_t *); extern int machine_at_m560_init(const machine_t *);
extern int machine_at_ms5164_init(const machine_t *); extern int machine_at_ms5164_init(const machine_t *);
#endif
/* m_at_sockets7.c */ /* m_at_sockets7.c */
extern int machine_at_ax59pro_init(const machine_t *); extern int machine_at_ax59pro_init(const machine_t *);

2
src/machine/m_at_socket7.c
View File

@@ -899,7 +899,6 @@ machine_at_ms5146_init(const machine_t *model)
} }
#if defined(DEV_BRANCH) && defined(USE_M154X)
int int
machine_at_m560_init(const machine_t *model) machine_at_m560_init(const machine_t *model)
{ {
@@ -966,4 +965,3 @@ machine_at_ms5164_init(const machine_t *model)
return ret; return ret;
} }
#endif

2
src/machine/machine_table.c
View File

@@ -661,12 +661,10 @@ const machine_t machines[] = {
{ "[SiS 5571] MSI MS-5146", "ms5146", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2500, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 262144, 8192, 127, machine_at_ms5146_init, NULL }, { "[SiS 5571] MSI MS-5146", "ms5146", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2500, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 262144, 8192, 127, machine_at_ms5146_init, NULL },
/* ALi ALADDiN IV */ /* ALi ALADDiN IV */
#if defined(DEV_BRANCH) && defined(USE_M154X)
/* Has the ALi M1543 southbridge with on-chip KBC. */ /* Has the ALi M1543 southbridge with on-chip KBC. */
{ "[ALi ALADDiN IV] PC Chips M560", "m560", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 83333333, 2500, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 262144, 8192, 255, machine_at_m560_init, NULL }, { "[ALi ALADDiN IV] PC Chips M560", "m560", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 83333333, 2500, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 262144, 8192, 255, machine_at_m560_init, NULL },
/* Has the ALi M1543 southbridge with on-chip KBC. */ /* Has the ALi M1543 southbridge with on-chip KBC. */
{ "[ALi ALADDiN IV] MSI MS-5164", "ms5164", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 60000000, 66666667, 2100, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 262144, 8192, 255, machine_at_ms5164_init, NULL }, { "[ALi ALADDiN IV] MSI MS-5164", "ms5164", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 60000000, 66666667, 2100, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 262144, 8192, 255, machine_at_ms5164_init, NULL },
#endif
/* Super Socket 7 machines */ /* Super Socket 7 machines */
/* Apollo MVP3 */ /* Apollo MVP3 */

3
src/usb.c
View File

@@ -146,6 +146,9 @@ ohci_mmio_read(uint32_t addr, void *p)
ret = dev->ohci_mmio[addr]; ret = dev->ohci_mmio[addr];
if (addr == 0x101)
ret = (ret & 0xfe) | (!!mem_a20_key);
return ret; return ret;
} }

19
src/win/Makefile.mingw
View File

@@ -48,9 +48,6 @@ ifeq ($(DEV_BUILD), y)
ifndef I450KX ifndef I450KX
I450KX := y I450KX := y
endif endif
ifndef M154X
M154X := y
endif
ifndef LASERXT ifndef LASERXT
LASERXT := y LASERXT := y
endif endif
@@ -78,9 +75,6 @@ ifeq ($(DEV_BUILD), y)
ifndef SIO_DETECT ifndef SIO_DETECT
SIO_DETECT := y SIO_DETECT := y
endif endif
ifndef M154X
M154X := y
endif
ifndef M6117 ifndef M6117
M6117 := y M6117 := y
endif endif
@@ -127,9 +121,6 @@ else
ifndef LASERXT ifndef LASERXT
LASERXT := n LASERXT := n
endif endif
ifndef M154X
M154X := n
endif
ifndef MGA ifndef MGA
MGA := n MGA := n
endif endif
@@ -154,9 +145,6 @@ else
ifndef SIO_DETECT ifndef SIO_DETECT
SIO_DETECT := n SIO_DETECT := n
endif endif
ifndef M154X
M154X := n
endif
ifndef M6117 ifndef M6117
M6117 := n M6117 := n
endif endif
@@ -563,11 +551,6 @@ OPTS += -DUSE_SIO_DETECT
DEVBROBJ += sio_detect.o DEVBROBJ += sio_detect.o
endif endif
ifeq ($(M154X), y)
OPTS += -DUSE_M154X
DEVBROBJ += ali1531.o ali1543.o
endif
ifeq ($(M6117), y) ifeq ($(M6117), y)
OPTS += -DUSE_M6117 OPTS += -DUSE_M6117
DEVBROBJ += ali6117.o DEVBROBJ += ali6117.o
@@ -618,7 +601,7 @@ CPUOBJ := cpu.o cpu_table.o fpu.o x86.o \
CHIPSETOBJ := acc2168.o \ CHIPSETOBJ := acc2168.o \
cs4031.o cs8230.o \ cs4031.o cs8230.o \
ali1217.o ali1429.o ali1489.o \ ali1217.o ali1429.o ali1489.o ali1531.o ali1543.o \
gc100.o headland.o \ gc100.o headland.o \
intel_82335.o intel_420ex.o intel_4x0.o intel_sio.o intel_piix.o ioapic.o \ intel_82335.o intel_420ex.o intel_4x0.o intel_sio.o intel_piix.o ioapic.o \
neat.o \ neat.o \